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Merge git://git.denx.de/u-boot-uniphier

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This commit is contained in:
Tom Rini
2018-03-15 09:58:30 -04:00
parent 3fa9bc7969 46820e3f67
commit 735f397c14
10 changed files with 146 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/uniphier-ld11.dtsi
View File

@@ -352,6 +352,7 @@
<&mio_clk 12>; <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>; <&mio_rst 12>;
has-transaction-translator;
}; };
usb1: usb@5a810100 { usb1: usb@5a810100 {
@@ -365,6 +366,7 @@
<&mio_clk 13>; <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>; <&mio_rst 13>;
has-transaction-translator;
}; };
usb2: usb@5a820100 { usb2: usb@5a820100 {
@@ -378,6 +380,7 @@
<&mio_clk 14>; <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>; <&mio_rst 14>;
has-transaction-translator;
}; };
mioctrl@5b3e0000 { mioctrl@5b3e0000 {

21
arch/arm/dts/uniphier-ld4.dtsi
View File

@@ -276,6 +276,7 @@
<&mio_clk 12>; <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>; <&mio_rst 12>;
has-transaction-translator;
}; };
usb1: usb@5a810100 { usb1: usb@5a810100 {
@@ -289,6 +290,7 @@
<&mio_clk 13>; <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>; <&mio_rst 13>;
has-transaction-translator;
}; };
usb2: usb@5a820100 { usb2: usb@5a820100 {
@@ -302,6 +304,7 @@
<&mio_clk 14>; <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>; <&mio_rst 14>;
has-transaction-translator;
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
@@ -314,6 +317,24 @@
}; };
}; };
soc-glue@5f900000 {
compatible = "socionext,uniphier-ld4-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@130 {
compatible = "socionext,uniphier-efuse";
reg = <0x130 0x8>;
};
};
timer@60000200 { timer@60000200 {
compatible = "arm,cortex-a9-global-timer"; compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>; reg = <0x60000200 0x20>;

4
arch/arm/dts/uniphier-pro4-ref.dts
View File

@@ -91,3 +91,7 @@
&usb1 { &usb1 {
status = "okay"; status = "okay";
}; };
&nand {
status = "okay";
};

25
arch/arm/dts/uniphier-pro4.dtsi
View File

@@ -327,6 +327,7 @@
<&mio_clk 12>; <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>; <&mio_rst 12>;
has-transaction-translator;
}; };
usb3: usb@5a810100 { usb3: usb@5a810100 {
@@ -340,6 +341,7 @@
<&mio_clk 13>; <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>; <&mio_rst 13>;
has-transaction-translator;
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
@@ -352,6 +354,29 @@
}; };
}; };
soc-glue@5f900000 {
compatible = "socionext,uniphier-pro4-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@130 {
compatible = "socionext,uniphier-efuse";
reg = <0x130 0x8>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x14>;
};
};
aidet: aidet@5fc20000 { aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro4-aidet"; compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;

33
arch/arm/dts/uniphier-pro5.dtsi
View File

@@ -359,6 +359,39 @@
}; };
}; };
soc-glue@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@130 {
compatible = "socionext,uniphier-efuse";
reg = <0x130 0x8>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x28>;
};
efuse@300 {
compatible = "socionext,uniphier-efuse";
reg = <0x300 0x14>;
};
efuse@400 {
compatible = "socionext,uniphier-efuse";
reg = <0x400 0x8>;
};
};
aidet: aidet@5fc20000 { aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pro5-aidet"; compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;

18
arch/arm/dts/uniphier-pxs2.dtsi
View File

@@ -415,6 +415,24 @@
}; };
}; };
soc-glue@5f900000 {
compatible = "socionext,uniphier-pxs2-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x58>;
};
};
aidet: aidet@5fc20000 { aidet: aidet@5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet"; compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>; reg = <0x5fc20000 0x200>;

8
arch/arm/dts/uniphier-pxs3-ref.dts
View File

@@ -45,6 +45,14 @@
status = "okay"; status = "okay";
}; };
&serial2 {
status = "okay";
};
&serial3 {
status = "okay";
};
&gpio { &gpio {
xirq4 { xirq4 {
gpio-hog; gpio-hog;

4
arch/arm/dts/uniphier-pxs3.dtsi
View File

@@ -203,8 +203,8 @@
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 0>, gpio-ranges = <&pinctrl 0 0 0>,
<&pinctrl 96 0 0>, <&pinctrl 104 0 0>,
<&pinctrl 160 0 0>; <&pinctrl 168 0 0>;
gpio-ranges-group-names = "gpio_range0", gpio-ranges-group-names = "gpio_range0",
"gpio_range1", "gpio_range1",
"gpio_range2"; "gpio_range2";

21
arch/arm/dts/uniphier-sld8.dtsi
View File

@@ -280,6 +280,7 @@
<&mio_clk 12>; <&mio_clk 12>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>,
<&mio_rst 12>; <&mio_rst 12>;
has-transaction-translator;
}; };
usb1: usb@5a810100 { usb1: usb@5a810100 {
@@ -293,6 +294,7 @@
<&mio_clk 13>; <&mio_clk 13>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>,
<&mio_rst 13>; <&mio_rst 13>;
has-transaction-translator;
}; };
usb2: usb@5a820100 { usb2: usb@5a820100 {
@@ -306,6 +308,7 @@
<&mio_clk 14>; <&mio_clk 14>;
resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>,
<&mio_rst 14>; <&mio_rst 14>;
has-transaction-translator;
}; };
soc-glue@5f800000 { soc-glue@5f800000 {
@@ -318,6 +321,24 @@
}; };
}; };
soc-glue@5f900000 {
compatible = "socionext,uniphier-sld8-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5f900000 0x2000>;
efuse@100 {
compatible = "socionext,uniphier-efuse";
reg = <0x100 0x28>;
};
efuse@200 {
compatible = "socionext,uniphier-efuse";
reg = <0x200 0x14>;
};
};
timer@60000200 { timer@60000200 {
compatible = "arm,cortex-a9-global-timer"; compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>; reg = <0x60000200 0x20>;

22
include/configs/uniphier.h
View File

@@ -87,7 +87,7 @@
#define CONFIG_GATEWAYIP 192.168.11.1 #define CONFIG_GATEWAYIP 192.168.11.1
#define CONFIG_NETMASK 255.255.255.0 #define CONFIG_NETMASK 255.255.255.0
#define CONFIG_LOADADDR 0x84000000 #define CONFIG_LOADADDR 0x85000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_BOOTM_LEN (32 << 20) #define CONFIG_SYS_BOOTM_LEN (32 << 20)
@@ -115,7 +115,7 @@
#define CONFIG_BOOTFILE "fitImage" #define CONFIG_BOOTFILE "fitImage"
#define LINUXBOOT_ENV_SETTINGS \ #define LINUXBOOT_ENV_SETTINGS \
"fit_addr=0x00100000\0" \ "fit_addr=0x00100000\0" \
"fit_addr_r=0x84100000\0" \ "fit_addr_r=0x85100000\0" \
"fit_size=0x00f00000\0" \ "fit_size=0x00f00000\0" \
"norboot=setexpr fit_addr $nor_base + $fit_addr &&" \ "norboot=setexpr fit_addr $nor_base + $fit_addr &&" \
"bootm $fit_addr\0" \ "bootm $fit_addr\0" \
@@ -128,7 +128,7 @@
#ifdef CONFIG_ARM64 #ifdef CONFIG_ARM64
#define CONFIG_BOOTFILE "Image.gz" #define CONFIG_BOOTFILE "Image.gz"
#define LINUXBOOT_CMD "booti" #define LINUXBOOT_CMD "booti"
#define KERNEL_ADDR_LOAD "kernel_addr_load=0x84200000\0" #define KERNEL_ADDR_LOAD "kernel_addr_load=0x85200000\0"
#define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0" #define KERNEL_ADDR_R "kernel_addr_r=0x82080000\0"
#else #else
#define CONFIG_BOOTFILE "zImage" #define CONFIG_BOOTFILE "zImage"
@@ -138,15 +138,15 @@
#endif #endif
#define LINUXBOOT_ENV_SETTINGS \ #define LINUXBOOT_ENV_SETTINGS \
"fdt_addr=0x00100000\0" \ "fdt_addr=0x00100000\0" \
"fdt_addr_r=0x84100000\0" \ "fdt_addr_r=0x85100000\0" \
"fdt_size=0x00008000\0" \ "fdt_size=0x00008000\0" \
"kernel_addr=0x00200000\0" \ "kernel_addr=0x00200000\0" \
KERNEL_ADDR_LOAD \ KERNEL_ADDR_LOAD \
KERNEL_ADDR_R \ KERNEL_ADDR_R \
"kernel_size=0x00800000\0" \ "kernel_size=0x00e00000\0" \
"ramdisk_addr=0x00a00000\0" \ "ramdisk_addr=0x01000000\0" \
"ramdisk_addr_r=0x84a00000\0" \ "ramdisk_addr_r=0x86000000\0" \
"ramdisk_size=0x00600000\0" \ "ramdisk_size=0x00800000\0" \
"ramdisk_file=rootfs.cpio.uboot\0" \ "ramdisk_file=rootfs.cpio.uboot\0" \
"boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \ "boot_common=setexpr bootm_low $kernel_addr_r '&' fe000000 && " \
"if test $kernel_addr_load = $kernel_addr_r; then " \ "if test $kernel_addr_load = $kernel_addr_r; then " \
@@ -192,17 +192,17 @@
"tftpboot $second_image && " \ "tftpboot $second_image && " \
"mmc write $loadaddr 0 100 && " \ "mmc write $loadaddr 0 100 && " \
"tftpboot $third_image && " \ "tftpboot $third_image && " \
"mmc write $loadaddr 100 700\0" \ "mmc write $loadaddr 100 f00\0" \
"nandupdate=nand erase 0 0x00100000 &&" \ "nandupdate=nand erase 0 0x00100000 &&" \
"tftpboot $second_image && " \ "tftpboot $second_image && " \
"nand write $loadaddr 0 0x00020000 && " \ "nand write $loadaddr 0 0x00020000 && " \
"tftpboot $third_image && " \ "tftpboot $third_image && " \
"nand write $loadaddr 0x00020000 0x000e0000\0" \ "nand write $loadaddr 0x00020000 0x001e0000\0" \
"usbupdate=usb start &&" \ "usbupdate=usb start &&" \
"tftpboot $second_image && " \ "tftpboot $second_image && " \
"usb write $loadaddr 0 100 && " \ "usb write $loadaddr 0 100 && " \
"tftpboot $third_image && " \ "tftpboot $third_image && " \
"usb write $loadaddr 100 700\0" \ "usb write $loadaddr 100 f00\0" \
BOOT_IMAGES \ BOOT_IMAGES \
LINUXBOOT_ENV_SETTINGS LINUXBOOT_ENV_SETTINGS