ARM: always perform per-CPU GIC init
The current code in ARMv8's lowlevel_init() skips the per-CPU GIC initialization ifndef CONFIG_ARMV8_MULTIENTRY. However, the per-CPU init should always occur; it's just the one-time init that should only happen on the master. Once this consideration is taken into account, the only difference between the paths when CONFIG_ARMV8_MULTIENTRY is undefined/defined is the use of branch_if_slave. Naively, any unified code would need to invoke this conditionally upon ifdef CONFIG_ARMV8_MULTIENTRY. However, branch_if_slave already checks CONFIG_ARMV8_MULTIENTRY and does nothing if it isn't defined, so we don't even need that ifdef at the call site. Reported-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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@ -201,15 +201,6 @@ ENDPROC(apply_core_errata)
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WEAK(lowlevel_init)
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WEAK(lowlevel_init)
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mov x29, lr /* Save LR */
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mov x29, lr /* Save LR */
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#ifndef CONFIG_ARMV8_MULTIENTRY
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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/*
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* For single-entry systems the lowlevel init is very simple.
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*/
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ldr x0, =GICD_BASE
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bl gic_init_secure
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#endif
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#else /* CONFIG_ARMV8_MULTIENTRY is set */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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ldr x0, =GICD_BASE
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@ -222,7 +213,6 @@ WEAK(lowlevel_init)
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ldr x0, =GICD_BASE
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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bl gic_init_secure_percpu
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#endif
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#endif
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#endif
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branch_if_master x0, x1, 2f
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branch_if_master x0, x1, 2f
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