Blackfin: add driver for on-chip MMC/SD controller
This is a port of the Linux Blackfin on-chip SDH driver to U-Boot. Signed-off-by: Cliff Cai <cliff.cai@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Cliff Cai
Mike Frysinger
parent
6e87ea0ca9
commit
716ebf436c
@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
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LIB := $(obj)libmmc.a
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COBJS-$(CONFIG_ATMEL_MCI) += atmel_mci.o
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COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
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COBJS-$(CONFIG_OMAP3_MMC) += omap3_mmc.o
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COBJS := $(COBJS-y)
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546
drivers/mmc/bfin_sdh.c
Normal file
546
drivers/mmc/bfin_sdh.c
Normal file
@ -0,0 +1,546 @@
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/*
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* Driver for Blackfin on-chip SDH controller
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*
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* Copyright (c) 2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <common.h>
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#include <malloc.h>
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#include <part.h>
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#include <mmc.h>
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#include <asm/io.h>
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#include <asm/errno.h>
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#include <asm/byteorder.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/sdh.h>
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#include <asm/mach-common/bits/dma.h>
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#include "bfin_sdh.h"
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/* SD_CLK frequency must be less than 400k in identification mode */
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#ifndef CONFIG_SYS_MMC_CLK_ID
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#define CONFIG_SYS_MMC_CLK_ID 200000
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#endif
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/* SD_CLK for normal working */
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#ifndef CONFIG_SYS_MMC_CLK_OP
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#define CONFIG_SYS_MMC_CLK_OP 25000000
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#endif
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/* support 3.2-3.3V and 3.3-3.4V */
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#define CONFIG_SYS_MMC_OP_COND 0x00300000
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#define MMC_DEFAULT_RCA 1
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#if defined(__ADSPBF51x__)
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# define bfin_read_SDH_PWR_CTL bfin_read_RSI_PWR_CONTROL
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# define bfin_write_SDH_PWR_CTL bfin_write_RSI_PWR_CONTROL
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# define bfin_read_SDH_CLK_CTL bfin_read_RSI_CLK_CONTROL
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# define bfin_write_SDH_CLK_CTL bfin_write_RSI_CLK_CONTROL
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# define bfin_write_SDH_ARGUMENT bfin_write_RSI_ARGUMENT
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# define bfin_write_SDH_COMMAND bfin_write_RSI_COMMAND
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# define bfin_read_SDH_RESPONSE0 bfin_read_RSI_RESPONSE0
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# define bfin_read_SDH_RESPONSE1 bfin_read_RSI_RESPONSE1
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# define bfin_read_SDH_RESPONSE2 bfin_read_RSI_RESPONSE2
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# define bfin_read_SDH_RESPONSE3 bfin_read_RSI_RESPONSE3
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# define bfin_write_SDH_DATA_TIMER bfin_write_RSI_DATA_TIMER
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# define bfin_write_SDH_DATA_LGTH bfin_write_RSI_DATA_LGTH
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# define bfin_read_SDH_DATA_CTL bfin_read_RSI_DATA_CONTROL
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# define bfin_write_SDH_DATA_CTL bfin_write_RSI_DATA_CONTROL
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# define bfin_read_SDH_STATUS bfin_read_RSI_STATUS
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# define bfin_write_SDH_STATUS_CLR bfin_write_RSI_STATUSCL
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# define bfin_read_SDH_CFG bfin_read_RSI_CONFIG
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# define bfin_write_SDH_CFG bfin_write_RSI_CONFIG
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# define bfin_write_DMA_START_ADDR bfin_write_DMA4_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA4_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA4_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA4_CONFIG
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#elif defined(__ADSPBF54x__)
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# define bfin_write_DMA_START_ADDR bfin_write_DMA22_START_ADDR
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# define bfin_write_DMA_X_COUNT bfin_write_DMA22_X_COUNT
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# define bfin_write_DMA_X_MODIFY bfin_write_DMA22_X_MODIFY
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# define bfin_write_DMA_CONFIG bfin_write_DMA22_CONFIG
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#else
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# error no support for this proc yet
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#endif
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static unsigned int mmc_rca;
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static int mmc_card_is_sd;
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static block_dev_desc_t mmc_blkdev;
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struct mmc_cid cid;
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static __u32 csd[4];
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#define get_bits(resp, start, size) \
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({ \
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const int __size = size; \
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const uint32_t __mask = (__size < 32 ? 1 << __size : 0) - 1; \
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const int32_t __off = 3 - ((start) / 32); \
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const int32_t __shft = (start) & 31; \
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uint32_t __res; \
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\
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__res = resp[__off] >> __shft; \
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if (__size + __shft > 32) \
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__res |= resp[__off-1] << ((32 - __shft) % 32); \
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__res & __mask; \
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})
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block_dev_desc_t *mmc_get_dev(int dev)
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{
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return &mmc_blkdev;
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}
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static void mci_set_clk(unsigned long clk)
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{
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unsigned long sys_clk;
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unsigned long clk_div;
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__u16 clk_ctl = 0;
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/* setting SD_CLK */
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sys_clk = get_sclk();
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bfin_write_SDH_CLK_CTL(0);
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if (sys_clk % (2 * clk) == 0)
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clk_div = sys_clk / (2 * clk) - 1;
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else
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clk_div = sys_clk / (2 * clk);
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if (clk_div > 0xff)
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clk_div = 0xff;
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clk_ctl |= (clk_div & 0xff);
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clk_ctl |= CLK_E;
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bfin_write_SDH_CLK_CTL(clk_ctl);
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}
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static int
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mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags)
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{
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unsigned int sdh_cmd;
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unsigned int status;
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int ret = 0;
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sdh_cmd = 0;
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unsigned long *response = resp;
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sdh_cmd |= cmd;
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if (flags & MMC_RSP_PRESENT)
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sdh_cmd |= CMD_RSP;
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if (flags & MMC_RSP_136)
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sdh_cmd |= CMD_L_RSP;
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bfin_write_SDH_ARGUMENT(arg);
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bfin_write_SDH_COMMAND(sdh_cmd | CMD_E);
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/* wait for a while */
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do {
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udelay(1);
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status = bfin_read_SDH_STATUS();
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} while (!(status & (CMD_SENT | CMD_RESP_END | CMD_TIME_OUT |
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CMD_CRC_FAIL)));
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if (flags & MMC_RSP_PRESENT) {
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response[0] = bfin_read_SDH_RESPONSE0();
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if (flags & MMC_RSP_136) {
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response[1] = bfin_read_SDH_RESPONSE1();
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response[2] = bfin_read_SDH_RESPONSE2();
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response[3] = bfin_read_SDH_RESPONSE3();
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}
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}
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if (status & CMD_TIME_OUT) {
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printf("CMD%d timeout\n", (int)cmd);
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ret |= -ETIMEDOUT;
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} else if (status & CMD_CRC_FAIL && flags & MMC_RSP_CRC) {
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printf("CMD%d CRC failure\n", (int)cmd);
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ret |= -EILSEQ;
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}
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bfin_write_SDH_STATUS_CLR(CMD_SENT_STAT | CMD_RESP_END_STAT |
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CMD_TIMEOUT_STAT | CMD_CRC_FAIL_STAT);
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return ret;
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}
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static int
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mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags)
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{
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unsigned long aresp[4];
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int ret = 0;
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ret = mmc_cmd(MMC_CMD_APP_CMD, 0, aresp,
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MMC_RSP_PRESENT);
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if (ret)
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return ret;
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if ((aresp[0] & (ILLEGAL_COMMAND | APP_CMD)) != APP_CMD)
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return -ENODEV;
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ret = mmc_cmd(cmd, arg, resp, flags);
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return ret;
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}
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static unsigned long
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mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, void *buffer)
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{
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int ret, i;
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unsigned long resp[4];
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unsigned long card_status;
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__u8 *buf = buffer;
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__u32 status;
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__u16 data_ctl = 0;
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__u16 dma_cfg = 0;
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if (blkcnt == 0)
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return 0;
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debug("mmc_bread: dev %d, start %d, blkcnt %d\n", dev, start, blkcnt);
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/* Force to use 512-byte block,because a lot of code depends on this */
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data_ctl |= 9 << 4;
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data_ctl |= DTX_DIR;
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bfin_write_SDH_DATA_CTL(data_ctl);
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dma_cfg |= WDSIZE_32 | RESTART | WNR | DMAEN;
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/* FIXME later */
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bfin_write_SDH_DATA_TIMER(0xFFFFFFFF);
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for (i = 0; i < blkcnt; ++i, ++start) {
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blackfin_dcache_flush_invalidate_range(buf + i * mmc_blkdev.blksz,
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buf + (i + 1) * mmc_blkdev.blksz);
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bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz);
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bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4);
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bfin_write_DMA_X_MODIFY(4);
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bfin_write_DMA_CONFIG(dma_cfg);
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bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz);
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/* Put the device into Transfer state */
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ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_SELECT_CARD failed\n");
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goto out;
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}
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/* Set block length */
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ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_SET_BLOCKLEN failed\n");
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goto out;
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}
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ret = mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK,
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start * mmc_blkdev.blksz, resp,
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MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_READ_SINGLE_BLOCK failed\n");
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goto out;
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}
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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do {
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udelay(1);
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status = bfin_read_SDH_STATUS();
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} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)));
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if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | RX_OVERRUN)) {
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bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT | \
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DAT_CRC_FAIL_STAT | RX_OVERRUN_STAT);
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goto read_error;
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} else {
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bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
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mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0);
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}
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}
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out:
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return i;
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read_error:
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mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1);
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printf("mmc: bread failed, status = %08x, card status = %08lx\n",
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status, card_status);
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goto out;
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}
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static unsigned long
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mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer)
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{
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int ret, i = 0;
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unsigned long resp[4];
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unsigned long card_status;
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const __u8 *buf = buffer;
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__u32 status;
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__u16 data_ctl = 0;
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__u16 dma_cfg = 0;
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if (blkcnt == 0)
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return 0;
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debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n",
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dev, start, blkcnt);
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/* Force to use 512-byte block,because a lot of code depends on this */
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data_ctl |= 9 << 4;
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data_ctl &= ~DTX_DIR;
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bfin_write_SDH_DATA_CTL(data_ctl);
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dma_cfg |= WDSIZE_32 | RESTART | DMAEN;
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/* FIXME later */
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bfin_write_SDH_DATA_TIMER(0xFFFFFFFF);
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for (i = 0; i < blkcnt; ++i, ++start) {
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bfin_write_DMA_START_ADDR(buf + i * mmc_blkdev.blksz);
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bfin_write_DMA_X_COUNT(mmc_blkdev.blksz / 4);
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bfin_write_DMA_X_MODIFY(4);
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bfin_write_DMA_CONFIG(dma_cfg);
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bfin_write_SDH_DATA_LGTH(mmc_blkdev.blksz);
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/* Put the device into Transfer state */
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ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_SELECT_CARD failed\n");
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goto out;
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}
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/* Set block length */
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ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_SET_BLOCKLEN failed\n");
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goto out;
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}
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ret = mmc_cmd(MMC_CMD_WRITE_BLOCK,
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start * mmc_blkdev.blksz, resp,
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MMC_RSP_R1);
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if (ret) {
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printf("MMC_CMD_WRITE_SINGLE_BLOCK failed\n");
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goto out;
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}
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bfin_write_SDH_DATA_CTL(bfin_read_SDH_DATA_CTL() | DTX_DMA_E | DTX_E);
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do {
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udelay(1);
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status = bfin_read_SDH_STATUS();
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} while (!(status & (DAT_BLK_END | DAT_END | DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)));
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if (status & (DAT_TIME_OUT | DAT_CRC_FAIL | TX_UNDERRUN)) {
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bfin_write_SDH_STATUS_CLR(DAT_TIMEOUT_STAT |
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DAT_CRC_FAIL_STAT | TX_UNDERRUN_STAT);
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goto write_error;
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} else {
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bfin_write_SDH_STATUS_CLR(DAT_BLK_END_STAT | DAT_END_STAT);
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mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, 0);
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}
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}
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out:
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return i;
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write_error:
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mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, MMC_RSP_R1);
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printf("mmc: bwrite failed, status = %08x, card status = %08lx\n",
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status, card_status);
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goto out;
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}
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static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp)
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{
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cid->mid = resp[0] >> 24;
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cid->oid = (resp[0] >> 8) & 0xffff;
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cid->pnm[0] = resp[0];
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cid->pnm[1] = resp[1] >> 24;
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cid->pnm[2] = resp[1] >> 16;
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cid->pnm[3] = resp[1] >> 8;
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cid->pnm[4] = resp[1];
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cid->pnm[5] = resp[2] >> 24;
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cid->pnm[6] = 0;
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cid->prv = resp[2] >> 16;
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cid->psn = (resp[2] << 16) | (resp[3] >> 16);
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cid->mdt = resp[3] >> 8;
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}
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static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp)
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{
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cid->mid = resp[0] >> 24;
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cid->oid = (resp[0] >> 8) & 0xffff;
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cid->pnm[0] = resp[0];
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cid->pnm[1] = resp[1] >> 24;
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cid->pnm[2] = resp[1] >> 16;
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cid->pnm[3] = resp[1] >> 8;
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cid->pnm[4] = resp[1];
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cid->pnm[5] = 0;
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cid->pnm[6] = 0;
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cid->prv = resp[2] >> 24;
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cid->psn = (resp[2] << 8) | (resp[3] >> 24);
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cid->mdt = (resp[3] >> 8) & 0x0fff;
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}
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static void mmc_dump_cid(const struct mmc_cid *cid)
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{
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printf("CID information:\n");
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printf("Manufacturer ID: %02X\n", cid->mid);
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printf("OEM/Application ID: %04X\n", cid->oid);
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printf("Product name: %s\n", cid->pnm);
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printf("Product Revision: %u.%u\n",
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cid->prv >> 4, cid->prv & 0x0f);
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printf("Product Serial Number: %lu\n", cid->psn);
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printf("Manufacturing Date: %02u/%02u\n",
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cid->mdt >> 4, cid->mdt & 0x0f);
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}
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static void mmc_dump_csd(__u32 *csd)
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{
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printf("CSD information:\n");
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printf("CSD structure version: 1.%u\n", get_bits(csd, 126, 2));
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printf("Card command classes: %03x\n", get_bits(csd, 84, 12));
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printf("Max trans speed: %s\n", (get_bits(csd, 96, 8) == 0x32) ? "25MHz" : "50MHz");
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printf("Read block length: %d\n", 1 << get_bits(csd, 80, 4));
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printf("Write block length: %u\n", 1 << get_bits(csd, 22, 4));
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printf("Card capacity: %u bytes\n",
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(get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2)) *
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(1 << get_bits(csd, 80, 4)));
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putc('\n');
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}
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static int mmc_idle_cards(void)
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{
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int ret = 0;
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/* Reset all cards */
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ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
|
||||
if (ret)
|
||||
return ret;
|
||||
udelay(500);
|
||||
return mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0);
|
||||
}
|
||||
|
||||
static int sd_init_card(struct mmc_cid *cid, int verbose)
|
||||
{
|
||||
unsigned long resp[4];
|
||||
int i, ret = 0;
|
||||
|
||||
mmc_idle_cards();
|
||||
for (i = 0; i < 1000; ++i) {
|
||||
ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND,
|
||||
resp, MMC_RSP_R3);
|
||||
if (ret || (resp[0] & 0x80000000))
|
||||
break;
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2);
|
||||
if (ret)
|
||||
return ret;
|
||||
sd_parse_cid(cid, resp);
|
||||
if (verbose)
|
||||
mmc_dump_cid(cid);
|
||||
|
||||
/* Get RCA of the card that responded */
|
||||
ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, MMC_RSP_R6);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
mmc_rca = (resp[0] >> 16) & 0xffff;
|
||||
if (verbose)
|
||||
printf("SD Card detected (RCA %u)\n", mmc_rca);
|
||||
mmc_card_is_sd = 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mmc_init_card(struct mmc_cid *cid, int verbose)
|
||||
{
|
||||
unsigned long resp[4];
|
||||
int i, ret = 0;
|
||||
|
||||
mmc_idle_cards();
|
||||
for (i = 0; i < 1000; ++i) {
|
||||
ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CONFIG_SYS_MMC_OP_COND, resp,
|
||||
MMC_RSP_R3);
|
||||
if (ret || (resp[0] & 0x80000000))
|
||||
break;
|
||||
ret = -ETIMEDOUT;
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Get CID of all cards. FIXME: Support more than one card */
|
||||
ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, MMC_RSP_R2);
|
||||
if (ret)
|
||||
return ret;
|
||||
mmc_parse_cid(cid, resp);
|
||||
if (verbose)
|
||||
mmc_dump_cid(cid);
|
||||
|
||||
/* Set Relative Address of the card that responded */
|
||||
ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp,
|
||||
MMC_RSP_R1);
|
||||
return ret;
|
||||
}
|
||||
|
||||
int mmc_init(int verbose)
|
||||
{
|
||||
__u16 pwr_ctl = 0;
|
||||
int ret;
|
||||
unsigned int max_blksz;
|
||||
/* Initialize sdh controller */
|
||||
#if defined(__ADSPBF54x__)
|
||||
bfin_write_DMAC1_PERIMUX(bfin_read_DMAC1_PERIMUX() | 0x1);
|
||||
bfin_write_PORTC_FER(bfin_read_PORTC_FER() | 0x3F00);
|
||||
bfin_write_PORTC_MUX(bfin_read_PORTC_MUX() & ~0xFFF0000);
|
||||
#elif defined(__ADSPBF51x__)
|
||||
bfin_write_PORTG_FER(bfin_read_PORTG_FER() | 0x01F8);
|
||||
bfin_write_PORTG_MUX((bfin_read_PORTG_MUX() & ~0x3FC) | 0x154);
|
||||
#else
|
||||
# error no portmux for this proc yet
|
||||
#endif
|
||||
bfin_write_SDH_CFG(bfin_read_SDH_CFG() | CLKS_EN);
|
||||
/* Disable card detect pin */
|
||||
bfin_write_SDH_CFG((bfin_read_SDH_CFG() & 0x1F) | 0x60);
|
||||
mci_set_clk(CONFIG_SYS_MMC_CLK_ID);
|
||||
/* setting power control */
|
||||
pwr_ctl |= ROD_CTL;
|
||||
pwr_ctl |= PWR_ON;
|
||||
bfin_write_SDH_PWR_CTL(pwr_ctl);
|
||||
mmc_card_is_sd = 0;
|
||||
ret = sd_init_card(&cid, verbose);
|
||||
if (ret) {
|
||||
mmc_rca = MMC_DEFAULT_RCA;
|
||||
ret = mmc_init_card(&cid, verbose);
|
||||
}
|
||||
if (ret)
|
||||
return ret;
|
||||
/* Get CSD from the card */
|
||||
ret = mmc_cmd(MMC_CMD_SEND_CSD, mmc_rca << 16, csd, MMC_RSP_R2);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (verbose)
|
||||
mmc_dump_csd(csd);
|
||||
/* Initialize the blockdev structure */
|
||||
mmc_blkdev.if_type = IF_TYPE_MMC;
|
||||
mmc_blkdev.part_type = PART_TYPE_DOS;
|
||||
mmc_blkdev.block_read = mmc_bread;
|
||||
mmc_blkdev.block_write = mmc_bwrite;
|
||||
sprintf(mmc_blkdev.vendor,
|
||||
"Man %02x%04x Snr %08lx",
|
||||
cid.mid, cid.oid, cid.psn);
|
||||
strncpy(mmc_blkdev.product, cid.pnm,
|
||||
sizeof(mmc_blkdev.product));
|
||||
sprintf(mmc_blkdev.revision, "%x %x",
|
||||
cid.prv >> 4, cid.prv & 0x0f);
|
||||
|
||||
max_blksz = 1 << get_bits(csd, 80, 4);
|
||||
/*
|
||||
* If we can't use 512 byte blocks, refuse to deal with the
|
||||
* card. Tons of code elsewhere seems to depend on this.
|
||||
*/
|
||||
if (max_blksz < 512 || (max_blksz > 512 && !get_bits(csd, 79, 1))) {
|
||||
printf("Card does not support 512 byte reads, aborting.\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
mmc_blkdev.blksz = 512;
|
||||
mmc_blkdev.lba = (get_bits(csd, 62, 12) + 1) * (1 << (get_bits(csd, 47, 3) + 2));
|
||||
mci_set_clk(CONFIG_SYS_MMC_CLK_OP);
|
||||
init_part(&mmc_blkdev);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int mmc_read(ulong src, uchar *dst, int size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int mmc_write(uchar *src, ulong dst, int size)
|
||||
{
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
int mmc2info(ulong addr)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
59
drivers/mmc/bfin_sdh.h
Normal file
59
drivers/mmc/bfin_sdh.h
Normal file
@ -0,0 +1,59 @@
|
||||
/*
|
||||
* Copyright (C) 2008 Analog Device Inc.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef __BLACKFIN_SDH_H__
|
||||
#define __BLACKFIN_SDH_H__
|
||||
|
||||
#define MMC_RSP_PRESENT (1 << 0)
|
||||
#define MMC_RSP_136 (1 << 1) /* 136 bit response */
|
||||
#define MMC_RSP_CRC (1 << 2) /* expect valid crc */
|
||||
#define MMC_RSP_BUSY (1 << 3) /* card may send busy */
|
||||
#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
|
||||
|
||||
#define MMC_CMD_MASK (3 << 5) /* non-SPI command type */
|
||||
#define MMC_CMD_AC (0 << 5)
|
||||
#define MMC_CMD_ADTC (1 << 5)
|
||||
#define MMC_CMD_BC (2 << 5)
|
||||
#define MMC_CMD_BCR (3 << 5)
|
||||
|
||||
#define MMC_RSP_SPI_S1 (1 << 7) /* one status byte */
|
||||
#define MMC_RSP_SPI_S2 (1 << 8) /* second byte */
|
||||
#define MMC_RSP_SPI_B4 (1 << 9) /* four data bytes */
|
||||
#define MMC_RSP_SPI_BUSY (1 << 10) /* card may send busy */
|
||||
|
||||
/*
|
||||
* These are the native response types, and correspond to valid bit
|
||||
* patterns of the above flags. One additional valid pattern
|
||||
* is all zeros, which means we don't expect a response.
|
||||
*/
|
||||
#define MMC_RSP_NONE (0)
|
||||
#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY)
|
||||
#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
|
||||
#define MMC_RSP_R3 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R4 (MMC_RSP_PRESENT)
|
||||
#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
|
||||
#define ILLEGAL_COMMAND (1 << 22)
|
||||
#define APP_CMD (1 << 5)
|
||||
|
||||
#endif
|
||||
122
include/asm-blackfin/mach-common/bits/sdh.h
Normal file
122
include/asm-blackfin/mach-common/bits/sdh.h
Normal file
@ -0,0 +1,122 @@
|
||||
/*
|
||||
* SDH Masks
|
||||
*/
|
||||
|
||||
#ifndef __BFIN_PERIPHERAL_SDH__
|
||||
#define __BFIN_PERIPHERAL_SDH__
|
||||
|
||||
/* Bit masks for SDH_COMMAND */
|
||||
#define CMD_IDX 0x3f /* Command Index */
|
||||
#define CMD_RSP 0x40 /* Response */
|
||||
#define CMD_L_RSP 0x80 /* Long Response */
|
||||
#define CMD_INT_E 0x100 /* Command Interrupt */
|
||||
#define CMD_PEND_E 0x200 /* Command Pending */
|
||||
#define CMD_E 0x400 /* Command Enable */
|
||||
|
||||
/* Bit masks for SDH_PWR_CTL */
|
||||
#define PWR_ON 0x3 /* Power On */
|
||||
#define SD_CMD_OD 0x40 /* Open Drain Output */
|
||||
#define ROD_CTL 0x80 /* Rod Control */
|
||||
|
||||
/* Bit masks for SDH_CLK_CTL */
|
||||
#define CLKDIV 0xff /* MC_CLK Divisor */
|
||||
#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
|
||||
#define PWR_SV_E 0x200 /* Power Save Enable */
|
||||
#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
|
||||
#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
|
||||
|
||||
/* Bit masks for SDH_RESP_CMD */
|
||||
#define RESP_CMD 0x3f /* Response Command */
|
||||
|
||||
/* Bit masks for SDH_DATA_CTL */
|
||||
#define DTX_E 0x1 /* Data Transfer Enable */
|
||||
#define DTX_DIR 0x2 /* Data Transfer Direction */
|
||||
#define DTX_MODE 0x4 /* Data Transfer Mode */
|
||||
#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
|
||||
#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
|
||||
|
||||
/* Bit masks for SDH_STATUS */
|
||||
#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
|
||||
#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
|
||||
#define CMD_TIME_OUT 0x4 /* CMD Time Out */
|
||||
#define DAT_TIME_OUT 0x8 /* Data Time Out */
|
||||
#define TX_UNDERRUN 0x10 /* Transmit Underrun */
|
||||
#define RX_OVERRUN 0x20 /* Receive Overrun */
|
||||
#define CMD_RESP_END 0x40 /* CMD Response End */
|
||||
#define CMD_SENT 0x80 /* CMD Sent */
|
||||
#define DAT_END 0x100 /* Data End */
|
||||
#define START_BIT_ERR 0x200 /* Start Bit Error */
|
||||
#define DAT_BLK_END 0x400 /* Data Block End */
|
||||
#define CMD_ACT 0x800 /* CMD Active */
|
||||
#define TX_ACT 0x1000 /* Transmit Active */
|
||||
#define RX_ACT 0x2000 /* Receive Active */
|
||||
#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
|
||||
#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
|
||||
#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
|
||||
#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
|
||||
#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
|
||||
#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
|
||||
#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
|
||||
#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
|
||||
|
||||
/* Bit masks for SDH_STATUS_CLR */
|
||||
#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
|
||||
#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
|
||||
#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
|
||||
#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
|
||||
#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
|
||||
#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
|
||||
#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
|
||||
#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
|
||||
#define DAT_END_STAT 0x100 /* Data End Status */
|
||||
#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
|
||||
#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
|
||||
|
||||
/* Bit masks for SDH_MASK0 */
|
||||
#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
|
||||
#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
|
||||
#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
|
||||
#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
|
||||
#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
|
||||
#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
|
||||
#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
|
||||
#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
|
||||
#define DAT_END_MASK 0x100 /* Data End Mask */
|
||||
#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
|
||||
#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
|
||||
#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
|
||||
#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
|
||||
#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
|
||||
#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
|
||||
#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
|
||||
#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
|
||||
#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
|
||||
#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
|
||||
#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
|
||||
#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
|
||||
#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
|
||||
|
||||
/* Bit masks for SDH_FIFO_CNT */
|
||||
#define FIFO_COUNT 0x7fff /* FIFO Count */
|
||||
|
||||
/* Bit masks for SDH_E_STATUS */
|
||||
#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
|
||||
#define SD_CARD_DET 0x10 /* SD Card Detect */
|
||||
|
||||
/* Bit masks for SDH_E_MASK */
|
||||
#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
|
||||
#define SCD_MSK 0x40 /* Mask Card Detect */
|
||||
|
||||
/* Bit masks for SDH_CFG */
|
||||
#define CLKS_EN 0x1 /* Clocks Enable */
|
||||
#define SD4E 0x4 /* SDIO 4-Bit Enable */
|
||||
#define MWE 0x8 /* Moving Window Enable */
|
||||
#define SD_RST 0x10 /* SDMMC Reset */
|
||||
#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
|
||||
#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
|
||||
#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
|
||||
|
||||
/* Bit masks for SDH_RD_WAIT_EN */
|
||||
#define RWR 0x1 /* Read Wait Request */
|
||||
|
||||
#endif
|
||||
1
include/asm-blackfin/mmc.h
Normal file
1
include/asm-blackfin/mmc.h
Normal file
@ -0,0 +1 @@
|
||||
#include <asm-avr32/arch-at32ap700x/mmc.h>
|
||||
Loading…
Reference in New Issue
Block a user