leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Cleanup

Browse Source
This commit is contained in:
Wolfgang Denk
2005-09-25 18:49:35 +02:00
parent 49a7581c6c
commit 716c1dcb41
10 changed files with 197 additions and 211 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
board/integratorap/integratorap.c
View File

@@ -36,7 +36,7 @@
#include <common.h>
#ifdef CONFIG_PCI
# include <pci.h>
#include <pci.h>
#endif
void flash__init (void);
@@ -46,7 +46,7 @@ void peripheral_power_enable (void);
#if defined(CONFIG_SHOW_BOOT_PROGRESS)
void show_boot_progress(int progress)
{
printf("Boot reached stage %d\n", progress);
printf("Boot reached stage %d\n", progress);
}
#endif
@@ -79,7 +79,7 @@ int board_init (void)
extern void cm_remap(void);
cm_remap(); /* remaps writeable memory to 0x00000000 */
#endif
icache_enable ();
flash__init ();
@@ -483,7 +483,7 @@ int dram_init (void)
DECLARE_GLOBAL_DATA_PTR;
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
#ifdef CONFIG_CM_SPD_DETECT
{
@@ -492,22 +492,22 @@ extern void dram_query(void);
unsigned long sdram_shift;
dram_query(); /* Assembler accesses to CM registers */
/* Queries the SPD values */
/* Queries the SPD values */
/* Obtain the SDRAM size from the CM SDRAM register */
cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM);
/* Register SDRAM size
/* Register SDRAM size
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
* 0xXXXXXXbbb000bb 16 MB
* 0xXXXXXXbbb001bb 32 MB
* 0xXXXXXXbbb010bb 64 MB
* 0xXXXXXXbbb011bb 128 MB
* 0xXXXXXXbbb100bb 256 MB
*
*/
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4;
gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift;
}
#endif /* CM_SPD_DETECT */

64
board/integratorap/platform.S
View File

@@ -36,7 +36,7 @@ reset_cpu:
reset_failed:
b reset_failed
/* set up the platform, once the cpu has been initialized */
.globl platformsetup
platformsetup:
@@ -48,45 +48,45 @@ platformsetup:
* itself should be performed in cpu/arm<>/start.S
* This function affects only the core module or board settings
*/
#ifdef CONFIG_CM_INIT
/* CM has an initialization register
* - bits in it are wired into test-chip pins to force
* reset defaults
* - may need to change its contents for U-Boot
*/
/* set the desired CM specific value */
mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */
#if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E)
orr r2,r2,#CMMASK_INIT_102
#else
#if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \
!defined (CONFIG_CM940T)
#ifdef CONFIG_CM_MULTIPLE_SSRAM
/* set simple mapping */
and r2,r2,#CMMASK_MAP_SIMPLE
#endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */
#ifdef CONFIG_CM_TCRAM
/* disable TCRAM */
and r2,r2,#CMMASK_TCRAM_DISABLE
#endif /* #ifdef CONFIG_CM_TCRAM */
#if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \
defined (CONFIG_CM1136JF_S)
and r2,r2,#CMMASK_LE
#endif /* cpu with little endian initialization */
orr r2,r2,#CMMASK_CMxx6_COMMON
#endif /* CMxx6 code */
#endif /* ARM102xxE value */
/* read CM_INIT */
@@ -96,7 +96,7 @@ platformsetup:
and r3,r1,r2
cmp r3,r2
beq init_reg_OK
/* lock for change */
mov r3, #CMVAL_LOCK
and r3,r3,#CMMASK_LOCK
@@ -107,16 +107,16 @@ platformsetup:
str r1, [r0, #OS_INIT]
mov r1, #CMVAL_UNLOCK
str r1, [r0, #OS_LOCK]
/* soft reset so new values used */
b reset_cpu
init_reg_OK:
#endif /* CONFIG_CM_INIT */
mov pc, lr
#ifdef CONFIG_CM_SPD_DETECT
/* Fast memory is available for the DRAM data
* - ensure it has been transferred, then summarize the data
@@ -128,13 +128,13 @@ dram_query:
/* set up SDRAM info */
/* - based on example code from the CM User Guide */
mov r0, #CM_BASE
readspdbit:
ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */
and r1, r1, #0x20 /* mask SPD bit (5) */
cmp r1, #0x20 /* test if set */
bne readspdbit
setupsdram:
add r0, r0, #OS_SPD /* address the copy of the SDP data */
ldrb r1, [r0, #3] /* number of row address lines */
@@ -148,40 +148,40 @@ setupsdram:
bne not16
mov r6, #0x2 /* store size and CAS latency of 2 */
b writesize
not16:
cmp r5, #0x20 /* is it 32MB? */
bne not32
mov r6, #0x6
b writesize
not32:
cmp r5, #0x40 /* is it 64MB? */
bne not64
mov r6, #0xa
b writesize
not64:
cmp r5, #0x80 /* is it 128MB? */
bne not128
mov r6, #0xe
b writesize
not128:
/* if it is none of these sizes then it is either 256MB, or
* there is no SDRAM fitted so default to 256MB
*/
mov r6, #0x12
writesize:
mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */
orr r2, r1, r2, ASL#12 /* OR in column address lines */
orr r3, r2, r3, ASL#16 /* OR in number of banks */
orr r6, r6, r3 /* OR in size and CAS latency */
str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */
#endif /* #ifdef CONFIG_CM_SPD_DETECT */
ldmfd r13!,{r4-r6,pc} /* back to caller */
#ifdef CONFIG_CM_REMAP
@@ -191,23 +191,23 @@ writesize:
.globl cm_remap
cm_remap:
stmfd r13!,{r4-r10,lr}
mov r0, #CM_BASE
ldr r1, [r0, #OS_CTRL]
orr r1, r1, #CMMASK_REMAP /* set remap and led bits */
str r1, [r0, #OS_CTRL]
/* Now 0x00000000 is writeable, replace the vectors */
ldr r0, =_start /* r0 <- start of vectors */
ldr r2, =_armboot_start /* r2 <- past vectors */
sub r1,r1,r1 /* destination 0x00000000 */
copy_vec:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
ble copy_vec
ldmfd r13!,{r4-r10,pc} /* back to caller */
#endif /* #ifdef CONFIG_CM_REMAP */

4
board/mpc8260ads/mpc8260ads.c
View File

@@ -13,7 +13,7 @@
* Yuli Barcohen <yuli@arabellasw.com>
* Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
*
* Copyright (c) 2005 MontaVista Software, Inc.
* Copyright (c) 2005 MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
* Added support for PCI.
*
@@ -267,7 +267,7 @@ int board_early_init_f (void)
#ifdef CONFIG_PCI
volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
/* mask alll the PCI interrupts */
pci_ic->pci_int_mask |= 0xfff00000;
#endif

1
board/omap2420h4/sys_info.c
View File

@@ -385,4 +385,3 @@ u32 get_device_type(void)
mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8);
return(mode >>= 8);
}