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armv8: LSCH2 early and final mmu needs matching NS attribute

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When switching between the early and final mmu tables, the stack will
get corrupted if the Non-Secure attribute is different.  For ls1043a,
this issue is currently masked because flush_dcache_all is called
before the switch when CONFIG_SYS_DPAA_FMAN is defined.

Signed-off-by: Ed Swarthout <Ed.Swarthout@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Ed Swarthout 2016-03-28 16:16:01 -05:00 committed by York Sun
parent ce96ba4b84
commit 70e21b0642
1 changed files with 8 additions and 4 deletions
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12
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
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@ -157,9 +157,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
@ -245,7 +247,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
{ CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
@ -256,7 +259,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
{ CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
#endif
};
#endif