From da20981269d890cb85ef9336a3f488d61fbd73b7 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 24 Nov 2016 15:29:50 +0800 Subject: [PATCH 01/22] rockchip: board: popmetal: de-assert the host rst pin in board init The PopMetal board have a on board FE1.1 usb 2.0 hub which connect to the usb host port, we need to de-assert its reset pin to enable it. Signed-off-by: Kever Yang Acked-by: Simon Glass Added rockchip: tag: Signed-off-by: Simon Glass --- .../chipspark/popmetal_rk3288/popmetal-rk3288.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c index aad74ef109..ed82b2bd78 100644 --- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c +++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c @@ -6,6 +6,7 @@ #include #include +#include void board_boot_order(u32 *spl_boot_list) { @@ -13,3 +14,19 @@ void board_boot_order(u32 *spl_boot_list) spl_boot_list[0] = BOOT_DEVICE_MMC2; spl_boot_list[1] = BOOT_DEVICE_MMC1; } + +#define GPIO7A3_HUB_RST 227 + +int rk_board_late_init(void) +{ + int ret; + + ret = gpio_request(GPIO7A3_HUB_RST, "hub_rst"); + if (ret) + return ret; + ret = gpio_direction_output(GPIO7A3_HUB_RST, 1); + if (ret) + return ret; + + return 0; +} From f57f35a833aa9748ae5a9600fd45a134a3e09152 Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 24 Nov 2016 15:29:51 +0800 Subject: [PATCH 02/22] rockchip: config: popmetal: enable the USB host controller and function RK3288 using the dwc2 USB host controller, enable it and other usb host funtion like storage and ether. Signed-off-by: Kever Yang Acked-by: Simon Glass Added rockchip: tag: Signed-off-by: Simon Glass --- configs/popmetal-rk3288_defconfig | 3 +++ include/configs/rk3288_common.h | 7 +++++++ 2 files changed, 10 insertions(+) diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index a123b841f9..c4bf33a2b3 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -64,3 +64,6 @@ CONFIG_SYSRESET=y CONFIG_USE_TINY_PRINTF=y CONFIG_CMD_DHRYSTONE=y CONFIG_ERRNO_STR=y +CONFIG_CMD_USB=y +CONFIG_USB=y +CONFIG_USB_STORAGE=y diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index a9995ee190..33b1f0e999 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -87,6 +87,13 @@ #define CONFIG_G_DNL_VENDOR_NUM 0x2207 #define CONFIG_G_DNL_PRODUCT_NUM 0x320a +/* usb host support */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ From 897ddcad61122df3caeddc1f8e18e8f2416d458e Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Thu, 24 Nov 2016 15:29:52 +0800 Subject: [PATCH 03/22] rockchip: dts: popmetal: add usb host power supply node The popmetal board using a HOST_VBUS_DRV gpio signal to control the USB host port 5V power, add a fix regulator and pinctrl for it, and enable the USB host1 controller with the vbus-supply. Signed-off-by: Kever Yang Reviewed-by: Simon Glass Added rockchip: tag: Signed-off-by: Simon Glass --- arch/arm/dts/rk3288-popmetal.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm/dts/rk3288-popmetal.dtsi b/arch/arm/dts/rk3288-popmetal.dtsi index f3bd4685bd..e5be4cb471 100644 --- a/arch/arm/dts/rk3288-popmetal.dtsi +++ b/arch/arm/dts/rk3288-popmetal.dtsi @@ -145,6 +145,18 @@ regulator-always-on; vin-supply = <&vcc_io>; }; + + vcc5v0_host: usb-host-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 14 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; }; &cpu0 { @@ -471,6 +483,12 @@ rockchip,pins = <7 11 RK_FUNC_GPIO &pcfg_pull_none>; }; }; + + usb_host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <0 14 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; }; &tsadc { @@ -515,6 +533,11 @@ status = "okay"; }; +&usb_host1 { + vbus-supply = <&vcc5v0_host>; + status = "okay"; +}; + &usbphy { status = "okay"; }; From e1e9703a0af99d227c07d874ea987f9f2c66fff2 Mon Sep 17 00:00:00 2001 From: Jacob Chen Date: Fri, 18 Nov 2016 15:54:25 +0800 Subject: [PATCH 04/22] rockchip: configs: correct env offset when enable CONFIG_ROCKCHIP_SPL_BACK_TO_BROM With CONFIG_ROCKCHIP_SPL_BACK_TO_BROM enabled, the environment is inside u-boot. So solve it by moving environment after u-boot. Signed-off-by: Jacob Chen --- include/configs/evb_rk3288.h | 9 +++++++++ include/configs/fennec_rk3288.h | 9 +++++++++ include/configs/miniarm_rk3288.h | 9 +++++++++ include/configs/popmetal_rk3288.h | 9 +++++++++ 4 files changed, 36 insertions(+) diff --git a/include/configs/evb_rk3288.h b/include/configs/evb_rk3288.h index 77b647eccd..554ca0e636 100644 --- a/include/configs/evb_rk3288.h +++ b/include/configs/evb_rk3288.h @@ -12,11 +12,20 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else /* SPL @ 32k for ~36k * ENV @ 96k * u-boot @ 128K */ #define CONFIG_ENV_OFFSET (96 * 1024) +#endif #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/fennec_rk3288.h b/include/configs/fennec_rk3288.h index 77b647eccd..554ca0e636 100644 --- a/include/configs/fennec_rk3288.h +++ b/include/configs/fennec_rk3288.h @@ -12,11 +12,20 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else /* SPL @ 32k for ~36k * ENV @ 96k * u-boot @ 128K */ #define CONFIG_ENV_OFFSET (96 * 1024) +#endif #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/miniarm_rk3288.h b/include/configs/miniarm_rk3288.h index 94513650e6..5a623ca6ea 100644 --- a/include/configs/miniarm_rk3288.h +++ b/include/configs/miniarm_rk3288.h @@ -17,11 +17,20 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else /* SPL @ 32k for ~36k * ENV @ 96k * u-boot @ 128K */ #define CONFIG_ENV_OFFSET (96 * 1024) +#endif #define CONFIG_SYS_WHITE_ON_BLACK diff --git a/include/configs/popmetal_rk3288.h b/include/configs/popmetal_rk3288.h index 77b647eccd..554ca0e636 100644 --- a/include/configs/popmetal_rk3288.h +++ b/include/configs/popmetal_rk3288.h @@ -12,11 +12,20 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 1 + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else /* SPL @ 32k for ~36k * ENV @ 96k * u-boot @ 128K */ #define CONFIG_ENV_OFFSET (96 * 1024) +#endif #define CONFIG_SYS_WHITE_ON_BLACK From 21ba55dd72b50f5730d8cb57c35ab0a6aa0c08f5 Mon Sep 17 00:00:00 2001 From: Jacob Chen Date: Fri, 18 Nov 2016 15:54:26 +0800 Subject: [PATCH 05/22] rockchip: configs: make rk3036 env config same as rk3288 To make rockchip soc keep the same partition map Signed-off-by: Jacob Chen --- include/configs/kylin_rk3036.h | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/include/configs/kylin_rk3036.h b/include/configs/kylin_rk3036.h index 4f0bd84ad8..bc28525844 100644 --- a/include/configs/kylin_rk3036.h +++ b/include/configs/kylin_rk3036.h @@ -19,9 +19,20 @@ #define CONFIG_ENV_IS_IN_MMC #define CONFIG_SYS_MMC_ENV_DEV 0 /* emmc */ #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ -#define CONFIG_ENV_OFFSET (SZ_4M - SZ_64K) /* reserved area */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) -#define CONFIG_SYS_REDUNDAND_ENVIRONMENT + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* SPL @ 32k for 34k + * u-boot directly after @ 68k for 400k or so + * ENV @ 992k + */ +#define CONFIG_ENV_OFFSET ((1024-32) * 1024) +#else +/* SPL @ 32k for ~36k + * ENV @ 96k + * u-boot @ 128K + */ +#define CONFIG_ENV_OFFSET (96 * 1024) +#endif #endif From 1a581460856d87c88e64088dca19fccc6c1be089 Mon Sep 17 00:00:00 2001 From: Martin Michlmayr Date: Sat, 17 Dec 2016 17:40:26 -0800 Subject: [PATCH 06/22] rockchip: Fix veyron-minnie's Kconfig description The veyron-minnie Kconfig referred to jerry by mistake. Signed-off-by: Martin Michlmayr Acked-by: Simon Glass --- arch/arm/mach-rockchip/rk3288/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 223ae41dd4..54545f378c 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -61,7 +61,7 @@ config TARGET_CHROMEBIT_MICKEY config TARGET_CHROMEBOOK_MINNIE bool "Google/Rockchip Veyron-Minnie Chromebook" help - Jerry is a RK3288-based convertible clamshell device with 2 USB 3.0 + Minnie is a RK3288-based convertible clamshell device with 2 USB 3.0 ports, micro HDMI, a 10.1-inch 1280x800 EDP display, micro-SD card, HD camera, touchpad, WiFi and Bluetooth. It includes a Chrome OS EC (Cortex-M3) to provide access to the keyboard and battery From 39fbb56f845431686966a90456bd232f0b355dbd Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 28 Dec 2016 11:32:35 +0800 Subject: [PATCH 07/22] mmc: rockchip_sdhci: add clock init for mmc Init the clock rate to max-frequency from dts with clock driver api. Signed-off-by: Kever Yang Reviewed-by: Jaehoon Chung --- drivers/mmc/rockchip_sdhci.c | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c index c56e1a3a1c..e33e35e4fa 100644 --- a/drivers/mmc/rockchip_sdhci.c +++ b/drivers/mmc/rockchip_sdhci.c @@ -12,7 +12,9 @@ #include #include #include +#include +DECLARE_GLOBAL_DATA_PTR; /* 400KHz is max freq for card ID etc. Use that as min */ #define EMMC_MIN_FREQ 400000 @@ -32,11 +34,24 @@ static int arasan_sdhci_probe(struct udevice *dev) struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; - int ret; + int max_frequency, ret; + struct clk clk; + + + max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "max-frequency", 0); + ret = clk_get_by_index(dev, 0, &clk); + if (!ret) { + ret = clk_set_rate(&clk, max_frequency); + if (IS_ERR_VALUE(ret)) + printf("%s clk set rate fail!\n", __func__); + } else { + printf("%s fail to get clk\n", __func__); + } host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; - ret = sdhci_setup_cfg(&plat->cfg, host, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, + ret = sdhci_setup_cfg(&plat->cfg, host, max_frequency, EMMC_MIN_FREQ); host->mmc = &plat->mmc; From f5f3de89355336f44f595fa8fb6bb5ed60aee4ed Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 28 Dec 2016 11:32:36 +0800 Subject: [PATCH 08/22] dts: arm64: rk3399: add max-frequency for sdhci Add 'max-frequency' for sdhci node for clock init. Signed-off-by: Kever Yang Reviewed-by: Jaehoon Chung --- arch/arm/dts/rk3399.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/rk3399.dtsi b/arch/arm/dts/rk3399.dtsi index 179860c900..22277ff0ad 100644 --- a/arch/arm/dts/rk3399.dtsi +++ b/arch/arm/dts/rk3399.dtsi @@ -188,6 +188,7 @@ interrupts = ; assigned-clocks = <&cru SCLK_EMMC>; assigned-clock-rates = <200000000>; + max-frequency = <200000000>; clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; clock-names = "clk_xin", "clk_ahb"; phys = <&emmc_phy>; From 2577d3f9245968161c797c0f5bacc4eacea0d67d Mon Sep 17 00:00:00 2001 From: Kever Yang Date: Wed, 28 Dec 2016 17:48:26 +0800 Subject: [PATCH 09/22] arm64: rk3399: update rockchip_get_cru API rk3399 has two clock-controller: cru and pmucru, update the rockchip_get_crui() API, and rockchip_get_clk() do not used for other module. Signed-off-by: Kever Yang --- arch/arm/mach-rockchip/rk3399/clk_rk3399.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c index 7663591154..ce706a61e2 100644 --- a/arch/arm/mach-rockchip/rk3399/clk_rk3399.c +++ b/arch/arm/mach-rockchip/rk3399/clk_rk3399.c @@ -11,10 +11,10 @@ #include #include -int rockchip_get_clk(struct udevice **devp) +static int rockchip_get_cruclk(struct udevice **devp) { return uclass_get_device_by_driver(UCLASS_CLK, - DM_GET_DRIVER(rockchip_rk3399_pmuclk), devp); + DM_GET_DRIVER(clk_rk3399), devp); } void *rockchip_get_cru(void) @@ -23,7 +23,7 @@ void *rockchip_get_cru(void) struct udevice *dev; int ret; - ret = rockchip_get_clk(&dev); + ret = rockchip_get_cruclk(&dev); if (ret) return ERR_PTR(ret); From 9b8320167ea05ede1e5d30dfeb14850fdf2355b2 Mon Sep 17 00:00:00 2001 From: Nickey Yang Nickey Yang Date: Thu, 29 Dec 2016 10:47:30 +0800 Subject: [PATCH 10/22] rockchip: rk3288: set isp/vop qos priority level Isp-camera preview image will be broken when dual screen display mode. This patch set isp/vop qos level higher to solve this problem. We have verified this patch on rk3288-miniarm board. Signed-off-by: Nickey Yang --- .../include/asm/arch-rockchip/qos_rk3288.h | 20 +++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board.c | 20 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/qos_rk3288.h diff --git a/arch/arm/include/asm/arch-rockchip/qos_rk3288.h b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h new file mode 100644 index 0000000000..b3094fcfbe --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/qos_rk3288.h @@ -0,0 +1,20 @@ +/* + * Copyright 2016 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_QOS_RK3288_H +#define _ASM_ARCH_QOS_RK3288_H + +#define PRIORITY_HIGH_SHIFT 2 +#define PRIORITY_LOW_SHIFT 0 + +#define CPU_AXI_QOS_PRIORITY 0x08 + +#define VIO0_VOP_QOS 0xffad0400 +#define VIO1_VOP_QOS 0xffad0000 +#define VIO1_ISP_R_QOS 0xffad0900 +#define VIO1_ISP_W0_QOS 0xffad0100 +#define VIO1_ISP_W1_QOS 0xffad0180 + +#endif diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c index bca6075c2c..8bf45f7fc7 100644 --- a/arch/arm/mach-rockchip/rk3288-board.c +++ b/arch/arm/mach-rockchip/rk3288-board.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -51,9 +52,28 @@ __weak int rk_board_late_init(void) return 0; } +int rk3288_qos_init(void) +{ + int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; + /* set vop qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); + + if (!fdt_node_check_compatible(gd->fdt_blob, 0, + "rockchip,rk3288-miniarm")) + { + /* set isp qos to higher priority */ + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); + writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); + } + return 0; +} + int board_late_init(void) { setup_boot_mode(); + rk3288_qos_init(); return rk_board_late_init(); } From 0fc41e551eebe9b745961083c5961509b9bab240 Mon Sep 17 00:00:00 2001 From: Nickey Yang Nickey Yang Date: Thu, 29 Dec 2016 14:01:26 +0800 Subject: [PATCH 11/22] rockchip: video: fix mpixelclock in rockchip HDMI Correct mpixelclock errors in rockchip_phy_config[] and rockchip_mpll_cfg[]. Signed-off-by: Nickey Yang --- drivers/video/rockchip/rk_hdmi.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/video/rockchip/rk_hdmi.c b/drivers/video/rockchip/rk_hdmi.c index 032b1de103..1a4fa3677e 100644 --- a/drivers/video/rockchip/rk_hdmi.c +++ b/drivers/video/rockchip/rk_hdmi.c @@ -85,13 +85,13 @@ struct hdmi_phy_config { static const struct hdmi_phy_config rockchip_phy_config[] = { { - .mpixelclock = 74250, + .mpixelclock = 74250000, .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, }, { - .mpixelclock = 148500, + .mpixelclock = 148500000, .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, }, { - .mpixelclock = 297000, + .mpixelclock = 297000000, .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, }, { .mpixelclock = ~0ul, @@ -101,22 +101,22 @@ static const struct hdmi_phy_config rockchip_phy_config[] = { static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { { - .mpixelclock = 40000, + .mpixelclock = 40000000, .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, }, { - .mpixelclock = 65000, + .mpixelclock = 65000000, .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, }, { - .mpixelclock = 66000, + .mpixelclock = 66000000, .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, }, { - .mpixelclock = 83500, + .mpixelclock = 835000000, .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, }, { - .mpixelclock = 146250, + .mpixelclock = 146250000, .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, }, { - .mpixelclock = 148500, + .mpixelclock = 148500000, .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, }, { .mpixelclock = ~0ul, @@ -870,7 +870,7 @@ static int rk_hdmi_probe(struct udevice *dev) clk_free(&clk); } if (ret) { - debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret); + debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret); return ret; } From b9e08d0e80e311591704a49341199637069fd157 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 11 Jan 2017 11:46:07 +0100 Subject: [PATCH 12/22] net: designware: Export various functions/struct to allow subclassing To allow other DM drivers to subclass the designware driver various functions and structures need to be exported. Export these. Signed-off-by: Sjoerd Simons Signed-off-by: Romain Perier Reviewed-by: Bin Meng Acked-by: Simon Glass Acked-by: Joe Hershberger --- drivers/net/designware.c | 6 +++--- drivers/net/designware.h | 4 ++++ 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 9e6d726184..6ef36bc8cb 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -628,7 +628,7 @@ static int designware_eth_bind(struct udevice *dev) return 0; } -static int designware_eth_probe(struct udevice *dev) +int designware_eth_probe(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); @@ -678,7 +678,7 @@ static int designware_eth_remove(struct udevice *dev) return 0; } -static const struct eth_ops designware_eth_ops = { +const struct eth_ops designware_eth_ops = { .start = designware_eth_start, .send = designware_eth_send, .recv = designware_eth_recv, @@ -687,7 +687,7 @@ static const struct eth_ops designware_eth_ops = { .write_hwaddr = designware_eth_write_hwaddr, }; -static int designware_eth_ofdata_to_platdata(struct udevice *dev) +int designware_eth_ofdata_to_platdata(struct udevice *dev) { struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); #ifdef CONFIG_DM_GPIO diff --git a/drivers/net/designware.h b/drivers/net/designware.h index d345c5b0c3..087ebef297 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -245,6 +245,10 @@ struct dw_eth_dev { }; #ifdef CONFIG_DM_ETH +int designware_eth_ofdata_to_platdata(struct udevice *dev); +int designware_eth_probe(struct udevice *dev); +extern const struct eth_ops designware_eth_ops; + struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; From 0ea38db90caa55e8366c9bef4214ab52b3fedf6a Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jan 2017 11:46:08 +0100 Subject: [PATCH 13/22] net: designware: Adjust dw_adjust_link() to return an error This function can fail, so return the error if there is one. Signed-off-by: Simon Glass Signed-off-by: Romain Perier Acked-by: Joe Hershberger --- drivers/net/designware.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 6ef36bc8cb..ebcef8beaa 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -230,14 +230,14 @@ static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id) return 0; } -static void dw_adjust_link(struct eth_mac_regs *mac_p, - struct phy_device *phydev) +static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p, + struct phy_device *phydev) { u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN; if (!phydev->link) { printf("%s: No link.\n", phydev->dev->name); - return; + return 0; } if (phydev->speed != 1000) @@ -256,6 +256,8 @@ static void dw_adjust_link(struct eth_mac_regs *mac_p, printf("Speed: %d, %s duplex%s\n", phydev->speed, (phydev->duplex) ? "full" : "half", (phydev->port == PORT_FIBRE) ? ", fiber mode" : ""); + + return 0; } static void _dw_eth_halt(struct dw_eth_dev *priv) @@ -321,7 +323,9 @@ static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) return ret; } - dw_adjust_link(mac_p, priv->phydev); + ret = dw_adjust_link(priv, mac_p, priv->phydev); + if (ret) + return ret; if (!priv->phydev->link) return -EIO; From f63f28ee2520263f5c78f64f1d404b2c329ffe87 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jan 2017 11:46:09 +0100 Subject: [PATCH 14/22] net: designware: Split the link init into a separate function With rockchip we need to make adjustments after the link speed is set but before enabling received/transmit. In preparation for this, split these two pieces into separate functions. Signed-off-by: Simon Glass Signed-off-by: Romain Perier Acked-by: Joe Hershberger --- drivers/net/designware.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index ebcef8beaa..0c596a7aea 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -327,6 +327,13 @@ static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) if (ret) return ret; + return 0; +} + +static int designware_eth_enable(struct dw_eth_dev *priv) +{ + struct eth_mac_regs *mac_p = priv->mac_regs_p; + if (!priv->phydev->link) return -EIO; @@ -484,7 +491,13 @@ static int dw_phy_init(struct dw_eth_dev *priv, void *dev) #ifndef CONFIG_DM_ETH static int dw_eth_init(struct eth_device *dev, bd_t *bis) { - return _dw_eth_init(dev->priv, dev->enetaddr); + int ret; + + ret = _dw_eth_init(dev->priv, dev->enetaddr); + if (!ret) + ret = designware_eth_enable(dev->priv); + + return ret; } static int dw_eth_send(struct eth_device *dev, void *packet, int length) @@ -575,8 +588,17 @@ int designware_initialize(ulong base_addr, u32 interface) static int designware_eth_start(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + int ret; - return _dw_eth_init(dev->priv, pdata->enetaddr); + ret = _dw_eth_init(priv, pdata->enetaddr); + if (ret) + return ret; + ret = designware_eth_enable(priv); + if (ret) + return ret; + + return 0; } static int designware_eth_send(struct udevice *dev, void *packet, int length) From e72ced234045f817df48cec71b4795b00e87afe3 Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jan 2017 11:46:10 +0100 Subject: [PATCH 15/22] net: designware: Export the operation functions Export all functions so that drivers can use them, or not, as the need arises. Signed-off-by: Simon Glass Signed-off-by: Romain Perier Acked-by: Joe Hershberger --- drivers/net/designware.c | 19 +++++++++---------- drivers/net/designware.h | 9 +++++++++ 2 files changed, 18 insertions(+), 10 deletions(-) diff --git a/drivers/net/designware.c b/drivers/net/designware.c index 0c596a7aea..f242fc6b3f 100644 --- a/drivers/net/designware.c +++ b/drivers/net/designware.c @@ -271,7 +271,7 @@ static void _dw_eth_halt(struct dw_eth_dev *priv) phy_shutdown(priv->phydev); } -static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) +int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) { struct eth_mac_regs *mac_p = priv->mac_regs_p; struct eth_dma_regs *dma_p = priv->dma_regs_p; @@ -330,7 +330,7 @@ static int _dw_eth_init(struct dw_eth_dev *priv, u8 *enetaddr) return 0; } -static int designware_eth_enable(struct dw_eth_dev *priv) +int designware_eth_enable(struct dw_eth_dev *priv) { struct eth_mac_regs *mac_p = priv->mac_regs_p; @@ -493,7 +493,7 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis) { int ret; - ret = _dw_eth_init(dev->priv, dev->enetaddr); + ret = designware_eth_init(dev->priv, dev->enetaddr); if (!ret) ret = designware_eth_enable(dev->priv); @@ -591,7 +591,7 @@ static int designware_eth_start(struct udevice *dev) struct dw_eth_dev *priv = dev_get_priv(dev); int ret; - ret = _dw_eth_init(priv, pdata->enetaddr); + ret = designware_eth_init(priv, pdata->enetaddr); if (ret) return ret; ret = designware_eth_enable(priv); @@ -601,36 +601,35 @@ static int designware_eth_start(struct udevice *dev) return 0; } -static int designware_eth_send(struct udevice *dev, void *packet, int length) +int designware_eth_send(struct udevice *dev, void *packet, int length) { struct dw_eth_dev *priv = dev_get_priv(dev); return _dw_eth_send(priv, packet, length); } -static int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) +int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp) { struct dw_eth_dev *priv = dev_get_priv(dev); return _dw_eth_recv(priv, packetp); } -static int designware_eth_free_pkt(struct udevice *dev, uchar *packet, - int length) +int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length) { struct dw_eth_dev *priv = dev_get_priv(dev); return _dw_free_pkt(priv); } -static void designware_eth_stop(struct udevice *dev) +void designware_eth_stop(struct udevice *dev) { struct dw_eth_dev *priv = dev_get_priv(dev); return _dw_eth_halt(priv); } -static int designware_eth_write_hwaddr(struct udevice *dev) +int designware_eth_write_hwaddr(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct dw_eth_dev *priv = dev_get_priv(dev); diff --git a/drivers/net/designware.h b/drivers/net/designware.h index 087ebef297..7992d0ebee 100644 --- a/drivers/net/designware.h +++ b/drivers/net/designware.h @@ -253,6 +253,15 @@ struct dw_eth_pdata { struct eth_pdata eth_pdata; u32 reset_delays[3]; }; + +int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr); +int designware_eth_enable(struct dw_eth_dev *priv); +int designware_eth_send(struct udevice *dev, void *packet, int length); +int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp); +int designware_eth_free_pkt(struct udevice *dev, uchar *packet, + int length); +void designware_eth_stop(struct udevice *dev); +int designware_eth_write_hwaddr(struct udevice *dev); #endif #endif From 0125bcf01cfb0715b35ab9d5325479b3953bb966 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 11 Jan 2017 11:46:11 +0100 Subject: [PATCH 16/22] net: gmac_rockchip: Add Rockchip GMAC driver Add a new driver for the GMAC ethernet interface present in Rockchip RK3288 SOCs. This driver subclasses the generic design-ware driver to add the glue needed specifically for Rockchip. Signed-off-by: Sjoerd Simons Signed-off-by: Simon Glass Signed-off-by: Romain Perier Acked-by: Joe Hershberger --- drivers/net/Kconfig | 7 ++ drivers/net/Makefile | 1 + drivers/net/gmac_rockchip.c | 154 ++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 drivers/net/gmac_rockchip.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 929b9e273e..f52629fa53 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -215,4 +215,11 @@ config PIC32_ETH This driver implements 10/100 Mbps Ethernet and MAC layer for Microchip PIC32 microcontrollers. +config GMAC_ROCKCHIP + bool "Rockchip Synopsys Designware Ethernet MAC" + depends on DM_ETH && ETH_DESIGNWARE + help + This driver provides Rockchip SoCs network support based on the + Synopsys Designware driver. + endif # NETDEVICES diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 9a7bfc6d5b..2493a48b88 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_FTGMAC100) += ftgmac100.o obj-$(CONFIG_FTMAC110) += ftmac110.o obj-$(CONFIG_FTMAC100) += ftmac100.o obj-$(CONFIG_GRETH) += greth.o +obj-$(CONFIG_GMAC_ROCKCHIP) += gmac_rockchip.o obj-$(CONFIG_DRIVER_TI_KEYSTONE_NET) += keystone_net.o obj-$(CONFIG_KS8851_MLL) += ks8851_mll.o obj-$(CONFIG_LAN91C96) += lan91c96.o diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c new file mode 100644 index 0000000000..5f833fa711 --- /dev/null +++ b/drivers/net/gmac_rockchip.c @@ -0,0 +1,154 @@ +/* + * (C) Copyright 2015 Sjoerd Simons + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Rockchip GMAC ethernet IP driver for U-Boot + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "designware.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Platform data for the gmac + * + * dw_eth_pdata: Required platform data for designware driver (must be first) + */ +struct gmac_rockchip_platdata { + struct dw_eth_pdata dw_eth_pdata; + int tx_delay; + int rx_delay; +}; + +static int gmac_rockchip_ofdata_to_platdata(struct udevice *dev) +{ + struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + + pdata->tx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "tx-delay", 0x30); + pdata->rx_delay = fdtdec_get_int(gd->fdt_blob, dev->of_offset, + "rx-delay", 0x10); + + return designware_eth_ofdata_to_platdata(dev); +} + +static int gmac_rockchip_fix_mac_speed(struct dw_eth_dev *priv) +{ + struct rk3288_grf *grf; + int clk; + + switch (priv->phydev->speed) { + case 10: + clk = GMAC_CLK_SEL_2_5M; + break; + case 100: + clk = GMAC_CLK_SEL_25M; + break; + case 1000: + clk = GMAC_CLK_SEL_125M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + GMAC_CLK_SEL_MASK << GMAC_CLK_SEL_SHIFT, + clk << GMAC_CLK_SEL_SHIFT); + + return 0; +} + +static int gmac_rockchip_probe(struct udevice *dev) +{ + struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); + struct rk3288_grf *grf; + struct clk clk; + int ret; + + ret = clk_get_by_index(dev, 0, &clk); + if (ret) + return ret; + + /* Since mac_clk is fed by an external clock we can use 0 here */ + ret = clk_set_rate(&clk, 0); + if (ret) + return ret; + + /* Set to RGMII mode */ + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->soc_con1, + RMII_MODE_MASK << RMII_MODE_SHIFT | + GMAC_PHY_INTF_SEL_MASK << GMAC_PHY_INTF_SEL_SHIFT, + GMAC_PHY_INTF_SEL_RGMII << GMAC_PHY_INTF_SEL_SHIFT); + + rk_clrsetreg(&grf->soc_con3, + RXCLK_DLY_ENA_GMAC_MASK << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_MASK << TXCLK_DLY_ENA_GMAC_SHIFT | + CLK_RX_DL_CFG_GMAC_MASK << CLK_RX_DL_CFG_GMAC_SHIFT | + CLK_TX_DL_CFG_GMAC_MASK << CLK_TX_DL_CFG_GMAC_SHIFT, + RXCLK_DLY_ENA_GMAC_ENABLE << RXCLK_DLY_ENA_GMAC_SHIFT | + TXCLK_DLY_ENA_GMAC_ENABLE << TXCLK_DLY_ENA_GMAC_SHIFT | + pdata->rx_delay << CLK_RX_DL_CFG_GMAC_SHIFT | + pdata->tx_delay << CLK_TX_DL_CFG_GMAC_SHIFT); + + return designware_eth_probe(dev); +} + +static int gmac_rockchip_eth_start(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + struct dw_eth_dev *priv = dev_get_priv(dev); + int ret; + + ret = designware_eth_init(priv, pdata->enetaddr); + if (ret) + return ret; + ret = gmac_rockchip_fix_mac_speed(priv); + if (ret) + return ret; + ret = designware_eth_enable(priv); + if (ret) + return ret; + + return 0; +} + +const struct eth_ops gmac_rockchip_eth_ops = { + .start = gmac_rockchip_eth_start, + .send = designware_eth_send, + .recv = designware_eth_recv, + .free_pkt = designware_eth_free_pkt, + .stop = designware_eth_stop, + .write_hwaddr = designware_eth_write_hwaddr, +}; + +static const struct udevice_id rockchip_gmac_ids[] = { + { .compatible = "rockchip,rk3288-gmac" }, + { } +}; + +U_BOOT_DRIVER(eth_gmac_rockchip) = { + .name = "gmac_rockchip", + .id = UCLASS_ETH, + .of_match = rockchip_gmac_ids, + .ofdata_to_platdata = gmac_rockchip_ofdata_to_platdata, + .probe = gmac_rockchip_probe, + .ops = &gmac_rockchip_eth_ops, + .priv_auto_alloc_size = sizeof(struct dw_eth_dev), + .platdata_auto_alloc_size = sizeof(struct gmac_rockchip_platdata), + .flags = DM_FLAG_ALLOC_PRIV_DMA, +}; From 8c3018e7125c159a3190b5f8bdf2442417402920 Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 11 Jan 2017 11:46:12 +0100 Subject: [PATCH 17/22] rockchip: Enable networking support on rock2 and firefly Enable the various configuration option required to get the ethernet interface up and running on Radxa Rock2 and Firefly. Signed-off-by: Sjoerd Simons Signed-off-by: Romain Perier Reviewed-by: Simon Glass Acked-by: Joe Hershberger --- configs/firefly-rk3288_defconfig | 4 ++++ configs/rock2_defconfig | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index eb78d547bb..3ed17b4c35 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -45,6 +45,10 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index a3b0c87688..95adbdf99c 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -43,6 +43,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_NETDEVICES=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y CONFIG_PINCTRL=y CONFIG_SPL_PINCTRL=y # CONFIG_SPL_PINCTRL_FULL is not set From cea951e0bf47e2abf934c3b3c631235416a53feb Mon Sep 17 00:00:00 2001 From: Simon Glass Date: Wed, 11 Jan 2017 11:46:13 +0100 Subject: [PATCH 18/22] rockchip: evb-rk3339: Enable DHCP This is the only RK3399 device without DHCP. Enable it so that we can use a common BOOT_TARGET_DEVICES setting. It is likely useful to be able to use USB networking, at least. Full networking can be enabled when a suitable platform needs it. Signed-off-by: Simon Glass --- configs/evb-rk3399_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-rk3399_defconfig b/configs/evb-rk3399_defconfig index 6988bcb866..02d91a7561 100644 --- a/configs/evb-rk3399_defconfig +++ b/configs/evb-rk3399_defconfig @@ -11,6 +11,9 @@ CONFIG_CMD_MMC=y CONFIG_CMD_SF=y CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y CONFIG_CMD_TIME=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y From 7bdedf110d9ad2af6b92e0094393e98136280817 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Wed, 11 Jan 2017 11:46:14 +0100 Subject: [PATCH 19/22] Enable DISTRO_DEFAULTS for Rockchip platforms This enables suitable commands needed for booting general purpose Linux distribution. This is required for example if we want to use PXE or DHCP as default boot targets, symbols no longer enabled by config_distro_defaults.h . Signed-off-by: Romain Perier --- Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/Kconfig b/Kconfig index 1fa791c1cc..3f79f6fec5 100644 --- a/Kconfig +++ b/Kconfig @@ -57,6 +57,7 @@ config DISTRO_DEFAULTS bool "Select defaults suitable for booting general purpose Linux distributions" default y if ARCH_SUNXI || TEGRA default y if ARCH_LS2080A + default y if ARCH_ROCKCHIP default n select CMD_BOOTZ if ARM && !ARM64 select CMD_BOOTI if ARM64 From e9145c55d3248eb6b530d134c4f50cd154842d5d Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 11 Jan 2017 11:46:15 +0100 Subject: [PATCH 20/22] rockchip: Add PXE and DHCP to the default boot targets Now that at least on the firefly board we have network support, enable PXE and DHCP boot targets by default. Signed-off-by: Sjoerd Simons Acked-by: Simon Glass Acked-by: Joe Hershberger --- include/configs/rockchip-common.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9ec71c4baa..be53e659ee 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -14,7 +14,9 @@ /* First try to boot from SD (index 0), then eMMC (index 1 */ #define BOOT_TARGET_DEVICES(func) \ func(MMC, mmc, 0) \ - func(MMC, mmc, 1) + func(MMC, mmc, 1) \ + func(PXE, pxe, na) \ + func(DHCP, dchp, na) /* Enable gpt partition table */ #define CONFIG_CMD_GPT From 7a63efa8360148b8c12b65f596171b23611869c4 Mon Sep 17 00:00:00 2001 From: Romain Perier Date: Wed, 11 Jan 2017 11:46:16 +0100 Subject: [PATCH 21/22] rockchip: Enable ETH address randomization for the rock2 This commit enables ethernet MAC address randomization on the rock2. It removes the error at startup 'ethernet@ff290000 address not set'. Signed-off-by: Romain Perier --- configs/rock2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index 95adbdf99c..488c6f46d3 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -32,6 +32,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent" +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y From 35a05761a1aebc857e73bec7d9e72a7f84cd96ba Mon Sep 17 00:00:00 2001 From: Sjoerd Simons Date: Wed, 11 Jan 2017 11:46:17 +0100 Subject: [PATCH 22/22] rockchip: Drop Ethernet from the TODO Now that ethernet support works, it can be dropped from the rockchip TODO Signed-off-by: Sjoerd Simons Acked-by: Simon Glass Acked-by: Joe Hershberger Signed-off-by: Simon Glass --- doc/README.rockchip | 1 - 1 file changed, 1 deletion(-) diff --git a/doc/README.rockchip b/doc/README.rockchip index 06ec80e523..43cafc7bd6 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -219,7 +219,6 @@ Immediate priorities are: - USB host - USB device - Run CPU at full speed (code exists but we only see ~60 DMIPS maximum) -- Ethernet - NAND flash - Support for other Rockchip parts - Boot U-Boot proper over USB OTG (at present only SPL works)