leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ARM: tegra: Tegra20 pinmux cleanup

Browse Source 
This renames all the Tegra20 pinmux pins and functions so they have a
prefix which matches the type name.

The entries in tegra20_pingroups[] are all updated to remove the columns
which are no longer used.

All affected code is updated to match.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit is contained in:
Stephen Warren 2014-03-21 12:28:58 -06:00 committed by Tom Warren
parent dfb42fc95d
commit 70ad375ee4
12 changed files with 375 additions and 390 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

175
arch/arm/cpu/tegra20-common/funcmux.c
View File

@ -14,7 +14,7 @@
* The PINMUX macro is used to set up pinmux tables.
*/
#define PINMUX(grp, mux, pupd, tri) \
{PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
{PMUX_PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri}
static const struct pmux_pingrp_config disp1_default[] = {
PINMUX(LDI, DISPA, NORMAL, NORMAL),
@ -42,26 +42,26 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_UART1:
switch (config) {
case FUNCMUX_UART1_IRRX_IRTX:
pinmux_set_func(PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_IRRX);
pinmux_tristate_disable(PINGRP_IRTX);
pinmux_set_func(PMUX_PINGRP_IRRX, PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_IRTX, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_IRRX);
pinmux_tristate_disable(PMUX_PINGRP_IRTX);
break;
case FUNCMUX_UART1_UAA_UAB:
pinmux_set_func(PINGRP_UAA, PMUX_FUNC_UARTA);
pinmux_set_func(PINGRP_UAB, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_UAA);
pinmux_tristate_disable(PINGRP_UAB);
pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_UARTA);
pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_UAA);
pinmux_tristate_disable(PMUX_PINGRP_UAB);
bad_config = 0;
break;
case FUNCMUX_UART1_GPU:
pinmux_set_func(PINGRP_GPU, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_GPU);
pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_GPU);
bad_config = 0;
break;
case FUNCMUX_UART1_SDIO1:
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PINGRP_SDIO1);
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_UARTA);
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
bad_config = 0;
break;
}
@ -77,53 +77,53 @@ int funcmux_select(enum periph_id id, int config)
* state the group to avoid driving any signal onto it
* until we know what's connected.
*/
pinmux_tristate_enable(PINGRP_SDB);
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_tristate_enable(PMUX_PINGRP_SDB);
pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
}
break;
case PERIPH_ID_UART2:
if (config == FUNCMUX_UART2_UAD) {
pinmux_set_func(PINGRP_UAD, PMUX_FUNC_UARTB);
pinmux_tristate_disable(PINGRP_UAD);
pinmux_set_func(PMUX_PINGRP_UAD, PMUX_FUNC_UARTB);
pinmux_tristate_disable(PMUX_PINGRP_UAD);
}
break;
case PERIPH_ID_UART4:
if (config == FUNCMUX_UART4_GMC) {
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PINGRP_GMC);
pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_UARTD);
pinmux_tristate_disable(PMUX_PINGRP_GMC);
}
break;
case PERIPH_ID_DVC_I2C:
/* there is only one selection, pinmux_config is ignored */
if (config == FUNCMUX_DVC_I2CP) {
pinmux_set_func(PINGRP_I2CP, PMUX_FUNC_I2C);
pinmux_tristate_disable(PINGRP_I2CP);
pinmux_set_func(PMUX_PINGRP_I2CP, PMUX_FUNC_I2C);
pinmux_tristate_disable(PMUX_PINGRP_I2CP);
}
break;
case PERIPH_ID_I2C1:
/* support pinmux_config of 0 for now, */
if (config == FUNCMUX_I2C1_RM) {
pinmux_set_func(PINGRP_RM, PMUX_FUNC_I2C);
pinmux_tristate_disable(PINGRP_RM);
pinmux_set_func(PMUX_PINGRP_RM, PMUX_FUNC_I2C);
pinmux_tristate_disable(PMUX_PINGRP_RM);
}
break;
case PERIPH_ID_I2C2: /* I2C2 */
switch (config) {
case FUNCMUX_I2C2_DDC: /* DDC pin group, select I2C2 */
pinmux_set_func(PINGRP_DDC, PMUX_FUNC_I2C2);
pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_I2C2);
/* PTA to HDMI */
pinmux_set_func(PINGRP_PTA, PMUX_FUNC_HDMI);
pinmux_tristate_disable(PINGRP_DDC);
pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_HDMI);
pinmux_tristate_disable(PMUX_PINGRP_DDC);
break;
case FUNCMUX_I2C2_PTA: /* PTA pin group, select I2C2 */
pinmux_set_func(PINGRP_PTA, PMUX_FUNC_I2C2);
pinmux_set_func(PMUX_PINGRP_PTA, PMUX_FUNC_I2C2);
/* set DDC_SEL to RSVDx (RSVD2 works for now) */
pinmux_set_func(PINGRP_DDC, PMUX_FUNC_RSVD2);
pinmux_tristate_disable(PINGRP_PTA);
pinmux_set_func(PMUX_PINGRP_DDC, PMUX_FUNC_RSVD2);
pinmux_tristate_disable(PMUX_PINGRP_PTA);
bad_config = 0;
break;
}
@ -131,50 +131,50 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_I2C3: /* I2C3 */
/* support pinmux_config of 0 for now */
if (config == FUNCMUX_I2C3_DTF) {
pinmux_set_func(PINGRP_DTF, PMUX_FUNC_I2C3);
pinmux_tristate_disable(PINGRP_DTF);
pinmux_set_func(PMUX_PINGRP_DTF, PMUX_FUNC_I2C3);
pinmux_tristate_disable(PMUX_PINGRP_DTF);
}
break;
case PERIPH_ID_SDMMC1:
if (config == FUNCMUX_SDMMC1_SDIO1_4BIT) {
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PINGRP_SDIO1);
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
}
break;
case PERIPH_ID_SDMMC2:
if (config == FUNCMUX_SDMMC2_DTA_DTD_8BIT) {
pinmux_set_func(PINGRP_DTA, PMUX_FUNC_SDIO2);
pinmux_set_func(PINGRP_DTD, PMUX_FUNC_SDIO2);
pinmux_set_func(PMUX_PINGRP_DTA, PMUX_FUNC_SDIO2);
pinmux_set_func(PMUX_PINGRP_DTD, PMUX_FUNC_SDIO2);
pinmux_tristate_disable(PINGRP_DTA);
pinmux_tristate_disable(PINGRP_DTD);
pinmux_tristate_disable(PMUX_PINGRP_DTA);
pinmux_tristate_disable(PMUX_PINGRP_DTD);
}
break;
case PERIPH_ID_SDMMC3:
switch (config) {
case FUNCMUX_SDMMC3_SDB_SLXA_8BIT:
pinmux_set_func(PINGRP_SLXA, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXC, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXD, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SLXK, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXA, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXC, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXD, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SLXK, PMUX_FUNC_SDIO3);
pinmux_tristate_disable(PINGRP_SLXA);
pinmux_tristate_disable(PINGRP_SLXC);
pinmux_tristate_disable(PINGRP_SLXD);
pinmux_tristate_disable(PINGRP_SLXK);
pinmux_tristate_disable(PMUX_PINGRP_SLXA);
pinmux_tristate_disable(PMUX_PINGRP_SLXC);
pinmux_tristate_disable(PMUX_PINGRP_SLXD);
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
/* fall through */
case FUNCMUX_SDMMC3_SDB_4BIT:
pinmux_set_func(PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SDC, PMUX_FUNC_SDIO3);
pinmux_set_func(PINGRP_SDD, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDB, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_SDIO3);
pinmux_set_func(PMUX_PINGRP_SDD, PMUX_FUNC_SDIO3);
pinmux_tristate_disable(PINGRP_SDB);
pinmux_tristate_disable(PINGRP_SDC);
pinmux_tristate_disable(PINGRP_SDD);
pinmux_tristate_disable(PMUX_PINGRP_SDB);
pinmux_tristate_disable(PMUX_PINGRP_SDC);
pinmux_tristate_disable(PMUX_PINGRP_SDD);
bad_config = 0;
break;
}
@ -183,24 +183,24 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_SDMMC4:
switch (config) {
case FUNCMUX_SDMMC4_ATC_ATD_8BIT:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_ATD, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATD, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATC);
pinmux_tristate_disable(PINGRP_ATD);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
pinmux_tristate_disable(PMUX_PINGRP_ATD);
break;
case FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT:
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_GME);
pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PMUX_PINGRP_GME);
/* fall through */
case FUNCMUX_SDMMC4_ATB_GMA_4_BIT:
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATB);
pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PMUX_PINGRP_ATB);
pinmux_tristate_disable(PMUX_PINGRP_GMA);
bad_config = 0;
break;
}
@ -208,9 +208,10 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_KBC:
if (config == FUNCMUX_DEFAULT) {
enum pmux_pingrp grp[] = {PINGRP_KBCA, PINGRP_KBCB,
PINGRP_KBCC, PINGRP_KBCD, PINGRP_KBCE,
PINGRP_KBCF};
enum pmux_pingrp grp[] = {PMUX_PINGRP_KBCA,
PMUX_PINGRP_KBCB, PMUX_PINGRP_KBCC,
PMUX_PINGRP_KBCD, PMUX_PINGRP_KBCE,
PMUX_PINGRP_KBCF};
int i;
for (i = 0; i < ARRAY_SIZE(grp); i++) {
@ -223,44 +224,44 @@ int funcmux_select(enum periph_id id, int config)
case PERIPH_ID_USB2:
if (config == FUNCMUX_USB2_ULPI) {
pinmux_set_func(PINGRP_UAA, PMUX_FUNC_ULPI);
pinmux_set_func(PINGRP_UAB, PMUX_FUNC_ULPI);
pinmux_set_func(PINGRP_UDA, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UAA, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UAB, PMUX_FUNC_ULPI);
pinmux_set_func(PMUX_PINGRP_UDA, PMUX_FUNC_ULPI);
pinmux_tristate_disable(PINGRP_UAA);
pinmux_tristate_disable(PINGRP_UAB);
pinmux_tristate_disable(PINGRP_UDA);
pinmux_tristate_disable(PMUX_PINGRP_UAA);
pinmux_tristate_disable(PMUX_PINGRP_UAB);
pinmux_tristate_disable(PMUX_PINGRP_UDA);
}
break;
case PERIPH_ID_SPI1:
if (config == FUNCMUX_SPI1_GMC_GMD) {
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_tristate_disable(PINGRP_GMC);
pinmux_tristate_disable(PINGRP_GMD);
pinmux_tristate_disable(PMUX_PINGRP_GMC);
pinmux_tristate_disable(PMUX_PINGRP_GMD);
}
break;
case PERIPH_ID_NDFLASH:
switch (config) {
case FUNCMUX_NDFLASH_ATC:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_ATC);
pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
break;
case FUNCMUX_NDFLASH_KBC_8_BIT:
pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCA, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCC, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCD, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCE, PMUX_FUNC_NAND);
pinmux_set_func(PMUX_PINGRP_KBCF, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_KBCA);
pinmux_tristate_disable(PINGRP_KBCC);
pinmux_tristate_disable(PINGRP_KBCD);
pinmux_tristate_disable(PINGRP_KBCE);
pinmux_tristate_disable(PINGRP_KBCF);
pinmux_tristate_disable(PMUX_PINGRP_KBCA);
pinmux_tristate_disable(PMUX_PINGRP_KBCC);
pinmux_tristate_disable(PMUX_PINGRP_KBCD);
pinmux_tristate_disable(PMUX_PINGRP_KBCE);
pinmux_tristate_disable(PMUX_PINGRP_KBCF);
bad_config = 0;
break;
@ -270,7 +271,7 @@ int funcmux_select(enum periph_id id, int config)
if (config == FUNCMUX_DEFAULT) {
int i;
for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) {
for (i = PMUX_PINGRP_LD0; i <= PMUX_PINGRP_LD17; i++) {
pinmux_set_func(i, PMUX_FUNC_DISPA);
pinmux_tristate_disable(i);
pinmux_set_pullupdown(i, PMUX_PULL_NORMAL);

268
arch/arm/cpu/tegra20-common/pinmux.c
View File

@ -255,183 +255,171 @@ enum pmux_pullid {
};
/* Convenient macro for defining pin group properties */
#define PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, mux, pupd) \
#define PINALL(pingrp, f0, f1, f2, f3, mux, pupd) \
{ \
.funcs = { \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
PMUX_FUNC_ ## f0, \
PMUX_FUNC_ ## f1, \
PMUX_FUNC_ ## f2, \
PMUX_FUNC_ ## f3, \
}, \
.ctl_id = mux, \
.pull_id = pupd \
}
/* A normal pin group where the mux name and pull-up name match */
#define PIN(pg_name, vdd, f0, f1, f2, f3, f_safe) \
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
MUXCTL_ ## pg_name, PUCTL_ ## pg_name)
#define PIN(pingrp, f0, f1, f2, f3) \
PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pingrp)
/* A pin group where the pull-up name doesn't have a 1-1 mapping */
#define PINP(pg_name, vdd, f0, f1, f2, f3, f_safe, pupd) \
PINALL(pg_name, vdd, f0, f1, f2, f3, f_safe, \
MUXCTL_ ## pg_name, PUCTL_ ## pupd)
#define PINP(pingrp, f0, f1, f2, f3, pupd) \
PINALL(pingrp, f0, f1, f2, f3, MUXCTL_##pingrp, PUCTL_##pupd)
/* A pin group number which is not used */
#define PIN_RESERVED \
PIN(NONE, NONE, RSVD, RSVD, RSVD, RSVD, RSVD)
PIN(NONE, RSVD1, RSVD2, RSVD3, RSVD4)
#define PMUX_FUNC_RSVD PMUX_FUNC_RSVD1
#define DRVGRP(drvgrp) \
PINALL(drvgrp, RSVD1, RSVD2, RSVD3, RSVD4, MUXCTL_NONE, PUCTL_NONE)
static const struct pmux_pingrp_desc tegra20_pingroups[] = {
PIN(ATA, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(ATB, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATC, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(ATD, NAND, IDE, NAND, GMI, SDIO4, IDE),
PIN(CDEV1, AUDIO, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC, OSC),
PIN(CDEV2, AUDIO, OSC, AHB_CLK, APB_CLK, PLLP_OUT4, OSC),
PIN(CSUS, VI, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK,
PLLC_OUT1),
PIN(DAP1, AUDIO, DAP1, RSVD, GMI, SDIO2, DAP1),
PIN(ATA, IDE, NAND, GMI, RSVD4),
PIN(ATB, IDE, NAND, GMI, SDIO4),
PIN(ATC, IDE, NAND, GMI, SDIO4),
PIN(ATD, IDE, NAND, GMI, SDIO4),
PIN(CDEV1, OSC, PLLA_OUT, PLLM_OUT1, AUDIO_SYNC),
PIN(CDEV2, OSC, AHB_CLK, APB_CLK, PLLP_OUT4),
PIN(CSUS, PLLC_OUT1, PLLP_OUT2, PLLP_OUT3, VI_SENSOR_CLK),
PIN(DAP1, DAP1, RSVD2, GMI, SDIO2),
PIN(DAP2, AUDIO, DAP2, TWC, RSVD, GMI, DAP2),
PIN(DAP3, BB, DAP3, RSVD, RSVD, RSVD, DAP3),
PIN(DAP4, UART, DAP4, RSVD, GMI, RSVD, DAP4),
PIN(DTA, VI, RSVD, SDIO2, VI, RSVD, RSVD4),
PIN(DTB, VI, RSVD, RSVD, VI, SPI1, RSVD1),
PIN(DTC, VI, RSVD, RSVD, VI, RSVD, RSVD1),
PIN(DTD, VI, RSVD, SDIO2, VI, RSVD, RSVD1),
PIN(DTE, VI, RSVD, RSVD, VI, SPI1, RSVD1),
PIN(DAP2, DAP2, TWC, RSVD3, GMI),
PIN(DAP3, DAP3, RSVD2, RSVD3, RSVD4),
PIN(DAP4, DAP4, RSVD2, GMI, RSVD4),
PIN(DTA, RSVD1, SDIO2, VI, RSVD4),
PIN(DTB, RSVD1, RSVD2, VI, SPI1),
PIN(DTC, RSVD1, RSVD2, VI, RSVD4),
PIN(DTD, RSVD1, SDIO2, VI, RSVD4),
PIN(DTE, RSVD1, RSVD2, VI, SPI1),
PINP(GPU, UART, PWM, UARTA, GMI, RSVD, RSVD4,
GPSLXAU),
PIN(GPV, SD, PCIE, RSVD, RSVD, RSVD, PCIE),
PIN(I2CP, SYS, I2C, RSVD, RSVD, RSVD, RSVD4),
PIN(IRTX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
PIN(IRRX, UART, UARTA, UARTB, GMI, SPI4, UARTB),
PIN(KBCB, SYS, KBC, NAND, SDIO2, MIO, KBC),
PIN(KBCA, SYS, KBC, NAND, SDIO2, EMC_TEST0_DLL, KBC),
PINP(PMC, SYS, PWR_ON, PWR_INTR, RSVD, RSVD, PWR_ON, NONE),
PINP(GPU, PWM, UARTA, GMI, RSVD4, GPSLXAU),
PIN(GPV, PCIE, RSVD2, RSVD3, RSVD4),
PIN(I2CP, I2C, RSVD2, RSVD3, RSVD4),
PIN(IRTX, UARTA, UARTB, GMI, SPI4),
PIN(IRRX, UARTA, UARTB, GMI, SPI4),
PIN(KBCB, KBC, NAND, SDIO2, MIO),
PIN(KBCA, KBC, NAND, SDIO2, EMC_TEST0_DLL),
PINP(PMC, PWR_ON, PWR_INTR, RSVD3, RSVD4, NONE),
PIN(PTA, NAND, I2C2, HDMI, GMI, RSVD, RSVD4),
PIN(RM, UART, I2C, RSVD, RSVD, RSVD, RSVD4),
PIN(KBCE, SYS, KBC, NAND, OWR, RSVD, KBC),
PIN(KBCF, SYS, KBC, NAND, TRACE, MIO, KBC),
PIN(GMA, NAND, UARTE, SPI3, GMI, SDIO4, SPI3),
PIN(GMC, NAND, UARTD, SPI4, GMI, SFLASH, SPI4),
PIN(SDMMC1, BB, SDIO1, RSVD, UARTE, UARTA, RSVD2),
PIN(OWC, SYS, OWR, RSVD, RSVD, RSVD, OWR),
PIN(PTA, I2C2, HDMI, GMI, RSVD4),
PIN(RM, I2C, RSVD2, RSVD3, RSVD4),
PIN(KBCE, KBC, NAND, OWR, RSVD4),
PIN(KBCF, KBC, NAND, TRACE, MIO),
PIN(GMA, UARTE, SPI3, GMI, SDIO4),
PIN(GMC, UARTD, SPI4, GMI, SFLASH),
PIN(SDMMC1, SDIO1, RSVD2, UARTE, UARTA),
PIN(OWC, OWR, RSVD2, RSVD3, RSVD4),
PIN(GME, NAND, RSVD, DAP5, GMI, SDIO4, GMI),
PIN(SDC, SD, PWM, TWC, SDIO3, SPI3, TWC),
PIN(SDD, SD, UARTA, PWM, SDIO3, SPI3, PWM),
PIN(GME, RSVD1, DAP5, GMI, SDIO4),
PIN(SDC, PWM, TWC, SDIO3, SPI3),
PIN(SDD, UARTA, PWM, SDIO3, SPI3),
PIN_RESERVED,
PINP(SLXA, SD, PCIE, SPI4, SDIO3, SPI2, PCIE, CRTP),
PIN(SLXC, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
PIN(SLXD, SD, SPDIF, SPI4, SDIO3, SPI2, SPI4),
PIN(SLXK, SD, PCIE, SPI4, SDIO3, SPI2, PCIE),
PINP(SLXA, PCIE, SPI4, SDIO3, SPI2, CRTP),
PIN(SLXC, SPDIF, SPI4, SDIO3, SPI2),
PIN(SLXD, SPDIF, SPI4, SDIO3, SPI2),
PIN(SLXK, PCIE, SPI4, SDIO3, SPI2),
PIN(SPDI, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
PIN(SPDO, AUDIO, SPDIF, RSVD, I2C, SDIO2, RSVD2),
PIN(SPIA, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPIB, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPIC, AUDIO, SPI1, SPI2, SPI3, GMI, GMI),
PIN(SPID, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
PIN(SPIE, AUDIO, SPI2, SPI1, SPI2_ALT, GMI, GMI),
PIN(SPIF, AUDIO, SPI3, SPI1, SPI2, RSVD, RSVD4),
PIN(SPDI, SPDIF, RSVD2, I2C, SDIO2),
PIN(SPDO, SPDIF, RSVD2, I2C, SDIO2),
PIN(SPIA, SPI1, SPI2, SPI3, GMI),
PIN(SPIB, SPI1, SPI2, SPI3, GMI),
PIN(SPIC, SPI1, SPI2, SPI3, GMI),
PIN(SPID, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPIE, SPI2, SPI1, SPI2_ALT, GMI),
PIN(SPIF, SPI3, SPI1, SPI2, RSVD4),
PIN(SPIG, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
PIN(SPIH, AUDIO, SPI3, SPI2, SPI2_ALT, I2C, SPI2_ALT),
PIN(UAA, BB, SPI3, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAB, BB, SPI2, MIPI_HS, UARTA, ULPI, MIPI_HS),
PIN(UAC, BB, OWR, RSVD, RSVD, RSVD, RSVD4),
PIN(UAD, UART, UARTB, SPDIF, UARTA, SPI4, SPDIF),
PIN(UCA, UART, UARTC, RSVD, GMI, RSVD, RSVD4),
PIN(UCB, UART, UARTC, PWM, GMI, RSVD, RSVD4),
PIN(SPIG, SPI3, SPI2, SPI2_ALT, I2C),
PIN(SPIH, SPI3, SPI2, SPI2_ALT, I2C),
PIN(UAA, SPI3, MIPI_HS, UARTA, ULPI),
PIN(UAB, SPI2, MIPI_HS, UARTA, ULPI),
PIN(UAC, OWR, RSVD2, RSVD3, RSVD4),
PIN(UAD, UARTB, SPDIF, UARTA, SPI4),
PIN(UCA, UARTC, RSVD2, GMI, RSVD4),
PIN(UCB, UARTC, PWM, GMI, RSVD4),
PIN_RESERVED,
PIN(ATE, NAND, IDE, NAND, GMI, RSVD, IDE),
PIN(KBCC, SYS, KBC, NAND, TRACE, EMC_TEST1_DLL, KBC),
PIN(ATE, IDE, NAND, GMI, RSVD4),
PIN(KBCC, KBC, NAND, TRACE, EMC_TEST1_DLL),
PIN_RESERVED,
PIN_RESERVED,
PIN(GMB, NAND, IDE, NAND, GMI, GMI_INT, GMI),
PIN(GMD, NAND, RSVD, NAND, GMI, SFLASH, GMI),
PIN(DDC, LCD, I2C2, RSVD, RSVD, RSVD, RSVD4),
PIN(GMB, IDE, NAND, GMI, GMI_INT),
PIN(GMD, RSVD1, NAND, GMI, SFLASH),
PIN(DDC, I2C2, RSVD2, RSVD3, RSVD4),
/* 64 */
PINP(LD0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD1, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD2, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD3, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD4, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD5, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD6, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD7, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD0, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD1, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD2, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD3, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD4, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD5, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD6, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD7, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD8, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD9, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD10, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD11, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD12, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD13, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD14, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD15, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD8, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD9, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD10, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD11, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD12, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD13, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD14, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD15, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD16, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LD17),
PINP(LD17, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD17),
PINP(LHP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
PINP(LHP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
PINP(LHP2, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD19_18),
PINP(LVP0, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LC),
PINP(LVP1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD21_20),
PINP(HDINT, LCD, HDMI, RSVD, RSVD, RSVD, HDMI , LC),
PINP(LD16, DISPA, DISPB, XIO, RSVD4, LD17),
PINP(LD17, DISPA, DISPB, RSVD3, RSVD4, LD17),
PINP(LHP0, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
PINP(LHP1, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
PINP(LHP2, DISPA, DISPB, RSVD3, RSVD4, LD19_18),
PINP(LVP0, DISPA, DISPB, RSVD3, RSVD4, LC),
PINP(LVP1, DISPA, DISPB, RSVD3, RSVD4, LD21_20),
PINP(HDINT, HDMI, RSVD2, RSVD3, RSVD4, LC),
PINP(LM0, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LC),
PINP(LM1, LCD, DISPA, DISPB, RSVD, CRT, RSVD3, LC),
PINP(LVS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSC0, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSC1, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LSCK, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LDC, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
PINP(LCSN, LCD, DISPA, DISPB, SPI3, RSVD, RSVD4, LS),
PINP(LM0, DISPA, DISPB, SPI3, RSVD4, LC),
PINP(LM1, DISPA, DISPB, RSVD3, CRT, LC),
PINP(LVS, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LSC0, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LSC1, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LSCK, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LDC, DISPA, DISPB, RSVD3, RSVD4, LS),
PINP(LCSN, DISPA, DISPB, SPI3, RSVD4, LS),
/* 96 */
PINP(LSPI, LCD, DISPA, DISPB, XIO, HDMI, DISPA, LC),
PINP(LSDA, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LSDI, LCD, DISPA, DISPB, SPI3, RSVD, DISPA, LS),
PINP(LPW0, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LPW1, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LS),
PINP(LPW2, LCD, DISPA, DISPB, SPI3, HDMI, DISPA, LS),
PINP(LDI, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
PINP(LHS, LCD, DISPA, DISPB, XIO, RSVD, RSVD4, LC),
PINP(LSPI, DISPA, DISPB, XIO, HDMI, LC),
PINP(LSDA, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LSDI, DISPA, DISPB, SPI3, RSVD4, LS),
PINP(LPW0, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LPW1, DISPA, DISPB, RSVD3, RSVD4, LS),
PINP(LPW2, DISPA, DISPB, SPI3, HDMI, LS),
PINP(LDI, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PINP(LHS, DISPA, DISPB, XIO, RSVD4, LC),
PINP(LPP, LCD, DISPA, DISPB, RSVD, RSVD, RSVD4, LD23_22),
PINP(LPP, DISPA, DISPB, RSVD3, RSVD4, LD23_22),
PIN_RESERVED,
PIN(KBCD, SYS, KBC, NAND, SDIO2, MIO, KBC),
PIN(GPU7, SYS, RTCK, RSVD, RSVD, RSVD, RTCK),
PIN(DTF, VI, I2C3, RSVD, VI, RSVD, RSVD4),
PIN(UDA, BB, SPI1, RSVD, UARTD, ULPI, RSVD2),
PIN(CRTP, LCD, CRT, RSVD, RSVD, RSVD, RSVD),
PINP(SDB, SD, UARTA, PWM, SDIO3, SPI2, PWM, NONE),
PIN(KBCD, KBC, NAND, SDIO2, MIO),
PIN(GPU7, RTCK, RSVD2, RSVD3, RSVD4),
PIN(DTF, I2C3, RSVD2, VI, RSVD4),
PIN(UDA, SPI1, RSVD2, UARTD, ULPI),
PIN(CRTP, CRT, RSVD2, RSVD3, RSVD4),
PINP(SDB, UARTA, PWM, SDIO3, SPI2, NONE),
/* these pin groups only have pullup and pull down control */
PINALL(CK32, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(DDRC, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCA, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCB, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCC, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCD, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(PMCE, SYS, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(XM2C, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
PINALL(XM2D, DDR, RSVD, RSVD, RSVD, RSVD, RSVD, MUXCTL_NONE,
PUCTL_NONE),
DRVGRP(CK32),
DRVGRP(DDRC),
DRVGRP(PMCA),
DRVGRP(PMCB),
DRVGRP(PMCC),
DRVGRP(PMCD),
DRVGRP(PMCE),
DRVGRP(XM2C),
DRVGRP(XM2D),
};
const struct pmux_pingrp_desc *tegra_soc_pingroups = tegra20_pingroups;

246
arch/arm/include/asm/arch-tegra20/pinmux.h
View File

@ -18,147 +18,145 @@
*/
enum pmux_pingrp {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
PINGRP_ATA,
PINGRP_ATB,
PINGRP_ATC,
PINGRP_ATD,
PINGRP_CDEV1,
PINGRP_CDEV2,
PINGRP_CSUS,
PINGRP_DAP1,
PMUX_PINGRP_ATA,
PMUX_PINGRP_ATB,
PMUX_PINGRP_ATC,
PMUX_PINGRP_ATD,
PMUX_PINGRP_CDEV1,
PMUX_PINGRP_CDEV2,
PMUX_PINGRP_CSUS,
PMUX_PINGRP_DAP1,
PINGRP_DAP2,
PINGRP_DAP3,
PINGRP_DAP4,
PINGRP_DTA,
PINGRP_DTB,
PINGRP_DTC,
PINGRP_DTD,
PINGRP_DTE,
PMUX_PINGRP_DAP2,
PMUX_PINGRP_DAP3,
PMUX_PINGRP_DAP4,
PMUX_PINGRP_DTA,
PMUX_PINGRP_DTB,
PMUX_PINGRP_DTC,
PMUX_PINGRP_DTD,
PMUX_PINGRP_DTE,
PINGRP_GPU,
PINGRP_GPV,
PINGRP_I2CP,
PINGRP_IRTX,
PINGRP_IRRX,
PINGRP_KBCB,
PINGRP_KBCA,
PINGRP_PMC,
PMUX_PINGRP_GPU,
PMUX_PINGRP_GPV,
PMUX_PINGRP_I2CP,
PMUX_PINGRP_IRTX,
PMUX_PINGRP_IRRX,
PMUX_PINGRP_KBCB,
PMUX_PINGRP_KBCA,
PMUX_PINGRP_PMC,
PINGRP_PTA,
PINGRP_RM,
PINGRP_KBCE,
PINGRP_KBCF,
PINGRP_GMA,
PINGRP_GMC,
PINGRP_SDIO1,
PINGRP_OWC,
PMUX_PINGRP_PTA,
PMUX_PINGRP_RM,
PMUX_PINGRP_KBCE,
PMUX_PINGRP_KBCF,
PMUX_PINGRP_GMA,
PMUX_PINGRP_GMC,
PMUX_PINGRP_SDIO1,
PMUX_PINGRP_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
PINGRP_GME,
PINGRP_SDC,
PINGRP_SDD,
PINGRP_RESERVED0,
PINGRP_SLXA,
PINGRP_SLXC,
PINGRP_SLXD,
PINGRP_SLXK,
PMUX_PINGRP_GME,
PMUX_PINGRP_SDC,
PMUX_PINGRP_SDD,
PMUX_PINGRP_RESERVED0,
PMUX_PINGRP_SLXA,
PMUX_PINGRP_SLXC,
PMUX_PINGRP_SLXD,
PMUX_PINGRP_SLXK,
PINGRP_SPDI,
PINGRP_SPDO,
PINGRP_SPIA,
PINGRP_SPIB,
PINGRP_SPIC,
PINGRP_SPID,
PINGRP_SPIE,
PINGRP_SPIF,
PMUX_PINGRP_SPDI,
PMUX_PINGRP_SPDO,
PMUX_PINGRP_SPIA,
PMUX_PINGRP_SPIB,
PMUX_PINGRP_SPIC,
PMUX_PINGRP_SPID,
PMUX_PINGRP_SPIE,
PMUX_PINGRP_SPIF,
PINGRP_SPIG,
PINGRP_SPIH,
PINGRP_UAA,
PINGRP_UAB,
PINGRP_UAC,
PINGRP_UAD,
PINGRP_UCA,
PINGRP_UCB,
PMUX_PINGRP_SPIG,
PMUX_PINGRP_SPIH,
PMUX_PINGRP_UAA,
PMUX_PINGRP_UAB,
PMUX_PINGRP_UAC,
PMUX_PINGRP_UAD,
PMUX_PINGRP_UCA,
PMUX_PINGRP_UCB,
PINGRP_RESERVED1,
PINGRP_ATE,
PINGRP_KBCC,
PINGRP_RESERVED2,
PINGRP_RESERVED3,
PINGRP_GMB,
PINGRP_GMD,
PINGRP_DDC,
PMUX_PINGRP_RESERVED1,
PMUX_PINGRP_ATE,
PMUX_PINGRP_KBCC,
PMUX_PINGRP_RESERVED2,
PMUX_PINGRP_RESERVED3,
PMUX_PINGRP_GMB,
PMUX_PINGRP_GMD,
PMUX_PINGRP_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
PINGRP_LD0,
PINGRP_LD1,
PINGRP_LD2,
PINGRP_LD3,
PINGRP_LD4,
PINGRP_LD5,
PINGRP_LD6,
PINGRP_LD7,
PMUX_PINGRP_LD0,
PMUX_PINGRP_LD1,
PMUX_PINGRP_LD2,
PMUX_PINGRP_LD3,
PMUX_PINGRP_LD4,
PMUX_PINGRP_LD5,
PMUX_PINGRP_LD6,
PMUX_PINGRP_LD7,
PINGRP_LD8,
PINGRP_LD9,
PINGRP_LD10,
PINGRP_LD11,
PINGRP_LD12,
PINGRP_LD13,
PINGRP_LD14,
PINGRP_LD15,
PMUX_PINGRP_LD8,
PMUX_PINGRP_LD9,
PMUX_PINGRP_LD10,
PMUX_PINGRP_LD11,
PMUX_PINGRP_LD12,
PMUX_PINGRP_LD13,
PMUX_PINGRP_LD14,
PMUX_PINGRP_LD15,
PINGRP_LD16,
PINGRP_LD17,
PINGRP_LHP0,
PINGRP_LHP1,
PINGRP_LHP2,
PINGRP_LVP0,
PINGRP_LVP1,
PINGRP_HDINT,
PMUX_PINGRP_LD16,
PMUX_PINGRP_LD17,
PMUX_PINGRP_LHP0,
PMUX_PINGRP_LHP1,
PMUX_PINGRP_LHP2,
PMUX_PINGRP_LVP0,
PMUX_PINGRP_LVP1,
PMUX_PINGRP_HDINT,
PINGRP_LM0,
PINGRP_LM1,
PINGRP_LVS,
PINGRP_LSC0,
PINGRP_LSC1,
PINGRP_LSCK,
PINGRP_LDC,
PINGRP_LCSN,
PMUX_PINGRP_LM0,
PMUX_PINGRP_LM1,
PMUX_PINGRP_LVS,
PMUX_PINGRP_LSC0,
PMUX_PINGRP_LSC1,
PMUX_PINGRP_LSCK,
PMUX_PINGRP_LDC,
PMUX_PINGRP_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
PINGRP_LSPI,
PINGRP_LSDA,
PINGRP_LSDI,
PINGRP_LPW0,
PINGRP_LPW1,
PINGRP_LPW2,
PINGRP_LDI,
PINGRP_LHS,
PMUX_PINGRP_LSPI,
PMUX_PINGRP_LSDA,
PMUX_PINGRP_LSDI,
PMUX_PINGRP_LPW0,
PMUX_PINGRP_LPW1,
PMUX_PINGRP_LPW2,
PMUX_PINGRP_LDI,
PMUX_PINGRP_LHS,
PINGRP_LPP,
PINGRP_RESERVED4,
PINGRP_KBCD,
PINGRP_GPU7,
PINGRP_DTF,
PINGRP_UDA,
PINGRP_CRTP,
PINGRP_SDB,
PMUX_PINGRP_LPP,
PMUX_PINGRP_RESERVED4,
PMUX_PINGRP_KBCD,
PMUX_PINGRP_GPU7,
PMUX_PINGRP_DTF,
PMUX_PINGRP_UDA,
PMUX_PINGRP_CRTP,
PMUX_PINGRP_SDB,
/* these pin groups only have pullup and pull down control */
PINGRP_FIRST_NO_MUX,
PINGRP_CK32 = PINGRP_FIRST_NO_MUX,
PINGRP_DDRC,
PINGRP_PMCA,
PINGRP_PMCB,
PINGRP_PMCC,
PINGRP_PMCD,
PINGRP_PMCE,
PINGRP_XM2C,
PINGRP_XM2D,
PMUX_PINGRP_CK32,
PMUX_PINGRP_DDRC,
PMUX_PINGRP_PMCA,
PMUX_PINGRP_PMCB,
PMUX_PINGRP_PMCC,
PMUX_PINGRP_PMCD,
PMUX_PINGRP_PMCE,
PMUX_PINGRP_XM2C,
PMUX_PINGRP_XM2D,
PMUX_PINGRP_COUNT,
};
@ -227,9 +225,7 @@ enum pmux_func {
PMUX_FUNC_VI,
PMUX_FUNC_VI_SENSOR_CLK,
PMUX_FUNC_XIO,
PMUX_FUNC_COUNT,
PMUX_FUNC_RSVD1 = 0x8000,
PMUX_FUNC_RSVD2 = 0x8001,
PMUX_FUNC_RSVD3 = 0x8002,

4
board/avionic-design/common/tamonten.c
View File

@ -37,8 +37,8 @@ void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_GME_8_BIT);
/* for write-protect GPIO PI6 */
pinmux_tristate_disable(PINGRP_ATA);
pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* for CD GPIO PH2 */
pinmux_tristate_disable(PINGRP_ATD);
pinmux_tristate_disable(PMUX_PINGRP_ATD);
}
#endif

22
board/compal/paz00/paz00.c
View File

@ -28,23 +28,23 @@
void pin_mux_mmc(void)
{
/* SDMMC4: config 3, x8 on 2nd set of pins */
pinmux_set_func(PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_set_func(PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
pinmux_tristate_disable(PINGRP_ATB);
pinmux_tristate_disable(PINGRP_GMA);
pinmux_tristate_disable(PINGRP_GME);
pinmux_tristate_disable(PMUX_PINGRP_ATB);
pinmux_tristate_disable(PMUX_PINGRP_GMA);
pinmux_tristate_disable(PMUX_PINGRP_GME);
/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
pinmux_set_func(PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
pinmux_tristate_disable(PINGRP_SDIO1);
pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
/* For power GPIO PV1 */
pinmux_tristate_disable(PINGRP_UAC);
pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* For CD GPIO PV5 */
pinmux_tristate_disable(PINGRP_GPV);
pinmux_tristate_disable(PMUX_PINGRP_GPV);
}
#endif
@ -55,6 +55,6 @@ void pin_mux_display(void)
debug("init display pinmux\n");
/* EN_VDD_PANEL GPIO A4 */
pinmux_tristate_disable(PINGRP_DAP2);
pinmux_tristate_disable(PMUX_PINGRP_DAP2);
}
#endif

4
board/compulab/trimslice/trimslice.c
View File

@ -20,7 +20,7 @@ void pin_mux_usb(void)
* USB1 internal/external mux GPIO, which masquerades as a VBUS GPIO
* in the current device tree.
*/
pinmux_tristate_disable(PINGRP_UAC);
pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_spi(void)
@ -38,5 +38,5 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
/* For CD GPIO PP1 */
pinmux_tristate_disable(PINGRP_DAP3);
pinmux_tristate_disable(PMUX_PINGRP_DAP3);
}

18
board/nvidia/harmony/harmony.c
View File

@ -25,28 +25,28 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC2, FUNCMUX_SDMMC2_DTA_DTD_8BIT);
/* For power GPIO PI6 */
pinmux_tristate_disable(PINGRP_ATA);
pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PH2 */
pinmux_tristate_disable(PINGRP_ATD);
pinmux_tristate_disable(PMUX_PINGRP_ATD);
/* For power GPIO PT3 */
pinmux_tristate_disable(PINGRP_DTB);
pinmux_tristate_disable(PMUX_PINGRP_DTB);
/* For CD GPIO PI5 */
pinmux_tristate_disable(PINGRP_ATC);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PINGRP_CDEV2);
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* USB2 PHY reset GPIO */
pinmux_tristate_disable(PINGRP_UAC);
pinmux_tristate_disable(PMUX_PINGRP_UAC);
}
void pin_mux_display(void)
{
pinmux_set_func(PINGRP_SDC, PMUX_FUNC_PWM);
pinmux_tristate_disable(PINGRP_SDC);
pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM);
pinmux_tristate_disable(PMUX_PINGRP_SDC);
}

6
board/nvidia/seaboard/seaboard.c
View File

@ -37,14 +37,14 @@ void pin_mux_mmc(void)
funcmux_select(PERIPH_ID_SDMMC3, FUNCMUX_SDMMC3_SDB_4BIT);
/* For power GPIO PI6 */
pinmux_tristate_disable(PINGRP_ATA);
pinmux_tristate_disable(PMUX_PINGRP_ATA);
/* For CD GPIO PI5 */
pinmux_tristate_disable(PINGRP_ATC);
pinmux_tristate_disable(PMUX_PINGRP_ATC);
}
#endif
void pin_mux_usb(void)
{
/* For USB's GPIO PD0. For now, since we have no pinmux in fdt */
pinmux_tristate_disable(PINGRP_SLXK);
pinmux_tristate_disable(PMUX_PINGRP_SLXK);
}

8
board/toradex/colibri_t20-common/colibri_t20-common.c
View File

@ -18,12 +18,12 @@ void colibri_t20_common_pin_mux_usb(void)
/* module internal USB bus to connect ethernet chipset */
funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI);
/* ULPI reference clock output */
pinmux_set_func(PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PINGRP_CDEV2);
pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4);
pinmux_tristate_disable(PMUX_PINGRP_CDEV2);
/* PHY reset GPIO */
pinmux_tristate_disable(PINGRP_UAC);
pinmux_tristate_disable(PMUX_PINGRP_UAC);
/* VBus GPIO */
pinmux_tristate_disable(PINGRP_DTE);
pinmux_tristate_disable(PMUX_PINGRP_DTE);
}
#endif

4
board/toradex/colibri_t20_iris/colibri_t20_iris.c
View File

@ -19,7 +19,7 @@ void pin_mux_usb(void)
colibri_t20_common_pin_mux_usb();
/* USB 1 aka Tegra USB port 3 VBus*/
pinmux_tristate_disable(PINGRP_SPIG);
pinmux_tristate_disable(PMUX_PINGRP_SPIG);
}
#endif
@ -31,6 +31,6 @@ void pin_mux_usb(void)
void pin_mux_mmc(void)
{
funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT);
pinmux_tristate_disable(PINGRP_GMB);
pinmux_tristate_disable(PMUX_PINGRP_GMB);
}
#endif

6
drivers/spi/tegra20_sflash.c
View File

@ -208,9 +208,9 @@ int tegra20_spi_claim_bus(struct spi_slave *slave)
* SPI pins on Tegra20 are muxed - change pinmux later due to UART
* issue.
*/
pinmux_set_func(PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_tristate_disable(PINGRP_LSPI);
pinmux_set_func(PINGRP_GMC, PMUX_FUNC_SFLASH);
pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
pinmux_tristate_disable(PMUX_PINGRP_LSPI);
pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
return 0;
}

4
drivers/video/tegra.c
View File

@ -229,8 +229,8 @@ static int handle_stage(const void *blob)
break;
case STAGE_PWM:
/* Enable PWM at 15/16 high, 32768 Hz with divider 1 */
pinmux_set_func(PINGRP_GPU, PMUX_FUNC_PWM);
pinmux_tristate_disable(PINGRP_GPU);
pinmux_set_func(PMUX_PINGRP_GPU, PMUX_FUNC_PWM);
pinmux_tristate_disable(PMUX_PINGRP_GPU);
pwm_enable(config.pwm_channel, 32768, 0xdf, 1);
break;