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arm64: fsl-layerscape: add get_svr and IS_SVR_REV helper

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Adds get_svr and IS_SVR_REV helpers for ARMv8 platforms,
similar to PPC and ARMv7.

Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
This commit is contained in:
Sriram Dash 2016-06-13 09:58:32 +05:30 committed by Marek Vasut
parent 1653cd18ee
commit 6fb522dc77
4 changed files with 14 additions and 0 deletions
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7
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
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@ -528,6 +528,13 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
return -1; /* cannot identify the cluster */ return -1; /* cannot identify the cluster */
} }
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
#ifdef CONFIG_DISPLAY_CPUINFO #ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void) int print_cpuinfo(void)
{ {

2
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
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@ -596,4 +596,6 @@ struct ccsr_cci400 {
#define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400 #define SCR0_USFCFG_MASK 0x00000400
uint get_svr(void);
#endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/ #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/

3
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
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@ -319,4 +319,7 @@ struct ccsr_reset {
u32 ip_rev1; /* 0xbf8 */ u32 ip_rev1; /* 0xbf8 */
u32 ip_rev2; /* 0xbfc */ u32 ip_rev2; /* 0xbfc */
}; };
uint get_svr(void);
#endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */ #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */

2
arch/arm/include/asm/arch-fsl-layerscape/soc.h
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@ -53,6 +53,8 @@ struct cpu_type {
#define SVR_MIN(svr) (((svr) >> 0) & 0xf) #define SVR_MIN(svr) (((svr) >> 0) & 0xf)
#define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E) #define SVR_SOC_VER(svr) (((svr) >> 8) & SVR_WO_E)
#define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1)) #define IS_E_PROCESSOR(svr) (!((svr >> 8) & 0x1))
#define IS_SVR_REV(svr, maj, min) \
((SVR_MAJ(svr) == (maj)) && (SVR_MIN(svr) == (min)))
/* ahci port register default value */ /* ahci port register default value */
#define AHCI_PORT_PHY_1_CFG 0xa003fffe #define AHCI_PORT_PHY_1_CFG 0xa003fffe