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mmc: tmio: Do not set divider to 1 in DDR mode

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The TMIO core has a quirk where divider == 1 must not be set in DDR modes.
Handle this by setting divider to 2, as suggested in the documentation.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Marek Vasut
2018-06-13 08:02:55 +02:00
committed by Marek Vasut
parent 8ec6a04b6b
commit 6f8f20f85d
1 changed files with 4 additions and 0 deletions
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4
drivers/mmc/tmio-common.c
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@@ -574,6 +574,10 @@ static void tmio_sd_set_clk_rate(struct tmio_sd_priv *priv,
divisor = DIV_ROUND_UP(mclk, mmc->clock); divisor = DIV_ROUND_UP(mclk, mmc->clock);
/* Do not set divider to 0xff in DDR mode */
if (mmc->ddr_mode && (divisor == 1))
divisor = 2;
if (divisor <= 1) if (divisor <= 1)
val = (priv->caps & TMIO_SD_CAP_RCAR) ? val = (priv->caps & TMIO_SD_CAP_RCAR) ?
TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1; TMIO_SD_CLKCTL_RCAR_DIV1 : TMIO_SD_CLKCTL_DIV1;