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Merge git://git.denx.de/u-boot-usb

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This commit is contained in:
Tom Rini 2015-07-24 16:39:56 -04:00
commit 6f4e050639
53 changed files with 667 additions and 375 deletions
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9
README
View File

@ -1671,7 +1671,7 @@ The following options need to be configured:
key for the Replay Protection Memory Block partition in eMMC.
- USB Device Firmware Update (DFU) class support:
CONFIG_DFU_FUNCTION
CONFIG_USB_FUNCTION_DFU
This enables the USB portion of the DFU USB class
CONFIG_CMD_DFU
@ -1716,6 +1716,9 @@ The following options need to be configured:
sending again an USB request to the device.
- USB Device Android Fastboot support:
CONFIG_USB_FUNCTION_FASTBOOT
This enables the USB part of the fastboot gadget
CONFIG_CMD_FASTBOOT
This enables the command "fastboot" which enables the Android
fastboot mode for the platform's USB device. Fastboot is a USB
@ -1727,12 +1730,12 @@ The following options need to be configured:
This enables support for booting images which use the Android
image format header.
CONFIG_USB_FASTBOOT_BUF_ADDR
CONFIG_FASTBOOT_BUF_ADDR
The fastboot protocol requires a large memory buffer for
downloads. Define this to the starting RAM address to use for
downloaded images.
CONFIG_USB_FASTBOOT_BUF_SIZE
CONFIG_FASTBOOT_BUF_SIZE
The fastboot protocol requires a large memory buffer for
downloads. This buffer should be as large as possible for a
platform. Define this to the size available RAM for fastboot.

2
arch/arm/cpu/armv7/omap-common/boot-common.c
View File

@ -163,7 +163,7 @@ void arch_preboot_os(void)
}
#endif
#if defined(CONFIG_CMD_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE)
#if defined(CONFIG_USB_FUNCTION_FASTBOOT) && !defined(CONFIG_ENV_IS_NOWHERE)
int fb_set_reboot_flag(void)
{
printf("Setting reboot to fastboot flag ...\n");

7
arch/arm/include/asm/arch-bcm281xx/sysmap.h
View File

@ -27,4 +27,11 @@
#define SECWD2_BASE_ADDR 0x35002f40
#define TIMER_BASE_ADDR 0x3e00d000
#define HSOTG_DCTL_OFFSET 0x00000804
#define HSOTG_DCTL_SFTDISCON_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_OFFSET 0x00000008
#define HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK 0x00000002
#define HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK 0x00000001
#endif

1
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -35,6 +35,7 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_DCU_ADDR (CONFIG_SYS_IMMR + 0x01ce0000)
#define CONFIG_SYS_LS102XA_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_LS102XA_USB1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_LS102XA_USB1_OFFSET)

1
arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
View File

@ -396,4 +396,5 @@ struct ccsr_cci400 {
} pcounter[4]; /* Performance Counter */
u8 res_e004[0x10000 - 0xe004];
};
#endif /* __ASM_ARCH_LS102XA_IMMAP_H_ */

40
board/broadcom/bcm28155_ap/bcm28155_ap.c
View File

@ -12,12 +12,20 @@
#include <asm/kona-common/clk.h>
#include <asm/arch/sysmap.h>
#include <usb.h>
#include <usb/s3c_udc.h>
#include <g_dnl.h>
#define SECWATCHDOG_SDOGCR_OFFSET 0x00000000
#define SECWATCHDOG_SDOGCR_EN_SHIFT 27
#define SECWATCHDOG_SDOGCR_SRSTEN_SHIFT 26
#define SECWATCHDOG_SDOGCR_CLKS_SHIFT 20
#define SECWATCHDOG_SDOGCR_LD_SHIFT 0
#ifndef CONFIG_USB_SERIALNO
#define CONFIG_USB_SERIALNO "1234567890"
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
@ -85,3 +93,35 @@ int board_mmc_init(bd_t *bis)
return ret;
}
#endif
#ifdef CONFIG_USB_GADGET
static struct s3c_plat_otg_data bcm_otg_data = {
.regs_otg = HSOTG_BASE_ADDR
};
int board_usb_init(int index, enum usb_init_type init)
{
debug("%s: performing s3c_udc_probe\n", __func__);
return s3c_udc_probe(&bcm_otg_data);
}
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{
debug("%s\n", __func__);
if (!getenv("serial#"))
g_dnl_set_serialnumber(CONFIG_USB_SERIALNO);
return 0;
}
int g_dnl_get_board_bcd_device_number(int gcnum)
{
debug("%s\n", __func__);
return 1;
}
int board_usb_cleanup(int index, enum usb_init_type init)
{
debug("%s\n", __func__);
return 0;
}
#endif

2
board/samsung/common/Makefile
View File

@ -6,7 +6,7 @@
#
obj-$(CONFIG_SOFT_I2C_MULTI_BUS) += multi_i2c.o
obj-$(CONFIG_USBDOWNLOAD_GADGET) += gadget.o
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += gadget.o
obj-$(CONFIG_MISC_COMMON) += misc.o
ifndef CONFIG_SPL_BUILD

4
board/siemens/common/factoryset.c
View File

@ -144,7 +144,7 @@ int factoryset_read_eeprom(int i2c_addr)
unsigned char eeprom_buf[0x3c00], hdr[4], buf[MAX_STRING_LENGTH];
unsigned char *cp, *cp1;
#if defined(CONFIG_DFU_FUNCTION)
#if defined(CONFIG_USB_FUNCTION_DFU)
factory_dat.usb_vendor_id = CONFIG_G_DNL_VENDOR_NUM;
factory_dat.usb_product_id = CONFIG_G_DNL_PRODUCT_NUM;
#endif
@ -202,7 +202,7 @@ int factoryset_read_eeprom(int i2c_addr)
cp1 += 3;
}
#if defined(CONFIG_DFU_FUNCTION)
#if defined(CONFIG_USB_FUNCTION_DFU)
/* read vid and pid for dfu mode */
if (0 <= get_factory_record_val(cp, size, (uchar *)"USBD1",
(uchar *)"vid", buf,

33
common/cmd_fastboot.c
View File

@ -10,11 +10,26 @@
#include <common.h>
#include <command.h>
#include <g_dnl.h>
#include <usb.h>
static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
int controller_index;
char *usb_controller;
int ret;
if (argc < 2)
return CMD_RET_USAGE;
usb_controller = argv[1];
controller_index = simple_strtoul(usb_controller, NULL, 0);
ret = board_usb_init(controller_index, USB_INIT_DEVICE);
if (ret) {
error("USB init failed: %d", ret);
return CMD_RET_FAILURE;
}
g_dnl_clear_detach();
ret = g_dnl_register("usb_dnl_fastboot");
if (ret)
@ -23,9 +38,8 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
if (!g_dnl_board_usb_cable_connected()) {
puts("\rUSB cable not detected.\n" \
"Command exit.\n");
g_dnl_unregister();
g_dnl_clear_detach();
return CMD_RET_FAILURE;
ret = CMD_RET_FAILURE;
goto exit;
}
while (1) {
@ -33,17 +47,22 @@ static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
break;
if (ctrlc())
break;
usb_gadget_handle_interrupts(0);
usb_gadget_handle_interrupts(controller_index);
}
ret = CMD_RET_SUCCESS;
exit:
g_dnl_unregister();
g_dnl_clear_detach();
return CMD_RET_SUCCESS;
board_usb_cleanup(controller_index, USB_INIT_DEVICE);
return ret;
}
U_BOOT_CMD(
fastboot, 1, 0, do_fastboot,
fastboot, 2, 1, do_fastboot,
"use USB Fastboot protocol",
"\n"
"<USB_controller>\n"
" - run as a fastboot usb device"
);

10
doc/README.android-fastboot
View File

@ -33,7 +33,7 @@ Board specific
The fastboot gadget relies on the USB download gadget, so the following
options must be configured:
CONFIG_USBDOWNLOAD_GADGET
CONFIG_USB_GADGET_DOWNLOAD
CONFIG_G_DNL_VENDOR_NUM
CONFIG_G_DNL_PRODUCT_NUM
CONFIG_G_DNL_MANUFACTURER
@ -42,13 +42,13 @@ NOTE: The CONFIG_G_DNL_VENDOR_NUM must be one of the numbers supported by
the fastboot client. The list of vendor IDs supported can be found in the
fastboot client source code (fastboot.c) mentioned above.
The fastboot function is enabled by defining CONFIG_CMD_FASTBOOT and
CONFIG_ANDROID_BOOT_IMAGE.
The fastboot function is enabled by defining CONFIG_USB_FUNCTION_FASTBOOT,
CONFIG_CMD_FASTBOOT and CONFIG_ANDROID_BOOT_IMAGE.
The fastboot protocol requires a large memory buffer for downloads. This
buffer should be as large as possible for a platform. The location of the
buffer and size are set with CONFIG_USB_FASTBOOT_BUF_ADDR and
CONFIG_USB_FASTBOOT_BUF_SIZE.
buffer and size are set with CONFIG_FASTBOOT_BUF_ADDR and
CONFIG_FASTBOOT_BUF_SIZE.
Fastboot partition aliases can also be defined for devices where GPT
limitations prevent user-friendly partition names such as "boot", "system"

2
drivers/dfu/Makefile
View File

@ -5,7 +5,7 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_DFU_FUNCTION) += dfu.o
obj-$(CONFIG_USB_FUNCTION_DFU) += dfu.o
obj-$(CONFIG_DFU_MMC) += dfu_mmc.o
obj-$(CONFIG_DFU_NAND) += dfu_nand.o
obj-$(CONFIG_DFU_RAM) += dfu_ram.o

11
drivers/usb/gadget/Makefile
View File

@ -11,15 +11,16 @@ obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
# new USB gadget layer dependencies
ifdef CONFIG_USB_GADGET
obj-$(CONFIG_USB_GADGET_ATMEL_USBA) += atmel_usba_udc.o
obj-$(CONFIG_USB_GADGET_BCM_UDC_OTG_PHY) += bcm_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG) += s3c_udc_otg.o
obj-$(CONFIG_USB_GADGET_S3C_UDC_OTG_PHY) += s3c_udc_otg_phy.o
obj-$(CONFIG_USB_GADGET_FOTG210) += fotg210.o
obj-$(CONFIG_CI_UDC) += ci_udc.o
obj-$(CONFIG_THOR_FUNCTION) += f_thor.o
obj-$(CONFIG_USBDOWNLOAD_GADGET) += g_dnl.o
obj-$(CONFIG_DFU_FUNCTION) += f_dfu.o
obj-$(CONFIG_USB_GADGET_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_CMD_FASTBOOT) += f_fastboot.o
obj-$(CONFIG_USB_GADGET_DOWNLOAD) += g_dnl.o
obj-$(CONFIG_USB_FUNCTION_THOR) += f_thor.o
obj-$(CONFIG_USB_FUNCTION_DFU) += f_dfu.o
obj-$(CONFIG_USB_FUNCTION_MASS_STORAGE) += f_mass_storage.o
obj-$(CONFIG_USB_FUNCTION_FASTBOOT) += f_fastboot.o
endif
ifdef CONFIG_USB_ETHER
obj-y += ether.o

22
drivers/usb/gadget/bcm_udc_otg.h Normal file
View File

@ -0,0 +1,22 @@
/*
* Copyright 2015 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __BCM_UDC_OTG_H
#define __BCM_UDC_OTG_H
#include <common.h>
static inline void wfld_set(uintptr_t addr, uint32_t fld_val, uint32_t fld_mask)
{
writel(((readl(addr) & ~(fld_mask)) | (fld_val)), (addr));
}
static inline void wfld_clear(uintptr_t addr, uint32_t fld_mask)
{
writel((readl(addr) & ~(fld_mask)), (addr));
}
#endif

51
drivers/usb/gadget/bcm_udc_otg_phy.c Normal file
View File

@ -0,0 +1,51 @@
/*
* Copyright 2015 Broadcom Corporation.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <config.h>
#include <common.h>
#include <asm/io.h>
#include <asm/arch/sysmap.h>
#include <usb/s3c_udc.h>
#include "bcm_udc_otg.h"
void otg_phy_init(struct s3c_udc *dev)
{
/* set Phy to driving mode */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
udelay(100);
/* clear Soft Disconnect */
wfld_clear(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
HSOTG_DCTL_SFTDISCON_MASK);
/* invoke Reset (active low) */
wfld_clear(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
/* Reset needs to be asserted for 2ms */
udelay(2000);
/* release Reset */
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK,
HSOTG_CTRL_PHY_P1CTL_SOFT_RESET_MASK);
}
void otg_phy_off(struct s3c_udc *dev)
{
/* Soft Disconnect */
wfld_set(HSOTG_BASE_ADDR + HSOTG_DCTL_OFFSET,
HSOTG_DCTL_SFTDISCON_MASK,
HSOTG_DCTL_SFTDISCON_MASK);
/* set Phy to non-driving (reset) mode */
wfld_set(HSOTG_CTRL_BASE_ADDR + HSOTG_CTRL_PHY_P1CTL_OFFSET,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK,
HSOTG_CTRL_PHY_P1CTL_NON_DRIVING_MASK);
}

31
drivers/usb/gadget/ci_udc.c
View File

@ -221,8 +221,8 @@ static void ci_flush_qtd(int ep_num)
*/
static void ci_flush_td(struct ept_queue_item *td)
{
const uint32_t start = (uint32_t)td;
const uint32_t end = (uint32_t) td + ILIST_ENT_SZ;
const unsigned long start = (unsigned long)td;
const unsigned long end = (unsigned long)td + ILIST_ENT_SZ;
flush_dcache_range(start, end);
}
@ -249,8 +249,8 @@ static void ci_invalidate_qtd(int ep_num)
*/
static void ci_invalidate_td(struct ept_queue_item *td)
{
const uint32_t start = (uint32_t)td;
const uint32_t end = start + ILIST_ENT_SZ;
const unsigned long start = (unsigned long)td;
const unsigned long end = start + ILIST_ENT_SZ;
invalidate_dcache_range(start, end);
}
@ -258,10 +258,12 @@ static struct usb_request *
ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
int num;
int num = -1;
struct ci_req *ci_req;
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
if (ci_ep->desc)
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
if (num == 0 && controller.ep0_req)
return &controller.ep0_req->req;
@ -281,9 +283,11 @@ static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
{
struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
struct ci_req *ci_req = container_of(req, struct ci_req, req);
int num;
int num = -1;
if (ci_ep->desc)
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
if (num == 0) {
if (!controller.ep0_req)
return;
@ -459,7 +463,7 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
if (len) {
qtd = (struct ept_queue_item *)
memalign(ILIST_ALIGN, ILIST_ENT_SZ);
dtd->next = (uint32_t)qtd;
dtd->next = (unsigned long)qtd;
dtd = qtd;
memset(dtd, 0, ILIST_ENT_SZ);
}
@ -503,10 +507,10 @@ static void ci_ep_submit_next_request(struct ci_ep *ci_ep)
ci_flush_qtd(num);
item = (struct ept_queue_item *)head->next;
item = (struct ept_queue_item *)(unsigned long)head->next;
while (item->next != TERMINATE) {
ci_flush_td((struct ept_queue_item *)item->next);
item = (struct ept_queue_item *)item->next;
ci_flush_td((struct ept_queue_item *)(unsigned long)item->next);
item = (struct ept_queue_item *)(unsigned long)item->next;
}
DBG("ept%d %s queue len %x, req %p, buffer %p\n",
@ -594,7 +598,8 @@ static void handle_ep_complete(struct ci_ep *ci_ep)
printf("EP%d/%s FAIL info=%x pg0=%x\n",
num, in ? "in" : "out", item->info, item->page0);
if (j != ci_req->dtd_count - 1)
next_td = (struct ept_queue_item *)item->next;
next_td = (struct ept_queue_item *)(unsigned long)
item->next;
if (j != 0)
free(item);
}

22
drivers/usb/gadget/f_fastboot.c
View File

@ -311,6 +311,9 @@ static int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
memcpy(in_req->buf, buffer, buffer_size);
in_req->length = buffer_size;
usb_ep_dequeue(fastboot_func->in_ep, in_req);
ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0);
if (ret)
printf("Error %d on queue\n", ret);
@ -377,7 +380,7 @@ static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
!strcmp_l1("max-download-size", cmd)) {
char str_num[12];
sprintf(str_num, "0x%08x", CONFIG_USB_FASTBOOT_BUF_SIZE);
sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
strncat(response, str_num, chars_left);
} else if (!strcmp_l1("serialno", cmd)) {
s = getenv("serial#");
@ -427,7 +430,7 @@ static void rx_handler_dl_image(struct usb_ep *ep, struct usb_request *req)
if (buffer_size < transfer_size)
transfer_size = buffer_size;
memcpy((void *)CONFIG_USB_FASTBOOT_BUF_ADDR + download_bytes,
memcpy((void *)CONFIG_FASTBOOT_BUF_ADDR + download_bytes,
buffer, transfer_size);
pre_dot_num = download_bytes / BYTES_PER_DOT;
@ -480,7 +483,7 @@ static void cb_download(struct usb_ep *ep, struct usb_request *req)
if (0 == download_size) {
sprintf(response, "FAILdata invalid size");
} else if (download_size > CONFIG_USB_FASTBOOT_BUF_SIZE) {
} else if (download_size > CONFIG_FASTBOOT_BUF_SIZE) {
download_size = 0;
sprintf(response, "FAILdata too large");
} else {
@ -541,7 +544,7 @@ static void cb_flash(struct usb_ep *ep, struct usb_request *req)
strcpy(response, "FAILno flash device defined");
#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
fb_mmc_flash_write(cmd, (void *)CONFIG_USB_FASTBOOT_BUF_ADDR,
fb_mmc_flash_write(cmd, (void *)CONFIG_FASTBOOT_BUF_ADDR,
download_bytes, response);
#endif
fastboot_tx_write_str(response);
@ -635,6 +638,9 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
int i;
if (req->status != 0 || req->length == 0)
return;
for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) {
func_cb = cmd_dispatch_info[i].cb;
@ -656,9 +662,7 @@ static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
}
}
if (req->status == 0) {
*cmdbuf = '\0';
req->actual = 0;
usb_ep_queue(ep, req, 0);
}
*cmdbuf = '\0';
req->actual = 0;
usb_ep_queue(ep, req, 0);
}

13
drivers/usb/gadget/g_dnl.c
View File

@ -12,6 +12,7 @@
#include <mmc.h>
#include <part.h>
#include <usb.h>
#include <g_dnl.h>
#include <usb_mass_storage.h>
@ -147,6 +148,18 @@ static int g_dnl_config_register(struct usb_composite_dev *cdev)
return usb_add_config(cdev, config);
}
__weak
int board_usb_init(int index, enum usb_init_type init)
{
return 0;
}
__weak
int board_usb_cleanup(int index, enum usb_init_type init)
{
return 0;
}
__weak
int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name)
{

2
drivers/usb/host/Makefile
View File

@ -51,8 +51,10 @@ obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o
# xhci
obj-$(CONFIG_USB_XHCI) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
obj-$(CONFIG_USB_XHCI_KEYSTONE) += xhci-keystone.o
obj-$(CONFIG_USB_XHCI_EXYNOS) += xhci-exynos5.o
obj-$(CONFIG_USB_XHCI_FSL) += xhci-fsl.o
obj-$(CONFIG_USB_XHCI_OMAP) += xhci-omap.o
obj-$(CONFIG_USB_XHCI_PCI) += xhci-pci.o
obj-$(CONFIG_USB_XHCI_UNIPHIER) += xhci-uniphier.o

26
drivers/usb/host/ehci-marvell.c
View File

@ -21,9 +21,6 @@
DECLARE_GLOBAL_DATA_PTR;
#define rdl(off) readl(MVUSB0_BASE + (off))
#define wrl(off, val) writel((val), MVUSB0_BASE + (off))
#define USB_WINDOW_CTRL(i) (0x320 + ((i) << 4))
#define USB_WINDOW_BASE(i) (0x324 + ((i) << 4))
#define USB_TARGET_DRAM 0x0
@ -48,20 +45,20 @@ static void usb_brg_adrdec_setup(void)
dram = mvebu_mbus_dram_info();
for (i = 0; i < 4; i++) {
wrl(USB_WINDOW_CTRL(i), 0);
wrl(USB_WINDOW_BASE(i), 0);
writel(0, MVUSB0_BASE + USB_WINDOW_CTRL(i));
writel(0, MVUSB0_BASE + USB_WINDOW_BASE(i));
}
for (i = 0; i < dram->num_cs; i++) {
const struct mbus_dram_window *cs = dram->cs + i;
/* Write size, attributes and target id to control register */
wrl(USB_WINDOW_CTRL(i),
((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1);
writel(((cs->size - 1) & 0xffff0000) | (cs->mbus_attr << 8) |
(dram->mbus_dram_target_id << 4) | 1,
MVUSB0_BASE + USB_WINDOW_CTRL(i));
/* Write base address to base register */
wrl(USB_WINDOW_BASE(i), cs->base);
writel(cs->base, MVUSB0_BASE + USB_WINDOW_BASE(i));
}
}
#else
@ -95,13 +92,14 @@ static void usb_brg_adrdec_setup(void)
size = gd->bd->bi_dram[i].size;
base = gd->bd->bi_dram[i].start;
if ((size) && (attrib))
wrl(USB_WINDOW_CTRL(i),
MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE));
writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
attrib, MVCPU_WIN_ENABLE),
MVUSB0_BASE + USB_WINDOW_CTRL(i));
else
wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
writel(MVCPU_WIN_DISABLE,
MVUSB0_BASE + USB_WINDOW_CTRL(i));
wrl(USB_WINDOW_BASE(i), base);
writel(base, MVUSB0_BASE + USB_WINDOW_BASE(i));
}
}
#endif

97
drivers/usb/host/xhci-dwc3.c Normal file
View File

@ -0,0 +1,97 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* DWC3 controller driver
*
* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <linux/usb/dwc3.h>
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
DWC3_GCTL_PRTCAPDIR(mode));
}
void dwc3_phy_reset(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(100);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
/* reset USB3 phy - if required */
dwc3_phy_reset(dwc3_reg);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}
int dwc3_core_init(struct dwc3 *dwc3_reg)
{
u32 reg;
u32 revision;
unsigned int dwc3_hwparams1;
revision = readl(&dwc3_reg->g_snpsid);
/* This should read as U3 followed by revision number */
if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
puts("this is not a DesignWare USB3 DRD Core\n");
return -1;
}
dwc3_core_soft_reset(dwc3_reg);
dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
reg = readl(&dwc3_reg->g_ctl);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
reg &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
default:
debug("No power optimization available\n");
}
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
* and falls back to high-speed mode which causes
* the device to enter a Connect/Disconnect loop
*/
if ((revision & DWC3_REVISION_MASK) < 0x190a)
reg |= DWC3_GCTL_U2RSTECN;
writel(reg, &dwc3_reg->g_ctl);
return 0;
}
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val)
{
setbits_le32(&dwc3_reg->g_fladj, GFLADJ_30MHZ_REG_SEL |
GFLADJ_30MHZ(val));
}

78
drivers/usb/host/xhci-exynos5.c
View File

@ -179,84 +179,6 @@ static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
}
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
DWC3_GCTL_PRTCAPDIR(mode));
}
static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_CORESOFTRESET);
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0],
DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(100);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg,
DWC3_GUSB2PHYCFG_PHYSOFTRST);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_CORESOFTRESET);
}
static int dwc3_core_init(struct dwc3 *dwc3_reg)
{
u32 reg;
u32 revision;
unsigned int dwc3_hwparams1;
revision = readl(&dwc3_reg->g_snpsid);
/* This should read as U3 followed by revision number */
if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
puts("this is not a DesignWare USB3 DRD Core\n");
return -EINVAL;
}
dwc3_core_soft_reset(dwc3_reg);
dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
reg = readl(&dwc3_reg->g_ctl);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
reg &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
default:
debug("No power optimization available\n");
}
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
* and falls back to high-speed mode which causes
* the device to enter a Connect/Disconnect loop
*/
if ((revision & DWC3_REVISION_MASK) < 0x190a)
reg |= DWC3_GCTL_U2RSTECN;
writel(reg, &dwc3_reg->g_ctl);
return 0;
}
static int exynos_xhci_core_init(struct exynos_xhci *exynos)
{
int ret;

111
drivers/usb/host/xhci-fsl.c Normal file
View File

@ -0,0 +1,111 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* FSL USB HOST xHCI Controller
*
* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <usb.h>
#include <asm-generic/errno.h>
#include <linux/compat.h>
#include <linux/usb/xhci-fsl.h>
#include <linux/usb/dwc3.h>
#include "xhci.h"
/* Declare global data pointer */
DECLARE_GLOBAL_DATA_PTR;
static struct fsl_xhci fsl_xhci;
unsigned long ctr_addr[] = FSL_USB_XHCI_ADDR;
__weak int __board_usb_init(int index, enum usb_init_type init)
{
return 0;
}
void usb_phy_reset(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(200);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}
static int fsl_xhci_core_init(struct fsl_xhci *fsl_xhci)
{
int ret = 0;
ret = dwc3_core_init(fsl_xhci->dwc3_reg);
if (ret) {
debug("%s:failed to initialize core\n", __func__);
return ret;
}
/* We are hard-coding DWC3 core to Host Mode */
dwc3_set_mode(fsl_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
/* Set GFLADJ_30MHZ as 20h as per XHCI spec default value */
dwc3_set_fladj(fsl_xhci->dwc3_reg, GFLADJ_30MHZ_DEFAULT);
return ret;
}
static int fsl_xhci_core_exit(struct fsl_xhci *fsl_xhci)
{
/*
* Currently fsl socs do not support PHY shutdown from
* sw. But this support may be added in future socs.
*/
return 0;
}
int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
{
struct fsl_xhci *ctx = &fsl_xhci;
int ret = 0;
ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
ret = board_usb_init(index, USB_INIT_HOST);
if (ret != 0) {
puts("Failed to initialize board for USB\n");
return ret;
}
ret = fsl_xhci_core_init(ctx);
if (ret < 0) {
puts("Failed to initialize xhci\n");
return ret;
}
*hccr = (struct xhci_hccr *)ctx->hcd;
*hcor = (struct xhci_hcor *)((uintptr_t) *hccr
+ HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
debug("fsl-xhci: init hccr %lx and hcor %lx hc_length %lx\n",
(uintptr_t)*hccr, (uintptr_t)*hcor,
(uintptr_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
return ret;
}
void xhci_hcd_stop(int index)
{
struct fsl_xhci *ctx = &fsl_xhci;
fsl_xhci_core_exit(ctx);
}

88
drivers/usb/host/xhci-keystone.c
View File

@ -68,94 +68,6 @@ static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
writel(val, &phy->phy_clock);
}
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
DWC3_GCTL_PRTCAPDIR(mode));
}
static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(100);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg[0], DWC3_GUSB2PHYCFG_PHYSOFTRST);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}
static int dwc3_core_init(struct dwc3 *dwc3_reg)
{
u32 revision, val;
unsigned long t_rst;
unsigned int dwc3_hwparams1;
revision = readl(&dwc3_reg->g_snpsid);
/* This should read as U3 followed by revision number */
if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
puts("this is not a DesignWare USB3 DRD Core\n");
return -EINVAL;
}
/* issue device SoftReset too */
writel(DWC3_DCTL_CSFTRST, &dwc3_reg->d_ctl);
t_rst = get_timer(0);
do {
val = readl(&dwc3_reg->d_ctl);
if (!(val & DWC3_DCTL_CSFTRST))
break;
WATCHDOG_RESET();
} while (get_timer(t_rst) < 500);
if (val & DWC3_DCTL_CSFTRST) {
debug("Reset timed out\n");
return -2;
}
dwc3_core_soft_reset(dwc3_reg);
dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
val = readl(&dwc3_reg->g_ctl);
val &= ~DWC3_GCTL_SCALEDOWN_MASK;
val &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
val &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
default:
printf("No power optimization available\n");
}
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
* and falls back to high-speed mode which causes
* the device to enter a Connect/Disconnect loop
*/
if ((revision & DWC3_REVISION_MASK) < 0x190a)
val |= DWC3_GCTL_U2RSTECN;
writel(val, &dwc3_reg->g_ctl);
return 0;
}
static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
{
int ret;

60
drivers/usb/host/xhci-omap.c
View File

@ -34,66 +34,6 @@ inline int __board_usb_init(int index, enum usb_init_type init)
int board_usb_init(int index, enum usb_init_type init)
__attribute__((weak, alias("__board_usb_init")));
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
{
clrsetbits_le32(&dwc3_reg->g_ctl,
DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
DWC3_GCTL_PRTCAPDIR(mode));
}
static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
{
/* Before Resetting PHY, put Core in Reset */
setbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
omap_reset_usb_phy(dwc3_reg);
/* After PHYs are stable we can take Core out of reset state */
clrbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_CORESOFTRESET);
}
static int dwc3_core_init(struct dwc3 *dwc3_reg)
{
u32 reg;
u32 revision;
unsigned int dwc3_hwparams1;
revision = readl(&dwc3_reg->g_snpsid);
/* This should read as U3 followed by revision number */
if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
puts("this is not a DesignWare USB3 DRD Core\n");
return -1;
}
dwc3_core_soft_reset(dwc3_reg);
dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
reg = readl(&dwc3_reg->g_ctl);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
reg &= ~DWC3_GCTL_DISSCRAMBLE;
switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
reg &= ~DWC3_GCTL_DSBLCLKGTNG;
break;
default:
debug("No power optimization available\n");
}
/*
* WORKAROUND: DWC3 revisions <1.90a have a bug
* where the device can fail to connect at SuperSpeed
* and falls back to high-speed mode which causes
* the device to enter a Connect/Disconnect loop
*/
if ((revision & DWC3_REVISION_MASK) < 0x190a)
reg |= DWC3_GCTL_U2RSTECN;
writel(reg, &dwc3_reg->g_ctl);
return 0;
}
static int omap_xhci_core_init(struct omap_xhci *omap)
{
int ret = 0;

18
drivers/usb/phy/omap_usb_phy.c
View File

@ -223,24 +223,6 @@ void usb_phy_power(int on)
}
#endif /* CONFIG_AM437X_USB2PHY2_HOST */
void omap_reset_usb_phy(struct dwc3 *dwc3_reg)
{
/* Assert USB3 PHY reset */
setbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Assert USB2 PHY reset */
setbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
mdelay(100);
/* Clear USB3 PHY reset */
clrbits_le32(&dwc3_reg->g_usb3pipectl[0], DWC3_GUSB3PIPECTL_PHYSOFTRST);
/* Clear USB2 PHY reset */
clrbits_le32(&dwc3_reg->g_usb2phycfg, DWC3_GUSB2PHYCFG_PHYSOFTRST);
}
void omap_enable_phy(struct omap_xhci *omap)
{
#ifdef CONFIG_OMAP_USB2PHY2_HOST

9
include/configs/am335x_evm.h
View File

@ -287,7 +287,7 @@
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
@ -298,10 +298,11 @@
#ifndef CONFIG_SPL_USBETH_SUPPORT
/* Fastboot */
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* To support eMMC booting */
#define CONFIG_STORAGE_EMMC
@ -344,7 +345,7 @@
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_CMD_DFU
#define DFU_ALT_INFO_MMC \

5
include/configs/am43xx_evm.h
View File

@ -110,6 +110,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
@ -127,7 +128,7 @@
#define CONFIG_USB_DWC3_GADGET
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#define CONFIG_G_DNL_VENDOR_NUM 0x0403
@ -137,7 +138,7 @@
#ifndef CONFIG_SPL_BUILD
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
#define CONFIG_CMD_DFU

11
include/configs/bav335x.h
View File

@ -444,7 +444,7 @@ DEFAULT_LINUX_BOOT_ENV \
#define CONFIG_MUSB_PIO_ONLY
#define CONFIG_MUSB_DISABLE_BULK_COMBINE_SPLIT
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_MUSB_HOST
@ -455,10 +455,11 @@ DEFAULT_LINUX_BOOT_ENV \
#ifndef CONFIG_SPL_USBETH_SUPPORT
/* Fastboot */
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* To support eMMC booting */
#define CONFIG_STORAGE_EMMC
@ -472,7 +473,7 @@ DEFAULT_LINUX_BOOT_ENV \
#ifdef CONFIG_MUSB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* USB TI's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x0451
@ -494,7 +495,7 @@ DEFAULT_LINUX_BOOT_ENV \
/* USB Device Firmware Update support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_CMD_DFU
#define DFU_ALT_INFO_MMC \

20
include/configs/bcm28155_ap.h
View File

@ -108,6 +108,7 @@
* for example.
*/
#define CONFIG_DOS_PARTITION
#define CONFIG_EFI_PARTITION
/* version string, parser, etc */
#define CONFIG_VERSION_VARIABLE
@ -133,4 +134,23 @@
#define CONFIG_FAT_WRITE
/* Fastboot and USB OTG */
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_FASTBOOT_FLASH
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 0
#define CONFIG_SYS_CACHELINE_SIZE 64
#define CONFIG_FASTBOOT_BUF_SIZE (CONFIG_SYS_SDRAM_SIZE - SZ_1M)
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_SDRAM_BASE
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_BCM_UDC_OTG_PHY
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USBID_ADDR 0x34052c46
#define CONFIG_G_DNL_VENDOR_NUM 0x18d1 /* google */
#define CONFIG_G_DNL_PRODUCT_NUM 0x0d02 /* nexus one */
#define CONFIG_G_DNL_MANUFACTURER "Broadcom Corporation"
#endif /* __BCM28155_AP_H */

1
include/configs/beagle_x15.h
View File

@ -68,6 +68,7 @@
/* USB xHCI HOST */
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE

6
include/configs/colibri_vf.h
View File

@ -257,16 +257,16 @@
#define CONFIG_G_DNL_PRODUCT_NUM CONFIG_TRDX_PID_COLIBRI_VF50
/* USB DFU */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_CMD_DFU
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1024 * 1024)
/* USB Storage */
#define CONFIG_USB_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
/* Enable SPI support */

10
include/configs/dra7xx_evm.h
View File

@ -89,10 +89,11 @@
DFU_ALT_INFO_RAM
/* Fastboot */
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x2F000000
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x2F000000
#define CONFIG_FASTBOOT_FLASH
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#endif
@ -175,6 +176,7 @@
#define CONFIG_CMD_USB
#define CONFIG_USB_HOST
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_OMAP
#define CONFIG_USB_STORAGE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
@ -189,7 +191,7 @@
#define CONFIG_USB_DWC3_GADGET
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_MANUFACTURER "Texas Instruments"
#define CONFIG_G_DNL_VENDOR_NUM 0x0451
@ -197,7 +199,7 @@
#define CONFIG_USB_GADGET_DUALSPEED
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_RAM
#define CONFIG_CMD_DFU

8
include/configs/exynos4-common.h
View File

@ -28,13 +28,13 @@
#define CONFIG_CMD_GPT
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_THOR_FUNCTION
#define CONFIG_USB_FUNCTION_THOR
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
@ -57,7 +57,7 @@
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
/* Common environment variables */
#define CONFIG_EXTRA_ENV_ITB \

1
include/configs/exynos5-common.h
View File

@ -182,6 +182,7 @@
/* USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2

4
include/configs/gw_ventana.h
View File

@ -205,8 +205,8 @@
/* USB Mass Storage Gadget */
#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* Netchip IDs */

1
include/configs/ks2_evm.h
View File

@ -195,6 +195,7 @@
/* USB Configuration */
#define CONFIG_USB_XHCI
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_KEYSTONE
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#define CONFIG_USB_STORAGE

24
include/configs/ls1021aqds.h
View File

@ -432,18 +432,30 @@ unsigned long get_board_ddr_clk(void);
/*
* USB
*/
#define CONFIG_HAS_FSL_DR_USB
/* EHCI Support - disbaled by default */
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_CMD_EXT2
#endif
/*XHCI Support - enabled by default*/
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2
#endif
/*

38
include/configs/ls1021atwr.h
View File

@ -27,6 +27,44 @@
#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
/*
* USB
*/
/*
* EHCI Support - disbaled by default as
* there is no signal coming out of soc on
* this board for this controller. However,
* the silicon still has this controller,
* and anyone can use this controller by
* taking signals out on their board.
*/
/*#define CONFIG_HAS_FSL_DR_USB*/
#ifdef CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#endif
/* XHCI Support - enabled by default */
#define CONFIG_HAS_FSL_XHCI_USB
#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_FSL
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
#endif
#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2
#endif
/*
* Generic Timer Definitions
*/

4
include/configs/mx6sabre_common.h
View File

@ -217,8 +217,8 @@
#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_VENDOR_NUM 0x0525

9
include/configs/nitrogen6x.h
View File

@ -337,8 +337,8 @@
#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* Netchip IDs */
@ -346,9 +346,10 @@
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "Boundary"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
#endif /* __CONFIG_H */

8
include/configs/odroid_xu3.h
View File

@ -60,10 +60,10 @@
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
#define CONFIG_G_DNL_PRODUCT_NUM 0x6601
#define CONFIG_G_DNL_MANUFACTURER "Samsung"
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
/* DFU */
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_CMD_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
@ -72,13 +72,13 @@
/* THOR */
#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM
#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D
#define CONFIG_THOR_FUNCTION
#define CONFIG_USB_FUNCTION_THOR
#define CONFIG_CMD_THOR_DOWNLOAD
/* UMS */
#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
/* FIXME: MUST BE REMOVED AFTER TMU IS TURNED ON */

7
include/configs/omap3_beagle.h
View File

@ -68,14 +68,15 @@
#define CONFIG_USB_ETHER_RNDIS
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_VENDOR_NUM 0x0451
#define CONFIG_G_DNL_PRODUCT_NUM 0xd022
#define CONFIG_G_DNL_MANUFACTURER "TI"
#define CONFIG_USB_FUNCTION_FASTBOOT
#define CONFIG_CMD_FASTBOOT
#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_USB_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_USB_FASTBOOT_BUF_SIZE 0x07000000
#define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR
#define CONFIG_FASTBOOT_BUF_SIZE 0x07000000
/* USB EHCI */
#define CONFIG_CMD_USB

8
include/configs/s5p_goni.h
View File

@ -68,15 +68,15 @@
#define CONFIG_CMD_GPT
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M
#define DFU_DEFAULT_POLL_TIMEOUT 300
/* TIZEN THOR downloader support */
#define CONFIG_CMD_THOR_DOWNLOAD
#define CONFIG_THOR_FUNCTION
#define CONFIG_USB_FUNCTION_THOR
/* USB Samsung's IDs */
#define CONFIG_G_DNL_VENDOR_NUM 0x04E8
@ -275,7 +275,7 @@
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_OF_LIBFDT

4
include/configs/siemens-am33x-common.h
View File

@ -249,7 +249,7 @@
#endif /* CONFIG_MUSB_GADGET */
#define CONFIG_USB_GADGET
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
/* USB DRACO ID as default */
#define CONFIG_USBD_HS
@ -258,7 +258,7 @@
#define CONFIG_G_DNL_MANUFACTURER "Siemens AG"
/* USB Device Firmware Update support */
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_NAND
#define CONFIG_CMD_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 << 20)

6
include/configs/socfpga_common.h
View File

@ -243,10 +243,10 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* USB Composite download gadget - g_dnl */
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (32 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT 300

4
include/configs/tbs2910.h
View File

@ -133,10 +133,10 @@
#define CONFIG_CI_UDC
#define CONFIG_USBD_HS
#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_GADGET_VBUS_DRAW 0
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
#define CONFIG_G_DNL_PRODUCT_NUM 0xa4a5
#define CONFIG_G_DNL_MANUFACTURER "TBS"

6
include/configs/tegra-common-usb-gadget.h
View File

@ -18,12 +18,12 @@
#define CONFIG_G_DNL_VENDOR_NUM 0x0955
#define CONFIG_G_DNL_PRODUCT_NUM 0x701A
#define CONFIG_G_DNL_MANUFACTURER "NVIDIA"
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_GADGET_DOWNLOAD
/* USB mass storage protocol */
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_CMD_USB_MASS_STORAGE
/* DFU protocol */
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_SYS_DFU_DATA_BUF_SIZE (1 * 1024 * 1024)
#define CONFIG_CMD_DFU
#ifdef CONFIG_MMC

2
include/configs/ti_omap5_common.h
View File

@ -135,7 +135,7 @@
"if test ${dofastboot} -eq 1; then " \
"echo Boot fastboot requested, resetting dofastboot ...;" \
"setenv dofastboot 0; saveenv;" \
"echo Booting into fastboot ...; fastboot;" \
"echo Booting into fastboot ...; fastboot 0;" \
"fi;" \
"run findfdt; " \
"run mmcboot;" \

6
include/configs/warp.h
View File

@ -80,8 +80,8 @@
#define CONFIG_USB_GADGET
#define CONFIG_CMD_USB_MASS_STORAGE
#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USBDOWNLOAD_GADGET
#define CONFIG_USB_FUNCTION_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
#define CONFIG_USB_GADGET_VBUS_DRAW 2
#define CONFIG_G_DNL_VENDOR_NUM 0x0525
@ -89,7 +89,7 @@
#define CONFIG_G_DNL_MANUFACTURER "FSL"
#define CONFIG_CMD_DFU
#define CONFIG_DFU_FUNCTION
#define CONFIG_USB_FUNCTION_DFU
#define CONFIG_DFU_MMC
#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_16M
#define DFU_DEFAULT_POLL_TIMEOUT 300

6
include/configs/zynq-common.h
View File

@ -110,10 +110,10 @@
# define CONFIG_CI_UDC /* ChipIdea CI13xxx UDC */
# define CONFIG_USB_GADGET
# define CONFIG_USB_GADGET_DUALSPEED
# define CONFIG_USBDOWNLOAD_GADGET
# define CONFIG_USB_GADGET_DOWNLOAD
# define CONFIG_SYS_DFU_DATA_BUF_SIZE 0x600000
# define DFU_DEFAULT_POLL_TIMEOUT 300
# define CONFIG_DFU_FUNCTION
# define CONFIG_USB_FUNCTION_DFU
# define CONFIG_DFU_RAM
# define CONFIG_USB_GADGET_VBUS_DRAW 2
# define CONFIG_G_DNL_VENDOR_NUM 0x03FD
@ -123,7 +123,7 @@
# define CONFIG_USB_CABLE_CHECK
# define CONFIG_CMD_DFU
# define CONFIG_CMD_THOR_DOWNLOAD
# define CONFIG_THOR_FUNCTION
# define CONFIG_USB_FUNCTION_THOR
# define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"set dfu_alt_info " \

1
include/g_dnl.h
View File

@ -34,6 +34,7 @@ struct g_dnl_bind_callback {
};
int g_dnl_bind_fixup(struct usb_device_descriptor *, const char *);
int g_dnl_get_board_bcd_device_number(int gcnum);
int g_dnl_board_usb_cable_connected(void);
int g_dnl_register(const char *s);
void g_dnl_unregister(void);

28
include/linux/usb/dwc3.h
View File

@ -109,7 +109,11 @@ struct dwc3 { /* offset: 0xC100 */
u32 g_hwparams8;
u32 reserved4[63];
u32 reserved4[11];
u32 g_fladj;
u32 reserved5[51];
u32 d_cfg;
u32 d_ctl;
@ -118,15 +122,15 @@ struct dwc3 { /* offset: 0xC100 */
u32 d_gcmdpar;
u32 d_gcmd;
u32 reserved5[2];
u32 reserved6[2];
u32 d_alepena;
u32 reserved6[55];
u32 reserved7[55];
struct d_physical_endpoint d_phy_ep_cmd[32];
u32 reserved7[128];
u32 reserved8[128];
u32 o_cfg;
u32 o_ctl;
@ -134,7 +138,7 @@ struct dwc3 { /* offset: 0xC100 */
u32 o_evten;
u32 o_sts;
u32 reserved8[3];
u32 reserved9[3];
u32 adp_cfg;
u32 adp_ctl;
@ -143,7 +147,7 @@ struct dwc3 { /* offset: 0xC100 */
u32 bc_cfg;
u32 reserved9;
u32 reserved10;
u32 bc_evt;
u32 bc_evten;
@ -191,4 +195,16 @@ struct dwc3 { /* offset: 0xC100 */
#define DWC3_DCTL_CSFTRST (1 << 30)
#define DWC3_DCTL_LSFTRST (1 << 29)
/* Global Frame Length Adjustment Register */
#define GFLADJ_30MHZ_REG_SEL (1 << 7)
#define GFLADJ_30MHZ(n) ((n) & 0x3f)
#define GFLADJ_30MHZ_DEFAULT 0x20
#ifdef CONFIG_USB_XHCI_DWC3
void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode);
void dwc3_core_soft_reset(struct dwc3 *dwc3_reg);
int dwc3_core_init(struct dwc3 *dwc3_reg);
void usb_phy_reset(struct dwc3 *dwc3_reg);
void dwc3_set_fladj(struct dwc3 *dwc3_reg, u32 val);
#endif
#endif /* __DWC3_H_ */

64
include/linux/usb/xhci-fsl.h Normal file
View File

@ -0,0 +1,64 @@
/*
* Copyright 2015 Freescale Semiconductor, Inc.
*
* FSL USB HOST xHCI Controller
*
* Author: Ramneek Mehresh<ramneek.mehresh@freescale.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _ASM_ARCH_XHCI_FSL_H_
#define _ASM_ARCH_XHCI_FSL_H_
/* Default to the FSL XHCI defines */
#define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
#define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
#define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
#define USB3_PHY_RX_POWERON BIT(14)
#define USB3_PHY_TX_POWERON BIT(15)
#define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
#define USB3_PWRCTL_CLK_CMD_SHIFT 14
#define USB3_PWRCTL_CLK_FREQ_SHIFT 22
/* USBOTGSS_WRAPPER definitions */
#define USBOTGSS_WRAPRESET BIT(17)
#define USBOTGSS_DMADISABLE BIT(16)
#define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
#define USBOTGSS_STANDBYMODE_SMRT BIT(5)
#define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
#define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
#define USBOTGSS_IDLEMODE_SMRT BIT(3)
#define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
/* USBOTGSS_IRQENABLE_SET_0 bit */
#define USBOTGSS_COREIRQ_EN BIT(1)
/* USBOTGSS_IRQENABLE_SET_1 bits */
#define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
#define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
#define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
#define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
#define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
#define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
#define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
#define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
#define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
struct fsl_xhci {
struct xhci_hccr *hcd;
struct dwc3 *dwc3_reg;
};
#if defined(CONFIG_LS102XA)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS102XA_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR 0
#elif defined(CONFIG_LS2085A)
#define CONFIG_SYS_FSL_XHCI_USB1_ADDR CONFIG_SYS_LS2085A_XHCI_USB1_ADDR
#define CONFIG_SYS_FSL_XHCI_USB2_ADDR CONFIG_SYS_LS2085A_XHCI_USB2_ADDR
#endif
#define FSL_USB_XHCI_ADDR {CONFIG_SYS_FSL_XHCI_USB1_ADDR, \
CONFIG_SYS_FSL_XHCI_USB2_ADDR}
#endif /* _ASM_ARCH_XHCI_FSL_H_ */