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Merge tag 'u-boot-imx-20191014' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

Browse Source 
u-boot-imx-20191014
-------------------

Travis: https://travis-ci.org/sbabic/u-boot-imx/builds/597498628

	- logicpd pinmux
	- i.MX7ULP: imx_ddr_size
	- fixes Toradex i.MX6/i.MX7
	- pico-imx7d
	- tpc70 converted to DM
	- New Board: meerkat96
	- add HAB version command
	- i.MX8 :
      		imx8: Jump from alias to OCRAM address at SPL init
      		imx8qm/qxp: Set SPL TEXT base to OCRAM base
This commit is contained in:
Tom Rini
2019-10-14 13:00:51 -04:00
parent cd5ffc5de5 d02be21d30
commit 6f1f28b8e1
49 changed files with 1270 additions and 665 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
board/freescale/imx8mm_evk/imx8mm_evk.c
View File

@@ -19,6 +19,11 @@ int board_init(void)
return 0;
}
int board_mmc_get_env_dev(int devno)
{
return devno;
}
int board_late_init(void)
{
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

2
board/freescale/mx7ulp_evk/mx7ulp_evk.c
View File

@@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
gd->ram_size = imx_ddr_size();
return 0;
}

172
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc.c
View File

@@ -9,64 +9,18 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <env.h>
#include <errno.h>
#include <fsl_esdhc_imx.h>
#include <fuse.h>
#include <i2c.h>
#include <miiphy.h>
#include <mmc.h>
#include <net.h>
#include <netdev.h>
#include <usb.h>
#include <usb/ehci-ci.h>
#include <led.h>
DECLARE_GLOBAL_DATA_PTR;
#define ENET_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS)
#define I2C_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info0 = {
.scl = {
.i2c_mode = MX6Q_PAD_CSI0_DAT9__I2C1_SCL | PC,
.gpio_mode = MX6Q_PAD_CSI0_DAT9__GPIO5_IO27 | PC,
.gp = IMX_GPIO_NR(5, 27)
},
.sda = {
.i2c_mode = MX6Q_PAD_CSI0_DAT8__I2C1_SDA | PC,
.gpio_mode = MX6Q_PAD_CSI0_DAT8__GPIO5_IO26 | PC,
.gp = IMX_GPIO_NR(5, 26)
}
};
static struct i2c_pads_info kp_imx6q_tpc_i2c_pad_info1 = {
.scl = {
.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
int dram_init(void)
{
gd->ram_size = imx_ddr_size();
@@ -83,56 +37,17 @@ int overwrite_console(void)
}
#ifdef CONFIG_FEC_MXC
static iomux_v3_cfg_t const enet_pads[] = {
IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* AR8031 PHY Reset */
IOMUX_PADS(PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void eth_phy_reset(void)
{
/* Reset AR8031 PHY */
gpio_direction_output(IMX_GPIO_NR(1, 25), 0);
mdelay(10);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
udelay(100);
}
static int setup_fec_clock(void)
{
struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
/* set gpr1[21] to select anatop clock */
clrsetbits_le32(&iomuxc_regs->gpr[1], 0x1 << 21, 0x1 << 21);
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK,
IOMUXC_GPR1_ENET_CLK_SEL_MASK);
return enable_fec_anatop_clock(0, ENET_50MHZ);
}
int board_eth_init(bd_t *bis)
{
SETUP_IOMUX_PADS(enet_pads);
setup_fec_clock();
eth_phy_reset();
return cpu_eth_init(bis);
}
static int ar8031_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
@@ -167,53 +82,6 @@ int board_phy_config(struct phy_device *phydev)
}
#endif
#ifdef CONFIG_FSL_ESDHC_IMX
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
static struct fsl_esdhc_cfg usdhc_cfg[] = {
{ USDHC2_BASE_ADDR },
{ USDHC4_BASE_ADDR },
};
int board_mmc_getcd(struct mmc *mmc)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
return !gpio_get_value(USDHC2_CD_GPIO);
case USDHC4_BASE_ADDR:
return 1; /* eMMC/uSDHC4 is always present */
}
return 0;
}
int board_mmc_init(bd_t *bis)
{
int i, ret;
/*
* According to the board_mmc_init() the following map is done:
* (U-Boot device node) (Physical Port)
* mmc0 micro SD
* mmc2 eMMC
*/
gpio_direction_input(USDHC2_CD_GPIO);
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
if (ret)
return ret;
}
return 0;
}
#endif
#ifdef CONFIG_USB_EHCI_MX6
static void setup_usb(void)
{
@@ -223,30 +91,6 @@ static void setup_usb(void)
*/
imx_iomux_set_gpr_register(1, 13, 1, 0);
}
int board_usb_phy_mode(int port)
{
if (port == 1)
return USB_INIT_HOST;
else
return USB_INIT_DEVICE;
}
int board_ehci_power(int port, int on)
{
switch (port) {
case 0:
break;
case 1:
gpio_direction_output(IMX_GPIO_NR(3, 31), !!on);
break;
default:
printf("MXC USB port %d not yet supported\n", port);
return -EINVAL;
}
return 0;
}
#endif
int board_early_init_f(void)
@@ -255,6 +99,10 @@ int board_early_init_f(void)
setup_usb();
#endif
#ifdef CONFIG_FEC_MXC
setup_fec_clock();
#endif
return 0;
}
@@ -268,9 +116,6 @@ int board_init(void)
/* Enable eim_slow clocks */
setbits_le32(&mxc_ccm->CCGR6, 0x1 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET);
setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info0);
setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &kp_imx6q_tpc_i2c_pad_info1);
return 0;
}
@@ -290,6 +135,9 @@ int board_late_init(void)
add_board_boot_modes(board_boot_modes);
#endif
if (IS_ENABLED(CONFIG_LED))
led_default_state();
env_set("boardname", "kp-tpc");
env_set("boardsoc", "imx6q");
return 0;

137
board/k+p/kp_imx6q_tpc/kp_imx6q_tpc_spl.c
View File

@@ -9,30 +9,12 @@
#include <asm/arch/clock.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux.h>
#include <asm/arch/mx6-ddr.h>
#include <asm/arch/mx6-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/gpio.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/mach-imx/mxc_i2c.h>
#include <asm/io.h>
#include <errno.h>
#include <fuse.h>
#include <fsl_esdhc_imx.h>
#include <i2c.h>
#include <mmc.h>
#include <spl.h>
#define UART_PAD_CTRL \
(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define USDHC_PAD_CTRL \
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
DECLARE_GLOBAL_DATA_PTR;
static void ccgr_init(void)
@@ -48,60 +30,6 @@ static void ccgr_init(void)
writel(0x000003FF, &ccm->CCGR6);
}
/* onboard microSD */
static iomux_v3_cfg_t const usdhc2_pads[] = {
IOMUX_PADS(PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/* eMMC */
static iomux_v3_cfg_t const usdhc4_pads[] = {
IOMUX_PADS(PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
IOMUX_PADS(PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
};
/* SD */
static void setup_iomux_sd(void)
{
SETUP_IOMUX_PADS(usdhc2_pads);
SETUP_IOMUX_PADS(usdhc4_pads);
}
/* UART */
static iomux_v3_cfg_t const uart1_pads[] = {
IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
static void setup_iomux_uart(void)
{
SETUP_IOMUX_PADS(uart1_pads);
}
/* USB */
static iomux_v3_cfg_t const usb_pads[] = {
IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL)),
IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static void setup_iomux_usb(void)
{
SETUP_IOMUX_PADS(usb_pads);
}
/* DDR3 */
static const struct mx6dq_iomux_ddr_regs mx6_ddr_ioregs = {
.dram_sdclk_0 = 0x00000030,
@@ -255,57 +183,24 @@ static void spl_dram_init(void)
#endif
}
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC2_BASE_ADDR},
{USDHC4_BASE_ADDR},
};
#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
int board_mmc_getcd(struct mmc *mmc)
void board_boot_order(u32 *spl_boot_list)
{
struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
int ret = 0;
u32 boot_device = spl_boot_device();
u32 reg = imx6_src_get_boot_mode();
switch (cfg->esdhc_base) {
case USDHC2_BASE_ADDR:
ret = !gpio_get_value(USDHC2_CD_GPIO);
break;
case USDHC4_BASE_ADDR:
ret = 1; /* eMMC/uSDHC4 is always present */
break;
}
reg = (reg & IMX6_BMODE_MASK) >> IMX6_BMODE_SHIFT;
return ret;
}
debug("%s: boot device: 0x%x (0x4 SD, 0x6 eMMC)\n", __func__, reg);
if (boot_device == BOOT_DEVICE_MMC1)
if (reg == IMX6_BMODE_MMC || reg == IMX6_BMODE_EMMC)
boot_device = BOOT_DEVICE_MMC2;
int board_mmc_init(bd_t *bd)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
spl_boot_list[0] = boot_device;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1
* 0x3 SD4
* Below boot device is a 'fallback' - it shall always be possible to
* boot from SD card
*/
switch (reg & 0x3) {
case 0x1:
SETUP_IOMUX_PADS(usdhc2_pads);
usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
case 0x3:
SETUP_IOMUX_PADS(usdhc4_pads);
usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
break;
}
return fsl_esdhc_initialize(bd, &usdhc_cfg[0]);
spl_boot_list[1] = BOOT_DEVICE_MMC1;
}
void board_init_f(ulong dummy)
@@ -319,9 +214,8 @@ void board_init_f(ulong dummy)
/* setup GP timer */
timer_init();
setup_iomux_sd();
setup_iomux_uart();
setup_iomux_usb();
/* Early - pre reloc - driver model setup */
spl_early_init();
/* UART clocks enabled and gd valid - init serial console */
preloader_console_init();
@@ -331,7 +225,4 @@ void board_init_f(ulong dummy)
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */
board_init_r(NULL, 0);
}

85
board/logicpd/imx6/imx6logic.c
View File

@@ -42,32 +42,6 @@ int dram_init(void)
return 0;
}
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT5__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT6__UART2_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const uart3_pads[] = {
MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_EIM_EB3__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
static iomux_v3_cfg_t const nand_pads[] = {
MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
@@ -135,7 +109,6 @@ int overwrite_console(void)
int board_early_init_f(void)
{
setup_iomux_uart();
setup_nand_pins();
return 0;
}
@@ -177,36 +150,6 @@ int spl_start_uboot(void)
}
#endif
/* SD interface */
#define USDHC_PAD_CTRL \
(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
static iomux_v3_cfg_t const usdhc1_pads[] = {
MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
};
static iomux_v3_cfg_t const usdhc2_pads[] = {
MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
};
#ifdef CONFIG_FSL_ESDHC_IMX
struct fsl_esdhc_cfg usdhc_cfg[] = {
{USDHC1_BASE_ADDR}, /* SOM */
{USDHC2_BASE_ADDR} /* Baseboard */
};
void board_boot_order(u32 *spl_boot_list)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
@@ -236,34 +179,6 @@ void board_boot_order(u32 *spl_boot_list)
spl_boot_list[2] = BOOT_DEVICE_BOARD;
}
int board_mmc_init(bd_t *bis)
{
struct src *psrc = (struct src *)SRC_BASE_ADDR;
unsigned int reg = readl(&psrc->sbmr1) >> 11;
/*
* Upon reading BOOT_CFG register the following map is done:
* Bit 11 and 12 of BOOT_CFG register can determine the current
* mmc port
* 0x1 SD1-SOM
* 0x2 SD2-Baseboard
*/
reg &= 0x3; /* Only care about bottom 2 bits */
switch (reg) {
case 0:
SETUP_IOMUX_PADS(usdhc1_pads);
break;
case 1:
SETUP_IOMUX_PADS(usdhc2_pads);
break;
}
return 0;
}
#endif
static void ccgr_init(void)
{
struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

12
board/novtech/meerkat96/Kconfig Normal file
View File

@@ -0,0 +1,12 @@
if TARGET_MEERKAT96
config SYS_BOARD
default "meerkat96"
config SYS_VENDOR
default "novtech"
config SYS_CONFIG_NAME
default "meerkat96"
endif

6
board/novtech/meerkat96/MAINTAINERS Normal file
View File

@@ -0,0 +1,6 @@
MEERKAT96 BOARD
M: Shawn Guo <shawn.guo@kernel.org>
S: Maintained
F: board/novtech/meerkat96
F: include/configs/meerkat96.h
F: configs/meerkat96_defconfig

1
board/novtech/meerkat96/Makefile Normal file
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@@ -0,0 +1 @@
obj-y := meerkat96.o

18
board/novtech/meerkat96/README Normal file
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@@ -0,0 +1,18 @@
* Build U-Boot for Meerkat96 board
$ make mrproper
$ make meerkat96_defconfig
$ make
It will generate the U-Boot binary called u-boot-dtb.imx
* Install U-Boot to MicroSD card
Plug MicroSD card to a Linux machine (with card reader), find the
device name and replace sd[x] with the name in the following command.
$ sudo dd if=u-boot-dtb.imx of=/dev/sd[x] bs=512 seek=2
It will install U-Boot to MicroSD card at 1KiB offset. Insert the
card to Meerkat96 MicroSD slot, power up the board, and U-Boot should
boot from the card.

127
board/novtech/meerkat96/imximage.cfg Normal file
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/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*
* Refer docs/README.imxmage for more details about how-to configure
* and create imximage boot image
*
* The syntax is taken as close as possible with the kwbimage
*/
#define __ASSEMBLY__
#include <config.h>
/* image version */
IMAGE_VERSION 2
/*
* Boot Device : sd
*/
BOOT_FROM sd
/*
* Secure boot support
*/
#ifdef CONFIG_SECURE_BOOT
CSF CONFIG_CSF_SIZE
#endif
/*
* Device Configuration Data (DCD)
*
* Each entry must have the format:
* Addr-type Address Value
*
* where:
* Addr-type register length (1,2 or 4 bytes)
* Address absolute address of the register
* value value to be stored in the register
*/
/* Enable OCRAM EPDC */
DATA 4 0x30340004 0x4F400005
/* =============================================================================
* DDR Controller Registers
* =============================================================================
* Memory type: DDR3
* Manufacturer: ISSI
* Device Part Number: IS43TR16256AL-125KBL
* Clock Freq.: 533MHz
* Density per CS in Gb: 4
* Chip Selects used: 1
* Number of Banks: 8
* Row address: 15
* Column address: 10
* Data bus width: 16
* ROW-BANK interleave: ENABLED
* =============================================================================
*/
DATA 4 0x30391000 0x00000002 // deassert presetn
DATA 4 0x307A0000 0x01041001 // DDRC_MSTR
DATA 4 0x307A0064 0x00400046 // DDRC_RFSHTMG
DATA 4 0x307a0490 0x00000001 // DDRC_PCTRL_0
DATA 4 0x307A00D4 0x00690000 // DDRC_INIT1
DATA 4 0x307A00D0 0x00020083 // DDRC_INIT0
DATA 4 0x307A00DC 0x09300004 // DDRC_INIT3
DATA 4 0x307A00E0 0x04080000 // DDRC_INIT4
DATA 4 0x307A00E4 0x00100004 // DDRC_INIT5
DATA 4 0x307A00F4 0x0000033F // DDRC_RANKCTL
DATA 4 0x307A0100 0x090B1109 // DDRC_DRAMTMG0
DATA 4 0x307A0104 0x0007020D // DDRC_DRAMTMG1
DATA 4 0x307A0108 0x03040407 // DDRC_DRAMTMG2
DATA 4 0x307A010C 0x00002006 // DDRC_DRAMTMG3
DATA 4 0x307A0110 0x04020205 // DDRC_DRAMTMG4
DATA 4 0x307A0114 0x03030202 // DDRC_DRAMTMG5
DATA 4 0x307A0120 0x00000803 // DDRC_DRAMTMG8
DATA 4 0x307A0180 0x00800020 // DDRC_ZQCTL0
DATA 4 0x307A0190 0x02098204 // DDRC_DFITMG0
DATA 4 0x307A0194 0x00030303 // DDRC_DFITMG1
DATA 4 0x307A01A0 0x80400003 // DDRC_DFIUPD0
DATA 4 0x307A01A4 0x00100020 // DDRC_DFIUPD1
DATA 4 0x307A01A8 0x80100004 // DDRC_DFIUPD2
DATA 4 0x307A0200 0x00000015 // DDRC_ADDRMAP0
DATA 4 0x307A0204 0x00070707 // DDRC_ADDRMAP1
DATA 4 0x307A0210 0x00000F0F // DDRC_ADDRMAP4
DATA 4 0x307A0214 0x06060606 // DDRC_ADDRMAP5
DATA 4 0x307A0218 0x0F060606 // DDRC_ADDRMAP6
DATA 4 0x307A0240 0x06000604 // DDRC_ODTCFG
DATA 4 0x307A0244 0x00000001 // DDRC_ODTMAP
/* =============================================================================
* PHY Control Register
* =============================================================================
*/
DATA 4 0x30391000 0x00000000 // deassert presetn
DATA 4 0x30790000 0x17420F40 // DDR_PHY_PHY_CON0
DATA 4 0x30790004 0x10210100 // DDR_PHY_PHY_CON1
DATA 4 0x30790010 0x00060807 // DDR_PHY_PHY_CON4
DATA 4 0x307900B0 0x1010007E // DDR_PHY_MDLL_CON0
DATA 4 0x3079009C 0x00000D6E // DDR_PHY_DRVDS_CON0
DATA 4 0x30790030 0x08080808 // DDR_PHY_OFFSET_WR_CON0
DATA 4 0x30790020 0x08080808 // DDR_PHY_OFFSET_RD_CON0
DATA 4 0x30790050 0x01000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790050 0x00000010 // DDR_PHY_OFFSETD_CON0
DATA 4 0x30790018 0x0000000F // DDR_PHY_LP_CON0
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - Start Manual ZQ
DATA 4 0x307900C0 0x0E447304
DATA 4 0x307900C0 0x0E447306
DATA 4 0x307900C0 0x0E447304 // <= NOTE: Depending on JTAG device used, may need ~ 7 us pause at this point.
DATA 4 0x307900C0 0x0E407304 // DDR_PHY_ZQ_CON0 - End Manual ZQ
/* =============================================================================
* Final Initialization start sequence
* =============================================================================
*/
DATA 4 0x30384130 0x00000000 // Disable Clock
DATA 4 0x30340020 0x00000178 // IOMUX_GRP_GRP8 - Start input to PHY
DATA 4 0x30384130 0x00000002 // Enable Clock
/* <= NOTE: Depending on JTAG device used, may need ~ 250 us pause at this point. */

71
board/novtech/meerkat96/meerkat96.c Normal file
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@@ -0,0 +1,71 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Linaro Ltd.
* Copyright (C) 2016 NXP Semiconductors
*/
#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx7-pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/iomux-v3.h>
#include <asm/io.h>
#include <common.h>
#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
static iomux_v3_cfg_t const meerkat96_pads[] = {
/* UART6 as debug serial */
MX7D_PAD_SD1_CD_B__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
MX7D_PAD_SD1_WP__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
/* WDOG1 for reset */
MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int dram_init(void)
{
gd->ram_size = PHYS_SDRAM_SIZE;
return 0;
}
int board_early_init_f(void)
{
imx_iomux_v3_setup_multiple_pads(meerkat96_pads,
ARRAY_SIZE(meerkat96_pads));
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int checkboard(void)
{
char *mode;
if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT))
mode = "secure";
else
mode = "non-secure";
printf("Board: i.MX7D Meerkat96 in %s mode\n", mode);
return 0;
}
int board_late_init(void)
{
set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
return 0;
}

92
board/tbs/tbs2910/tbs2910.c
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@@ -14,25 +14,16 @@
#include <asm/mach-imx/video.h>
#include <mmc.h>
#include <fsl_esdhc_imx.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/arch/mxc_hdmi.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#define WEAK_PULLUP (PAD_CTL_PUS_47K_UP | \
PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
PAD_CTL_SRE_SLOW)
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
PAD_CTL_SRE_FAST | PAD_CTL_HYS)
#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
static iomux_v3_cfg_t const uart1_pads[] = {
MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -43,55 +34,12 @@ static iomux_v3_cfg_t const uart2_pads[] = {
MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static iomux_v3_cfg_t const enet_pads[] = {
MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
/* AR8035 PHY Reset */
MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static iomux_v3_cfg_t const pcie_pads[] = {
/* W_DISABLE# */
MX6_PAD_KEY_COL4__GPIO4_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
/* PERST# */
MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
int dram_init(void)
{
gd->ram_size = 2048ul * 1024 * 1024;
return 0;
}
static void setup_iomux_enet(void)
{
imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
/* Reset AR8035 PHY */
gpio_request(IMX_GPIO_NR(1, 25), "ETH_PHY_RESET");
gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
udelay(500);
gpio_set_value(IMX_GPIO_NR(1, 25), 1);
}
static void setup_pcie(void)
{
imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
}
static void setup_iomux_uart(void)
{
imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -200,46 +148,6 @@ static void setup_display(void)
}
#endif /* CONFIG_VIDEO_IPUV3 */
static int ar8035_phy_fixup(struct phy_device *phydev)
{
unsigned short val;
/* To enable AR8035 ouput a 125MHz clk from CLK_25M */
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
val &= 0xffe3;
val |= 0x18;
phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
/* introduce tx clock delay */
phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
val |= 0x0100;
phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
return 0;
}
int board_phy_config(struct phy_device *phydev)
{
ar8035_phy_fixup(phydev);
if (phydev->drv->config)
phydev->drv->config(phydev);
return 0;
}
int board_eth_init(bd_t *bis)
{
setup_iomux_enet();
setup_pcie();
return cpu_eth_init(bis);
}
int board_early_init_f(void)
{
setup_iomux_uart();

4
board/toradex/colibri_imx7/colibri_imx7.c
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@@ -274,7 +274,7 @@ int power_init_board(void)
int ret;
ret = pmic_get("rn5t567", &dev);
ret = pmic_get("rn5t567@33", &dev);
if (ret)
return ret;
ver = pmic_reg_read(dev, RN5T567_LSIVER);
@@ -308,7 +308,7 @@ void reset_cpu(ulong addr)
{
struct udevice *dev;
pmic_get("rn5t567", &dev);
pmic_get("rn5t567@33", &dev);
/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
pmic_reg_write(dev, RN5T567_REPCNT, 0x1);