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net: dwc_eth_qos: Pad descriptors to cacheline size

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The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
after the descriptor. Use this to pad the descriptors to cacheline size and
remove the need for noncached memory altogether. Moreover, this lets Tegra
use the generic cache flush / invalidate operations.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Cc: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Marek Vasut
2021-01-07 11:12:16 +01:00
committed by Tom Rini
parent dd70ff4815
commit 6f1e668d96
2 changed files with 51 additions and 79 deletions
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1
include/configs/stm32mp1.h
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@@ -69,7 +69,6 @@
/* Ethernet need */
#ifdef CONFIG_DWC_ETH_QOS
#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */
#define CONFIG_SERVERIP 192.168.1.1
#define CONFIG_BOOTP_SERVERIP
#define CONFIG_SYS_AUTOLOAD "no"