Blackfin: bfin_spi: add optional DMA support
This moves the last piece from the old spi_flash driver to the new SPI framework -- optional DMA RX support. This typically cuts speeds by ~40% at the cost of additional ~300 bytes. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger
parent
2c0a6f2d4f
commit
6f070e1867
75
arch/blackfin/include/asm/dma.h
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75
arch/blackfin/include/asm/dma.h
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@ -0,0 +1,75 @@
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/*
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* dma.h - Blackfin DMA defines/structures/etc...
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*
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* Copyright 2004-2008 Analog Devices Inc.
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _BLACKFIN_DMA_H_
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#define _BLACKFIN_DMA_H_
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#include <asm/mach-common/bits/dma.h>
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struct dmasg_large {
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void *next_desc_addr;
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unsigned long start_addr;
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unsigned short cfg;
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unsigned short x_count;
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short x_modify;
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unsigned short y_count;
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short y_modify;
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} __attribute__((packed));
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struct dmasg {
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unsigned long start_addr;
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unsigned short cfg;
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unsigned short x_count;
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short x_modify;
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unsigned short y_count;
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short y_modify;
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} __attribute__((packed));
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struct dma_register {
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void *next_desc_ptr; /* DMA Next Descriptor Pointer register */
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unsigned long start_addr; /* DMA Start address register */
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unsigned short cfg; /* DMA Configuration register */
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unsigned short dummy1; /* DMA Configuration register */
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unsigned long reserved;
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unsigned short x_count; /* DMA x_count register */
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unsigned short dummy2;
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short x_modify; /* DMA x_modify register */
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unsigned short dummy3;
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unsigned short y_count; /* DMA y_count register */
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unsigned short dummy4;
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short y_modify; /* DMA y_modify register */
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unsigned short dummy5;
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void *curr_desc_ptr; /* DMA Current Descriptor Pointer
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register */
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unsigned long curr_addr_ptr; /* DMA Current Address Pointer
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register */
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unsigned short irq_status; /* DMA irq status register */
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unsigned short dummy6;
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unsigned short peripheral_map; /* DMA peripheral map register */
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unsigned short dummy7;
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unsigned short curr_x_count; /* DMA Current x-count register */
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unsigned short dummy8;
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unsigned long reserved2;
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unsigned short curr_y_count; /* DMA Current y-count register */
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unsigned short dummy9;
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unsigned long reserved3;
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};
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#endif
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@ -1,7 +1,7 @@
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/*
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* Driver for Blackfin On-Chip SPI device
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (c) 2005-2010 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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@ -13,6 +13,7 @@
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#include <spi.h>
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#include <asm/blackfin.h>
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#include <asm/dma.h>
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#include <asm/gpio.h>
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#include <asm/portmux.h>
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#include <asm/mach-common/bits/spi.h>
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@ -237,10 +238,131 @@ void spi_release_bus(struct spi_slave *slave)
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SSYNC();
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}
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#ifdef __ADSPBF54x__
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# define SPI_DMA_BASE DMA4_NEXT_DESC_PTR
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#elif defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__) || \
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defined(__ADSPBF538__) || defined(__ADSPBF539__)
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# define SPI_DMA_BASE DMA5_NEXT_DESC_PTR
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#elif defined(__ADSPBF561__)
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# define SPI_DMA_BASE DMA2_4_NEXT_DESC_PTR
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#elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__) || \
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defined(__ADSPBF52x__) || defined(__ADSPBF51x__)
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# define SPI_DMA_BASE DMA7_NEXT_DESC_PTR
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#else
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# error "Please provide SPI DMA channel defines"
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#endif
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static volatile struct dma_register *dma = (void *)SPI_DMA_BASE;
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#ifndef CONFIG_BFIN_SPI_IDLE_VAL
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# define CONFIG_BFIN_SPI_IDLE_VAL 0xff
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#endif
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#ifdef CONFIG_BFIN_SPI_NO_DMA
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# define SPI_DMA 0
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#else
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# define SPI_DMA 1
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#endif
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static int spi_dma_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
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uint bytes)
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{
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int ret = -1;
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u16 ndsize, spi_config, dma_config;
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struct dmasg dmasg[2];
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const u8 *buf;
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if (tx) {
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debug("%s: doing half duplex TX\n", __func__);
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buf = tx;
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spi_config = TDBR_DMA;
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dma_config = 0;
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} else {
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debug("%s: doing half duplex RX\n", __func__);
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buf = rx;
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spi_config = RDBR_DMA;
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dma_config = WNR;
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}
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dmasg[0].start_addr = (unsigned long)buf;
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dmasg[0].x_modify = 1;
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dma_config |= WDSIZE_8 | DMAEN;
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if (bytes <= 65536) {
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blackfin_dcache_flush_invalidate_range(buf, buf + bytes);
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ndsize = NDSIZE_5;
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dmasg[0].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
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dmasg[0].x_count = bytes;
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} else {
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blackfin_dcache_flush_invalidate_range(buf, buf + 65536 - 1);
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ndsize = NDSIZE_7;
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dmasg[0].cfg = NDSIZE_5 | dma_config | FLOW_ARRAY | DMA2D;
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dmasg[0].x_count = 0; /* 2^16 */
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dmasg[0].y_count = bytes >> 16; /* count / 2^16 */
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dmasg[0].y_modify = 1;
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dmasg[1].start_addr = (unsigned long)(buf + (bytes & ~0xFFFF));
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dmasg[1].cfg = NDSIZE_0 | dma_config | FLOW_STOP | DI_EN;
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dmasg[1].x_count = bytes & 0xFFFF; /* count % 2^16 */
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dmasg[1].x_modify = 1;
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}
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dma->cfg = 0;
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dma->irq_status = DMA_DONE | DMA_ERR;
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dma->curr_desc_ptr = dmasg;
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write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE));
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write_SPI_STAT(bss, -1);
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SSYNC();
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write_SPI_TDBR(bss, CONFIG_BFIN_SPI_IDLE_VAL);
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dma->cfg = ndsize | FLOW_ARRAY | DMAEN;
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write_SPI_CTL(bss, (bss->ctl & ~TDBR_CORE) | spi_config);
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SSYNC();
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/*
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* We already invalidated the first 64k,
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* now while we just wait invalidate the remaining part.
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* Its not likely that the DMA is going to overtake
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*/
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if (bytes > 65536)
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blackfin_dcache_flush_invalidate_range(buf + 65536, buf + bytes);
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while (!(dma->irq_status & DMA_DONE))
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if (ctrlc())
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goto done;
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dma->cfg = 0;
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ret = 0;
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done:
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write_SPI_CTL(bss, bss->ctl);
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return ret;
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}
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static int spi_pio_xfer(struct bfin_spi_slave *bss, const u8 *tx, u8 *rx,
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uint bytes)
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{
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/* todo: take advantage of hardware fifos */
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while (bytes--) {
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u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
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debug("%s: tx:%x ", __func__, value);
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write_SPI_TDBR(bss, value);
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SSYNC();
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while ((read_SPI_STAT(bss) & TXS))
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if (ctrlc())
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return -1;
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while (!(read_SPI_STAT(bss) & SPIF))
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if (ctrlc())
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return -1;
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while (!(read_SPI_STAT(bss) & RXS))
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if (ctrlc())
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return -1;
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value = read_SPI_RDBR(bss);
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if (rx)
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*rx++ = value;
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debug("rx:%x\n", value);
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}
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return 0;
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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@ -265,32 +387,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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/* todo: take advantage of hardware fifos and setup RX dma */
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while (bytes--) {
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u8 value = (tx ? *tx++ : CONFIG_BFIN_SPI_IDLE_VAL);
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debug("%s: tx:%x ", __func__, value);
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write_SPI_TDBR(bss, value);
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SSYNC();
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while ((read_SPI_STAT(bss) & TXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & SPIF))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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while (!(read_SPI_STAT(bss) & RXS))
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if (ctrlc()) {
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ret = -1;
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goto done;
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}
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value = read_SPI_RDBR(bss);
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if (rx)
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*rx++ = value;
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debug("rx:%x\n", value);
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}
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/* TX DMA doesn't work quite right */
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if (SPI_DMA && bytes > 6 && (!tx /*|| !rx*/))
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ret = spi_dma_xfer(bss, tx, rx, bytes);
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else
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ret = spi_pio_xfer(bss, tx, rx, bytes);
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done:
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if (flags & SPI_XFER_END)
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