From 88486d0423d3a58ce188fcf66e2b7a457acc39c2 Mon Sep 17 00:00:00 2001
From: York Sun <york.sun@nxp.com>
Date: Thu, 14 Sep 2017 12:49:57 -0700
Subject: [PATCH 01/12] armv7: ls1021a: Fix marco CONFIG_LS102XA
Commit a8ecb39e accidentally reverted config macro CONFIG_ARCH_LS1021A
to CONFIG_LS102XA.
Signed-off-by: York Sun <york.sun@nxp.com>
---
include/usb/ehci-ci.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/usb/ehci-ci.h b/include/usb/ehci-ci.h
index cd3eb47da4..59bfc14df6 100644
--- a/include/usb/ehci-ci.h
+++ b/include/usb/ehci-ci.h
@@ -156,7 +156,7 @@
#elif defined(CONFIG_MPC85xx)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC85xx_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR CONFIG_SYS_MPC85xx_USB2_ADDR
-#elif defined(CONFIG_LS102XA) || defined(CONFIG_ARCH_LS1012A)
+#elif defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_ARCH_LS1012A)
#define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_EHCI_USB1_ADDR
#define CONFIG_SYS_FSL_USB2_ADDR 0
#endif
From bdbcb522568fe46dc6141ea1f799e2d08b0e3d76 Mon Sep 17 00:00:00 2001
From: Ashish Kumar <Ashish.Kumar@nxp.com>
Date: Fri, 18 Aug 2017 10:54:35 +0530
Subject: [PATCH 02/12] armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller.
So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6698c0467d..7e5a6baf59 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -323,11 +323,14 @@ int sata_init(void)
{
struct ccsr_ahci __iomem *ccsr_ahci;
+#ifdef CONFIG_SYS_SATA2
ccsr_ahci = (void *)CONFIG_SYS_SATA2;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
+#endif
+#ifdef CONFIG_SYS_SATA1
ccsr_ahci = (void *)CONFIG_SYS_SATA1;
out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
@@ -335,6 +338,7 @@ int sata_init(void)
ahci_init((void __iomem *)CONFIG_SYS_SATA1);
scsi_scan(false);
+#endif
return 0;
}
From 32999fa5d6e8d7dd1542eae39d56837b5b5066b4 Mon Sep 17 00:00:00 2001
From: Santan Kumar <santan.kumar@nxp.com>
Date: Fri, 18 Aug 2017 15:20:31 +0530
Subject: [PATCH 03/12] board/ls2080ardb: Remove CONFIG_DISPLAY_BOARDINFO_LATE
CONFIG_DISPLAY_BOARDINFO_LATE config is used to delay
the prints of boardinfo late in cycle during uboot boot.
This feature is not required in case of QSPI_BOOT.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
include/configs/ls2080ardb.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 145b285685..e301228335 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -18,7 +18,6 @@
#define CONFIG_QIXIS_I2C_ACCESS
#endif
#define CONFIG_SYS_I2C_EARLY_INIT
-#define CONFIG_DISPLAY_BOARDINFO_LATE
#endif
#define I2C_MUX_CH_VOL_MONITOR 0xa
From 77dc01bdc155a133871c0965ff7d012cac2c3a53 Mon Sep 17 00:00:00 2001
From: Santan Kumar <santan.kumar@nxp.com>
Date: Fri, 18 Aug 2017 15:20:32 +0530
Subject: [PATCH 04/12] board/ls2081ardb: Update QSPI flash type from n25q512a
to s25fs512s
As per updated board design, different QSPI flash
is connected on boards, hence change QSPI flash type
from Micron n25q512a device to spansion s25fs512s
device in dts and config.
Signed-off-by: Santan Kumar <santan.kumar@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
arch/arm/dts/fsl-ls2081a-rdb.dts | 4 ++--
include/configs/ls2080ardb.h | 6 +-----
2 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/arch/arm/dts/fsl-ls2081a-rdb.dts b/arch/arm/dts/fsl-ls2081a-rdb.dts
index 6489362fc0..aa4aa68c9c 100644
--- a/arch/arm/dts/fsl-ls2081a-rdb.dts
+++ b/arch/arm/dts/fsl-ls2081a-rdb.dts
@@ -41,7 +41,7 @@
bus-num = <0>;
status = "okay";
- qflash0: n25q512a@0 {
+ qflash0: s25fs512s@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
@@ -49,7 +49,7 @@
reg = <0>;
};
- qflash1: n25q512a@1 {
+ qflash1: s25fs512s@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spi-flash";
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index e301228335..8a89375a57 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -288,19 +288,15 @@ unsigned long get_board_sys_clk(void);
/* SPI */
#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
#define CONFIG_SPI_FLASH
-#ifdef CONFIG_FSL_QSPI
+#ifdef CONFIG_FSL_DSPI
#define CONFIG_SPI_FLASH_STMICRO
#endif
#ifdef CONFIG_FSL_QSPI
-#ifdef CONFIG_TARGET_LS2081ARDB
-#define CONFIG_SPI_FLASH_STMICRO
-#else
#define CONFIG_SPI_FLASH_SPANSION
#endif
#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
#define FSL_QSPI_FLASH_NUM 2
#endif
-#endif
/*
* RTC configuration
From 4b97a8244226646e7670167d83569738d809c85b Mon Sep 17 00:00:00 2001
From: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Date: Thu, 31 Aug 2017 13:26:46 +0530
Subject: [PATCH 05/12] pci: layerscape: Fixup iommu-map for LS208xA
Commit 0aaa1a9 added support for LS208xA devices but fixing
iommu-map property is missing. This patch adds support for
fixing iommu-map.
Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com>
Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
[YS: revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
---
drivers/pci/pcie_layerscape_fixup.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pcie_layerscape_fixup.c b/drivers/pci/pcie_layerscape_fixup.c
index 9e6c2f5dfc..3dae20103d 100644
--- a/drivers/pci/pcie_layerscape_fixup.c
+++ b/drivers/pci/pcie_layerscape_fixup.c
@@ -130,19 +130,28 @@ static void fdt_pcie_set_iommu_map_entry(void *blob, struct ls_pcie *pcie,
u32 iommu_map[4];
int nodeoffset;
int lenp;
+ uint svr;
+ char *compat = NULL;
/* find pci controller node */
nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
pcie->dbi_res.start);
if (nodeoffset < 0) {
#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
- nodeoffset = fdt_node_offset_by_compat_reg(blob,
- CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
+ svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
+ if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
+ svr == SVR_LS2048A || svr == SVR_LS2044A ||
+ svr == SVR_LS2081A || svr == SVR_LS2041A)
+ compat = "fsl,ls2088a-pcie";
+ else
+ compat = CONFIG_FSL_PCIE_COMPAT;
+
+ if (compat)
+ nodeoffset = fdt_node_offset_by_compat_reg(blob,
+ compat, pcie->dbi_res.start);
+#endif
if (nodeoffset < 0)
return;
-#else
- return;
-#endif
}
/* get phandle to iommu controller */
From e45ff0ce63ff36fe66f3c00ace4a0889ac092020 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 4 Sep 2017 15:44:05 +0530
Subject: [PATCH 06/12] armv8: fsl: ifc: Put IFC related code under
CONFIG_FSL_IFC
IFC code is put under CONFIG_FSL_IFC
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++
arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 10 ++++++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 7e5a6baf59..e6142039a6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -297,7 +297,9 @@ void bypass_smmu(void)
void fsl_lsch3_early_init_f(void)
{
erratum_rcw_src();
+#ifdef CONFIG_FSL_IFC
init_early_memctl_regs(); /* tighten IFC timing */
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
erratum_a009203();
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index a0dac86bab..4d7992465a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -106,6 +106,7 @@ static struct mm_region early_map[] = {
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
+#ifdef CONFIG_FSL_IFC
/* For IFC Region #1, only the first 4MB is cache-enabled */
{ CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
CONFIG_SYS_FSL_IFC_SIZE1_1,
@@ -120,6 +121,7 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_IFC_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
+#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -129,11 +131,13 @@ static struct mm_region early_map[] = {
#endif
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
+#ifdef CONFIG_FSL_IFC
/* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
+#endif
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -163,10 +167,12 @@ static struct mm_region early_map[] = {
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
+#ifdef CONFIG_FSL_IFC
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
+#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
@@ -211,11 +217,13 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#ifdef CONFIG_FSL_IFC
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
CONFIG_SYS_FSL_IFC_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#endif
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
CONFIG_SYS_FSL_DCSR_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
@@ -310,10 +318,12 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
+#ifdef CONFIG_FSL_IFC
{ CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
CONFIG_SYS_FSL_IFC_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
+#endif
{ CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
CONFIG_SYS_FSL_DRAM_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
From 0d7f1ae0fe6c0d9af2c0208aab4843ec3fdfaf52 Mon Sep 17 00:00:00 2001
From: Sriram Dash <sriram.dash@nxp.com>
Date: Mon, 4 Sep 2017 15:45:02 +0530
Subject: [PATCH 07/12] armv8: fsl: i2c: Put I2C related code under
CONFIG_SYS_I2C
I2C code is put under CONFIG_SYS_I2C.
Signed-off-by: Sriram Dash <sriram.dash@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index e6142039a6..a90ee0afd7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -260,8 +260,8 @@ static void erratum_rcw_src(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A009203
static void erratum_a009203(void)
{
- u8 __iomem *ptr;
#ifdef CONFIG_SYS_I2C
+ u8 __iomem *ptr;
#ifdef I2C1_BASE_ADDR
ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG);
From 8472d8765b39351680ea9189ecddf99864b13056 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Tue, 29 Aug 2017 15:20:37 +0530
Subject: [PATCH 08/12] board/ls2080ardb: Add mcmemsize variable in default env
For most of ls2080ardb use-cases, mc private DRAM block is required
to be of 1.75GB.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
[YS: this reservation needs to be reduced if memory is not enough]
Reviewed-by: York Sun <york.sun@nxp.com>
---
include/configs/ls2080ardb.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h
index 8a89375a57..9e9979e1c7 100644
--- a/include/configs/ls2080ardb.h
+++ b/include/configs/ls2080ardb.h
@@ -387,6 +387,7 @@ unsigned long get_board_sys_clk(void);
"load_addr=0xa0000000\0" \
"kernel_size=0x2800000\0" \
"console=ttyAMA0,38400n8\0" \
+ "mcmemsize=0x70000000\0" \
MC_INIT_CMD \
BOOTENV \
"boot_scripts=ls2088ardb_boot.scr\0" \
From b5dfd47581b82a8cbe423c0060f0641ae0f5c1b5 Mon Sep 17 00:00:00 2001
From: Priyanka Jain <priyanka.jain@nxp.com>
Date: Fri, 15 Sep 2017 10:19:48 +0530
Subject: [PATCH 09/12] board/ls2080ardb: Update board env based on SoC
As per current implementation, default value of board env is
based on board filename i.e ls2080ardb.
With distro support changes, this env is used to decide upon
kernel dtb which is different for other SoCs (ls2088a, ls2081a)
combination supported with this board.
Add support to modify board env at runtime based on SoC type
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
board/freescale/ls2080ardb/ls2080ardb.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c
index 666562d106..827bfad521 100644
--- a/board/freescale/ls2080ardb/ls2080ardb.c
+++ b/board/freescale/ls2080ardb/ls2080ardb.c
@@ -251,6 +251,8 @@ int misc_init_r(void)
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 val;
+ struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ u32 svr = gur_in32(&gur->svr);
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
@@ -278,6 +280,16 @@ int misc_init_r(void)
if (adjust_vdd(0))
printf("Warning: Adjusting core voltage failed.\n");
+ /*
+ * Default value of board env is based on filename which is
+ * ls2080ardb. Modify board env for other supported SoCs
+ */
+ if ((SVR_SOC_VER(svr) == SVR_LS2088A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2048A))
+ env_set("board", "ls2088ardb");
+ else if ((SVR_SOC_VER(svr) == SVR_LS2081A) ||
+ (SVR_SOC_VER(svr) == SVR_LS2041A))
+ env_set("board", "ls2081ardb");
return 0;
}
From 3c7d647e11d6edcec66c83ac8197cca28f90fbf9 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Fri, 15 Sep 2017 09:51:58 +0800
Subject: [PATCH 10/12] armv8: ls1043a: disable IFC in SPL only when QSPI is
used
Current u-boot disables IFC support for SD boot on all ls1043a
boards. Actually IFC only conflicts with QSPI on ls1043a hardware.
Only when QSPI is used, IFC should be disabled. Otherwise,
the u-boot with ls1043aqds_sdcard_ifc_defconfig would not work.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
include/configs/ls1043a_common.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h
index 002830c27e..1f9efffa56 100644
--- a/include/configs/ls1043a_common.h
+++ b/include/configs/ls1043a_common.h
@@ -22,7 +22,7 @@
#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT))
#define SPL_NO_MMC
#endif
-#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT))
+#if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI))
#define SPL_NO_IFC
#endif
From e2c43a42425f0a8f80bf7e563767a78d28965565 Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Mon, 18 Sep 2017 14:58:37 +0800
Subject: [PATCH 11/12] armv8: ls1043ardb: disable PPA loading during SPL stage
for SD boot
PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
configs/ls1043ardb_sdcard_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig
index efdaaa3d69..f6ea06bfb0 100644
--- a/configs/ls1043ardb_sdcard_defconfig
+++ b/configs/ls1043ardb_sdcard_defconfig
@@ -3,7 +3,6 @@ CONFIG_TARGET_LS1043ARDB=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
CONFIG_SPL_MMC_SUPPORT=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
From 09c6778d9f5c85c40d8a81722c98142975c2a01e Mon Sep 17 00:00:00 2001
From: Yangbo Lu <yangbo.lu@nxp.com>
Date: Mon, 18 Sep 2017 14:58:49 +0800
Subject: [PATCH 12/12] armv8: ls1046ardb: disable PPA loading during SPL stage
for SD boot
PPA loading during SPL stage is not required for nornal
SD boot scenario.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
---
configs/ls1046ardb_sdcard_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig
index 600990ea60..1d7ed3b23a 100644
--- a/configs/ls1046ardb_sdcard_defconfig
+++ b/configs/ls1046ardb_sdcard_defconfig
@@ -1,7 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_LS1046ARDB=y
CONFIG_FSL_LS_PPA=y
-CONFIG_SPL_FSL_LS_PPA=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1046a-rdb"
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT_VERBOSE=y