leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'network_master' of https://source.denx.de/u-boot/custodians/u-boot-net into next

Browse Source 
- Fix some non-NULL terminated strings in the networking subsystem
- net: tsec: Mark tsec_get_interface as __maybe_unused
This commit is contained in:
Tom Rini
2021-09-29 07:58:20 -04:00
parent ba17871884 4df9f5e39f
commit 6eecaf5d0f
86 changed files with 277 additions and 255 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@@ -1147,7 +1147,7 @@ int arch_early_init_r(void)
#endif
#ifdef CONFIG_SYS_FSL_HAS_RGMII
/* some dpmacs in armv8a based freescale layerscape SOCs can be
* configured via both serdes(sgmii, xfi, xlaui etc) bits and via
* configured via both serdes(sgmii, 10gbase-r, xlaui etc) bits and via
* EC*_PMUX(rgmii) bits in RCW.
* e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
* serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits

8
arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc
View File

@@ -31,7 +31,7 @@ The LS1043A SoC includes the following function and features:
- Hardware buffer management for buffer allocation and de-allocation (BMan)
- Cryptography acceleration (SEC)
- Ethernet interfaces by FMan
- Up to 1 x XFI supporting 10G interface
- Up to 1 x 10GBase-R supporting 10G interface
- Up to 1 x QSGMII
- Up to 4 x SGMII supporting 1000Mbps
- Up to 2 x SGMII supporting 2500Mbps
@@ -190,7 +190,7 @@ The LS1046A SoC includes the following function and features:
- Two PLLs per four-lane SerDes
- Support for 10G operation
- Ethernet interfaces by FMan
- Up to 2 x XFI supporting 10G interface (MAC 9, 10)
- Up to 2 x 10GBase-R supporting 10G interface (MAC 9, 10)
- Up to 1 x QSGMII (MAC 5, 6, 10, 1)
- Up to 4 x SGMII supporting 1000Mbps (MAC 5, 6, 9, 10)
- Up to 3 x SGMII supporting 2500Mbps (MAC 5, 9, 10)
@@ -295,7 +295,7 @@ The LX2160A SoC includes the following function and features:
Single WRIOP tile supporting 130Gbps using 18 MACs
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
Support for XFI (and 10GBase-KR)
Support for 10GBase-R (and 10GBase-KR)
Support for CAUI4 (100G); CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.
@@ -400,7 +400,7 @@ The LX2162A SoC includes the following function and features:
Ethernet interfaces
Support for 10G-SXGMII (aka USXGMII).
Support for SGMII (and 1000Base-KX)
Support for XFI (and 10GBase-KR)
Support for 10GBase-R (and 10GBase-KR)
Support for CAUI2 (50G) and 25G-AUI(25G).
Support for XLAUI (and 40GBase-KR4) for 40G.
Support for two RGMII parallel interfaces.

2
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
View File

@@ -100,7 +100,7 @@ enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
return 0;
/*
* LS1044A/1048A support only one XFI port
* LS1044A/1048A support only one 10GBase-R port
* Disable MAC1 for LS1044A/1048A
*/
if (serdes == FSL_SRDS_1 && lane == 2) {

2
arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 1xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 6xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
@@ -14,6 +14,6 @@
&enetc0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};

10
arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
@@ -30,25 +30,25 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>;
};
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>;
};
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

6
arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7xx7
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot1 {
@@ -19,13 +19,13 @@
&mscc_felix_port0 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>;
};
&mscc_felix_port3 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>;
};

2
arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 8xxx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 9999
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*
*/

2
arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x3xx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW x5xx
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot2 {
@@ -19,7 +19,7 @@
&mscc_felix_port1 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>;
};

4
arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
View File

@@ -2,7 +2,7 @@
/*
* NXP LS1028A-QDS device tree fragment for RCW 7777
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
&slot3 {
@@ -19,7 +19,7 @@
&mscc_felix_port2 {
status = "okay";
phy-mode = "sgmii-2500";
phy-mode = "2500base-x";
phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>;
};

4
arch/arm/dts/fsl-ls1088a-qds-sd1-21.dtsi
View File

@@ -9,12 +9,12 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {

4
arch/arm/dts/fsl-ls1088a-qds-sd1-29.dtsi
View File

@@ -9,10 +9,10 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};

16
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
View File

@@ -9,40 +9,40 @@
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};

16
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
View File

@@ -24,49 +24,49 @@
&dpmac1 {
status = "okay";
phy-handle = <&mdio1_phy1>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac2 {
status = "okay";
phy-handle = <&mdio1_phy2>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac3 {
status = "okay";
phy-handle = <&mdio1_phy3>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac4 {
status = "okay";
phy-handle = <&mdio1_phy4>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac5 {
status = "okay";
phy-handle = <&mdio2_phy1>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac6 {
status = "okay";
phy-handle = <&mdio2_phy2>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac7 {
status = "okay";
phy-handle = <&mdio2_phy3>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&dpmac8 {
status = "okay";
phy-handle = <&mdio2_phy4>;
phy-connection-type = "xfi";
phy-connection-type = "10gbase-r";
};
&emdio1 {

2
arch/arm/dts/fsl-sch-24801.dtsi
View File

@@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-24801 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

2
arch/arm/dts/fsl-sch-28021.dtsi
View File

@@ -2,7 +2,7 @@
/*
* Device tree fragment for RCW SCH-28021 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*

4
arch/arm/dts/fsl-sch-30841.dtsi
View File

@@ -2,14 +2,14 @@
/*
* Device tree fragment for RCW SCH-30841 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
* SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
* It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
* together on a single lane or mapped 1:1 to serdes lanes.
* It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
* It supports several protocols - SGMII, 2500base-X, USXGMII, M-USX, 10GBase-R.
* PHY addresses are 0x00 - 0x03.
* On the card the first port is the bottom port (closest to PEX connector).
*/

4
arch/arm/dts/fsl-sch-30842.dtsi
View File

@@ -2,13 +2,13 @@
/*
* Device tree fragment for RCW SCH-30842 card
*
* Copyright 2019-2021 NXP Semiconductors
* Copyright 2019-2021 NXP
*/
/*
* SCH-30842 is a single port add-on card used with various FSL QDS boards.
* It integrates a AQR112 PHY, which supports several protocols - SGMII,
* SGMII-2500, USXGMII, XFI.
* 2500base-x, USXGMII, 10GBase-R.
* PHY address is 0x02.
*/
phy@02 {

2
arch/arm/dts/ls1021a-tsn.dts
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: GPL-2.0
/* Copyright 2016-2018 NXP Semiconductors
/* Copyright 2016-2018 NXP
* Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
*/