powerpc/b4860qds: Add LAW Target ID and Create LAW entry for Maple
Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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@ -70,6 +70,8 @@ enum law_trgt_if {
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LAW_TRGT_IF_DCSR = 0x1d,
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LAW_TRGT_IF_DCSR = 0x1d,
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LAW_TRGT_IF_LBC = 0x1f,
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LAW_TRGT_IF_LBC = 0x1f,
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LAW_TRGT_IF_QMAN = 0x3c,
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LAW_TRGT_IF_QMAN = 0x3c,
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LAW_TRGT_IF_MAPLE = 0x50,
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};
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};
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#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
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#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
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#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
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#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
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@ -33,6 +33,9 @@ struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
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SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
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#endif
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#endif
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SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
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SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
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#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
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SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
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#endif
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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#ifdef CONFIG_SYS_DCSRBAR_PHYS
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/* Limit DCSR to 32M to access NPC Trace Buffer */
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/* Limit DCSR to 32M to access NPC Trace Buffer */
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
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SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
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@ -526,6 +526,15 @@ unsigned long get_board_ddr_clk(void);
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_SPEED 10000000
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#define CONFIG_SF_DEFAULT_MODE 0
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#define CONFIG_SF_DEFAULT_MODE 0
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/*
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* MAPLE
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*/
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#ifdef CONFIG_PHYS_64BIT
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#define CONFIG_SYS_MAPLE_MEM_PHYS 0xFA0000000ull
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#else
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#define CONFIG_SYS_MAPLE_MEM_PHYS 0xA0000000
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#endif
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/*
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/*
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* General PCI
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* General PCI
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* Memory space is mapped 1-1, but I/O space must start from 0.
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* Memory space is mapped 1-1, but I/O space must start from 0.
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