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Merge all outstanding changes from the current next branch in now that
we have released.
This commit is contained in:
Tom Rini 2020-07-06 15:46:38 -04:00
commit 6e7d7aa2e2
845 changed files with 24753 additions and 28958 deletions
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16
.azure-pipelines.yml
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@ -226,6 +226,22 @@ jobs:
qemu_mips64el:
TEST_PY_BD: "qemu_mips64el"
TEST_PY_TEST_SPEC: "not sleep"
qemu_malta:
TEST_PY_BD: "malta"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_maltael:
TEST_PY_BD: "maltael"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64:
TEST_PY_BD: "malta64"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_malta64el:
TEST_PY_BD: "malta64el"
TEST_PY_ID: "--id qemu"
TEST_PY_TEST_SPEC: "not sleep and not efi"
qemu_ppce500:
TEST_PY_BD: "qemu-ppce500"
TEST_PY_TEST_SPEC: "not sleep"

32
.gitlab-ci.yml
View File

@ -276,6 +276,38 @@ qemu_mips64el test.py:
TEST_PY_TEST_SPEC: "not sleep"
<<: *buildman_and_testpy_dfn
qemu_malta test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_maltael test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "maltael"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64 test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta64"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu_malta64el test.py:
tags: [ 'all' ]
variables:
TEST_PY_BD: "malta64el"
TEST_PY_TEST_SPEC: "not sleep and not efi"
TEST_PY_ID: "--id qemu"
<<: *buildman_and_testpy_dfn
qemu-ppce500 test.py:
tags: [ 'all' ]
variables:

28
.travis.yml
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@ -573,6 +573,34 @@ matrix:
TEST_PY_TEST_SPEC="not sleep"
QEMU_TARGET="mips64el-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta"
env:
- TEST_PY_BD="malta"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-maltael"
env:
- TEST_PY_BD="maltael"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mipsel-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta64"
env:
- TEST_PY_BD="malta64"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips64-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-malta64el"
env:
- TEST_PY_BD="malta64el"
TEST_PY_TEST_SPEC="not sleep and not efi"
TEST_PY_ID="--id qemu"
QEMU_TARGET="mips64el-softmmu"
TOOLCHAIN="mips"
- name: "test/py qemu-ppce500"
env:
- TEST_PY_BD="qemu-ppce500"

62
Kconfig
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@ -5,6 +5,10 @@
#
mainmenu "U-Boot $(UBOOTVERSION) Configuration"
comment "Compiler: $(CC_VERSION_TEXT)"
source "scripts/Kconfig.include"
# Allow defaults in arch-specific code to override any given here
source "arch/Kconfig"
@ -62,6 +66,35 @@ config CC_OPTIMIZE_FOR_SIZE
This option is enabled by default for U-Boot.
config OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in full U-Boot"
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config SPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in SPL"
depends on SPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config TPL_OPTIMIZE_INLINING
bool "Allow compiler to uninline functions marked 'inline' in TPL"
depends on TPL
default n
help
This option determines if U-Boot forces gcc to inline the functions
developers have marked 'inline'. Doing so takes away freedom from gcc to
do what it thinks is best, which is desirable in some cases for size
reasons.
config CC_COVERAGE
bool "Enable code coverage analysis"
depends on SANDBOX
@ -69,6 +102,9 @@ config CC_COVERAGE
Enabling this option will pass "--coverage" to gcc to compile
and link code instrumented for coverage analysis.
config CC_HAS_ASM_INLINE
def_bool $(success,echo 'void foo(void) { asm inline (""); }' | $(CC) -x c - -c -o /dev/null)
config DISTRO_DEFAULTS
bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE
@ -358,12 +394,26 @@ config FIT_ENABLE_SHA256_SUPPORT
help
Enable this to support SHA256 checksum of FIT image contents. A
SHA256 checksum is a 256-bit (32-byte) hash value used to check that
the image contents have not been corrupted. SHA256 is recommended
for use in secure applications since (as at 2016) there is no known
feasible attack that could produce a 'collision' with differing
input data. Use this for the highest security. Note that only the
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
the image contents have not been corrupted.
config FIT_ENABLE_SHA384_SUPPORT
bool "Support SHA384 checksum of FIT image contents"
default n
select SHA384
help
Enable this to support SHA384 checksum of FIT image contents. A
SHA384 checksum is a 384-bit (48-byte) hash value used to check that
the image contents have not been corrupted. Use this for the highest
security.
config FIT_ENABLE_SHA512_SUPPORT
bool "Support SHA512 checksum of FIT image contents"
default n
select SHA512
help
Enable this to support SHA512 checksum of FIT image contents. A
SHA512 checksum is a 512-bit (64-byte) hash value used to check that
the image contents have not been corrupted.
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"

9
MAINTAINERS
View File

@ -633,6 +633,7 @@ F: include/pe.h
F: include/asm-generic/pe.h
F: lib/charset.c
F: lib/efi*/
F: test/lib/efi_*
F: test/py/tests/test_efi*
F: test/py/tests/test_efi*/
F: test/unicode_ut.c
@ -699,6 +700,7 @@ S: Maintained
T: git https://gitlab.denx.de/u-boot/u-boot.git
F: common/log*
F: cmd/log.c
F: doc/develop/logging.rst
F: test/log/
F: test/py/tests/test_log.py
@ -873,6 +875,13 @@ F: arch/riscv/
F: cmd/riscv/
F: tools/prelink-riscv.c
RISC-V KENDRYTE
M: Sean Anderson <seanga2@gmail.com>
S: Maintained
F: doc/device-tree-bindings/mfd/kendryte,k210-sysctl.txt
F: drivers/clk/kendryte/
F: include/kendryte/
RNG
M: Sughosh Ganu <sughosh.ganu@linaro.org>
R: Heinrich Schuchardt <xypron.glpk@gmx.de>

13
Makefile
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@ -683,6 +683,9 @@ KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# disable stringop warnings in gcc 8+
KBUILD_CFLAGS += $(call cc-disable-warning, stringop-truncation)
# Enabled with W=2, disabled by default as noisy
KBUILD_CFLAGS += $(call cc-disable-warning, maybe-uninitialized)
# change __FILE__ to the relative path from the srctree
KBUILD_CFLAGS += $(call cc-option,-fmacro-prefix-map=$(srctree)/=)
@ -887,7 +890,7 @@ ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
else
ifneq ($(CONFIG_SECURE_BOOT), y)
ifneq ($(CONFIG_NXP_ESBC), y)
# For Secure Boot The Image needs to be signed and Header must also
# be included. So The image has to be built explicitly
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot.pbl
@ -1025,7 +1028,7 @@ ifneq ($(CONFIG_DM),y)
@echo >&2 "===================================================="
endif
ifeq ($(CONFIG_MMC),y)
ifneq ($(CONFIG_DM_MMC)$(CONFIG_OF_CONTROL)$(CONFIG_BLK),yyy)
ifneq ($(CONFIG_DM_MMC)$(CONFIG_BLK),yy)
@echo >&2 "===================== WARNING ======================"
@echo >&2 "This board does not use CONFIG_DM_MMC. Please update"
@echo >&2 "the board to use CONFIG_DM_MMC before the v2019.04 release."
@ -1733,6 +1736,12 @@ u-boot-mtk.bin: u-boot.bin FORCE
$(call if_changed,mkimage)
endif
quiet_cmd_endian_swap = SWAP $@
cmd_endian_swap = $(srctree)/tools/endian-swap.py $< $@
u-boot-swap.bin: u-boot.bin FORCE
$(call if_changed,endian_swap)
ARCH_POSTLINK := $(wildcard $(srctree)/arch/$(ARCH)/Makefile.postlink)
# Rule to link u-boot

23
README
View File

@ -559,19 +559,6 @@ The following options need to be configured:
such as ARM architectural timer initialization.
- Linux Kernel Interface:
CONFIG_CLOCKS_IN_MHZ
U-Boot stores all clock information in Hz
internally. For binary compatibility with older Linux
kernels (which expect the clocks passed in the
bd_info data to be in MHz) the environment variable
"clocks_in_mhz" can be defined so that U-Boot
converts clock data to MHZ before passing it to the
Linux kernel.
When CONFIG_CLOCKS_IN_MHZ is defined, a definition of
"clocks_in_mhz=1" is automatically included in the
default environment.
CONFIG_MEMSIZE_IN_BYTES [relevant for MIPS only]
When transferring memsize parameter to Linux, some versions
@ -670,11 +657,6 @@ The following options need to be configured:
Define this variable to enable hw flow control in serial driver.
Current user of this option is drivers/serial/nsl16550.c driver
- Console Baudrate:
CONFIG_BAUDRATE - in bps
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- Autoboot Command:
CONFIG_BOOTCOMMAND
Only needed when CONFIG_BOOTDELAY is enabled;
@ -889,11 +871,6 @@ The following options need to be configured:
Allow generic access to the SPI bus on the Intel 8257x, for
example with the "sspi" command.
CONFIG_EEPRO100
Support for Intel 82557/82559/82559ER chips.
Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM
write routine for first time initialisation.
CONFIG_TULIP
Support for Digital 2114x chips.

21
arch/arm/Kconfig
View File

@ -549,6 +549,7 @@ config TARGET_GPLUGD
config ARCH_DAVINCI
bool "TI DaVinci"
select CPU_ARM926EJS
select SPL_DM_SPI if SPL
imply CMD_SAVES
help
Support for TI's DaVinci platform.
@ -566,6 +567,8 @@ config ARCH_MVEBU
select DM_SERIAL
select DM_SPI
select DM_SPI_FLASH
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select OF_CONTROL
select OF_SEPARATE
select SPI
@ -985,6 +988,8 @@ config ARCH_SOCFPGA
imply FAT_WRITE
imply SPL
imply SPL_DM
imply SPL_DM_SPI
imply SPL_DM_SPI_FLASH
imply SPL_LIBDISK_SUPPORT
imply SPL_MMC_SUPPORT
imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
@ -1093,6 +1098,8 @@ config ARCH_ZYNQ
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SPL_OF_CONTROL if SPL
select SPL_SEPARATE_BSS if SPL
select SUPPORT_SPL
@ -1131,6 +1138,8 @@ config ARCH_ZYNQMP
select OF_CONTROL
select SPL_BOARD_INIT if SPL
select SPL_CLK if SPL
select SPL_DM_SPI if SPI
select SPL_DM_SPI_FLASH if SPL_DM_SPI
select SPL_DM_MAILBOX if SPL
select SPL_FIRMWARE if SPL
select SPL_SEPARATE_BSS if SPL
@ -1447,6 +1456,8 @@ config TARGET_LS1021AQDS
select SUPPORT_SPL
select SYS_FSL_DDR
select FSL_DDR_INTERACTIVE
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
imply SCSI
config TARGET_LS1021ATWR
@ -1460,6 +1471,7 @@ config TARGET_LS1021ATWR
select CPU_V7_HAS_VIRT
select LS1_DEEP_SLEEP
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
config TARGET_LS1021ATSN
@ -1484,6 +1496,7 @@ config TARGET_LS1021AIOT
select CPU_V7_HAS_NONSEC
select CPU_V7_HAS_VIRT
select SUPPORT_SPL
select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
imply SCSI
help
Support for Freescale LS1021AIOT platform.
@ -1501,6 +1514,8 @@ config TARGET_LS1043AQDS
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DDR_INTERACTIVE if !SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
imply SCSI
imply SCSI_AHCI
help
@ -1515,6 +1530,8 @@ config TARGET_LS1043ARDB
select BOARD_EARLY_INIT_F
select BOARD_LATE_INIT
select SUPPORT_SPL
select FSL_DSPI if !SPL_NO_DSPI
select DM_SPI_FLASH if FSL_DSPI
help
Support for Freescale LS1043ARDB platform.
@ -1680,6 +1697,8 @@ config ARCH_ROCKCHIP
select OF_CONTROL
select SPI
select SPL_DM if SPL
select SPL_DM_SPI if SPL
select SPL_DM_SPI_FLASH if SPL
select SYS_MALLOC_F
select SYS_THUMB_BUILD if !ARM64
imply ADC
@ -1930,5 +1949,3 @@ config SPL_LDSCRIPT
default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64

12
arch/arm/dts/Makefile
View File

@ -280,6 +280,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
zynqmp-mini-emmc1.dtb \
zynqmp-mini-nand.dtb \
zynqmp-mini-qspi.dtb \
zynqmp-topic-miamimp-xilinx-xdp-v1r1.dtb \
zynqmp-zcu100-revC.dtb \
zynqmp-zcu102-revA.dtb \
zynqmp-zcu102-revB.dtb \
@ -848,6 +849,17 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \
dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \
omap3-igep0020.dtb
dtb-$(CONFIG_TARGET_OMAP4_PANDA) += \
omap4-panda.dtb \
omap4-panda-es.dtb
dtb-$(CONFIG_TARGET_OMAP4_SDP4430) += \
omap4-sdp.dtb \
omap4-sdp-es23plus.dtb
dtb-$(CONFIG_TARGET_OMAP5_UEVM) += \
omap5-uevm.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_PTC_EK) += \
at91-sama5d2_ptc_ek.dtb

68
arch/arm/dts/elpida_ecb240abacn.dtsi Normal file
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@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Common devices used in different OMAP boards
*/
/ {
elpida_ECB240ABACN: lpddr2 {
compatible = "Elpida,ECB240ABACN","jedec,lpddr2-s4";
density = <2048>;
io-width = <32>;
tRPab-min-tck = <3>;
tRCD-min-tck = <3>;
tWR-min-tck = <3>;
tRASmin-min-tck = <3>;
tRRD-min-tck = <2>;
tWTR-min-tck = <2>;
tXP-min-tck = <2>;
tRTP-min-tck = <2>;
tCKE-min-tck = <3>;
tCKESR-min-tck = <3>;
tFAW-min-tck = <8>;
timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <400000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <7500>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
compatible = "jedec,lpddr2-timings";
min-freq = <10000000>;
max-freq = <200000000>;
tRPab = <21000>;
tRCD = <18000>;
tWR = <15000>;
tRAS-min = <42000>;
tRRD = <10000>;
tWTR = <10000>;
tXP = <7500>;
tRTP = <7500>;
tCKESR = <15000>;
tDQSCK-max = <5500>;
tFAW = <50000>;
tZQCS = <90000>;
tZQCL = <360000>;
tZQinit = <1000000>;
tRAS-max-ns = <70000>;
tDQSCK-max-derated = <6000>;
};
};
};

488
arch/arm/dts/omap4-l4-abe.dtsi Normal file
View File

@ -0,0 +1,488 @@
&l4_abe { /* 0x40100000 */
compatible = "ti,omap4-l4-abe", "simple-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =
/* CPU to L4 ABE mapping */
<0x00000000 0x00000000 0x000400>, /* ap 0 */
<0x00000400 0x00000400 0x000400>, /* ap 1 */
<0x00022000 0x00022000 0x001000>, /* ap 2 */
<0x00023000 0x00023000 0x001000>, /* ap 3 */
<0x00024000 0x00024000 0x001000>, /* ap 4 */
<0x00025000 0x00025000 0x001000>, /* ap 5 */
<0x00026000 0x00026000 0x001000>, /* ap 6 */
<0x00027000 0x00027000 0x001000>, /* ap 7 */
<0x00028000 0x00028000 0x001000>, /* ap 8 */
<0x00029000 0x00029000 0x001000>, /* ap 9 */
<0x0002a000 0x0002a000 0x001000>, /* ap 10 */
<0x0002b000 0x0002b000 0x001000>, /* ap 11 */
<0x0002e000 0x0002e000 0x001000>, /* ap 12 */
<0x0002f000 0x0002f000 0x001000>, /* ap 13 */
<0x00030000 0x00030000 0x001000>, /* ap 14 */
<0x00031000 0x00031000 0x001000>, /* ap 15 */
<0x00032000 0x00032000 0x001000>, /* ap 16 */
<0x00033000 0x00033000 0x001000>, /* ap 17 */
<0x00038000 0x00038000 0x001000>, /* ap 18 */
<0x00039000 0x00039000 0x001000>, /* ap 19 */
<0x0003a000 0x0003a000 0x001000>, /* ap 20 */
<0x0003b000 0x0003b000 0x001000>, /* ap 21 */
<0x0003c000 0x0003c000 0x001000>, /* ap 22 */
<0x0003d000 0x0003d000 0x001000>, /* ap 23 */
<0x0003e000 0x0003e000 0x001000>, /* ap 24 */
<0x0003f000 0x0003f000 0x001000>, /* ap 25 */
<0x00080000 0x00080000 0x010000>, /* ap 26 */
<0x00080000 0x00080000 0x001000>, /* ap 27 */
<0x000a0000 0x000a0000 0x010000>, /* ap 28 */
<0x000a0000 0x000a0000 0x001000>, /* ap 29 */
<0x000c0000 0x000c0000 0x010000>, /* ap 30 */
<0x000c0000 0x000c0000 0x001000>, /* ap 31 */
<0x000f1000 0x000f1000 0x001000>, /* ap 32 */
<0x000f2000 0x000f2000 0x001000>, /* ap 33 */
/* L3 to L4 ABE mapping */
<0x49000000 0x49000000 0x000400>, /* ap 0 */
<0x49000400 0x49000400 0x000400>, /* ap 1 */
<0x49022000 0x49022000 0x001000>, /* ap 2 */
<0x49023000 0x49023000 0x001000>, /* ap 3 */
<0x49024000 0x49024000 0x001000>, /* ap 4 */
<0x49025000 0x49025000 0x001000>, /* ap 5 */
<0x49026000 0x49026000 0x001000>, /* ap 6 */
<0x49027000 0x49027000 0x001000>, /* ap 7 */
<0x49028000 0x49028000 0x001000>, /* ap 8 */
<0x49029000 0x49029000 0x001000>, /* ap 9 */
<0x4902a000 0x4902a000 0x001000>, /* ap 10 */
<0x4902b000 0x4902b000 0x001000>, /* ap 11 */
<0x4902e000 0x4902e000 0x001000>, /* ap 12 */
<0x4902f000 0x4902f000 0x001000>, /* ap 13 */
<0x49030000 0x49030000 0x001000>, /* ap 14 */
<0x49031000 0x49031000 0x001000>, /* ap 15 */
<0x49032000 0x49032000 0x001000>, /* ap 16 */
<0x49033000 0x49033000 0x001000>, /* ap 17 */
<0x49038000 0x49038000 0x001000>, /* ap 18 */
<0x49039000 0x49039000 0x001000>, /* ap 19 */
<0x4903a000 0x4903a000 0x001000>, /* ap 20 */
<0x4903b000 0x4903b000 0x001000>, /* ap 21 */
<0x4903c000 0x4903c000 0x001000>, /* ap 22 */
<0x4903d000 0x4903d000 0x001000>, /* ap 23 */
<0x4903e000 0x4903e000 0x001000>, /* ap 24 */
<0x4903f000 0x4903f000 0x001000>, /* ap 25 */
<0x49080000 0x49080000 0x010000>, /* ap 26 */
<0x49080000 0x49080000 0x001000>, /* ap 27 */
<0x490a0000 0x490a0000 0x010000>, /* ap 28 */
<0x490a0000 0x490a0000 0x001000>, /* ap 29 */
<0x490c0000 0x490c0000 0x010000>, /* ap 30 */
<0x490c0000 0x490c0000 0x001000>, /* ap 31 */
<0x490f1000 0x490f1000 0x001000>, /* ap 32 */
<0x490f2000 0x490f2000 0x001000>; /* ap 33 */
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x22000 0x1000>,
<0x49022000 0x49022000 0x1000>;
mcbsp1: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x24000 0x1000>,
<0x49024000 0x49024000 0x1000>;
mcbsp2: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCBSP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x1000>,
<0x49026000 0x49026000 0x1000>;
mcbsp3: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@28000 { /* 0x40128000, ap 8 08.0 */
compatible = "ti,sysc-mcasp", "ti,sysc";
reg = <0x28000 0x4>,
<0x28004 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCASP_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x28000 0x1000>,
<0x49028000 0x49028000 0x1000>;
/*
* Child device unsupported by davinci-mcasp. At least
* RX path is disabled for omap4, and only DIT mode
* works with no I2S. See also old Android kernel
* omap-mcasp driver for more information.
*/
};
target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2a000 0x1000>,
<0x4902a000 0x4902a000 0x1000>;
};
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_DMIC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2e000 0x1000>,
<0x4902e000 0x4902e000 0x1000>;
dmic: dmic@0 {
compatible = "ti,omap4-dmic";
reg = <0x0 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 67>;
dma-names = "up_link";
status = "disabled";
};
};
target-module@30000 { /* 0x40130000, ap 14 0e.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x30000 0x4>,
<0x30010 0x4>,
<0x30014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_EMUFREE |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_WD_TIMER3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x30000 0x1000>,
<0x49030000 0x49030000 0x1000>;
wdt3: wdt@0 {
compatible = "ti,omap4-wdt", "ti,omap3-wdt";
reg = <0x0 0x80>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
};
};
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_MCPDM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x32000 0x1000>,
<0x49032000 0x49032000 0x1000>;
/* Must be only enabled for boards with pdmclk wired */
status = "disabled";
mcpdm: mcpdm@0 {
compatible = "ti,omap4-mcpdm";
reg = <0x0 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
};
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x38000 0x1000>,
<0x49038000 0x49038000 0x1000>;
timer5: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x49038000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER5_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3a000 0x1000>,
<0x4903a000 0x4903a000 0x1000>;
timer6: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903a000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER6_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3c000 0x1000>,
<0x4903c000 0x4903c000 0x1000>;
timer7: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903c000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER7_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3e000 0x1000>,
<0x4903e000 0x4903e000 0x1000>;
timer8: timer@0 {
compatible = "ti,omap4430-timer";
reg = <0x00000000 0x80>,
<0x4903e000 0x80>;
clocks = <&abe_clkctrl OMAP4_TIMER8_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-pwm;
ti,timer-dsp;
};
};
target-module@80000 { /* 0x40180000, ap 26 1a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x10000>,
<0x49080000 0x49080000 0x10000>;
};
target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xa0000 0x10000>,
<0x490a0000 0x490a0000 0x10000>;
};
target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc0000 0x10000>,
<0x490c0000 0x490c0000 0x10000>;
};
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf1000 0x1000>,
<0x490f1000 0x490f1000 0x1000>;
/*
* No child device binding or driver in mainline.
* See Android tree and related upstreaming efforts
* for the old driver.
*/
};
};
};

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// SPDX-License-Identifier: GPL-2.0
/*
* Common omap4 mcpdm configuration
*
* Only include this file if your board has pdmclk wired from the
* pmic to ABE as mcpdm uses an external clock for the module.
*/
&omap4_pmx_core {
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
/* 0x4a100106 abe_pdm_ul_data.abe_pdm_ul_data ag25 */
OMAP4_IOPAD(0x106, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a100108 abe_pdm_dl_data.abe_pdm_dl_data af25 */
OMAP4_IOPAD(0x108, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a10010a abe_pdm_frame.abe_pdm_frame ae25 */
OMAP4_IOPAD(0x10a, PIN_INPUT_PULLUP | MUX_MODE0)
/* 0x4a10010c abe_pdm_lb_clk.abe_pdm_lb_clk af26 */
OMAP4_IOPAD(0x10c, PIN_INPUT_PULLDOWN | MUX_MODE0)
/* 0x4a10010e abe_clks.abe_clks ah26 */
OMAP4_IOPAD(0x10e, PIN_INPUT_PULLDOWN | MUX_MODE0)
>;
};
};
&mcpdm_module {
/*
* McPDM pads must be muxed at the interconnect target module
* level as the module on the SoC needs external clock from
* the PMIC
*/
pinctrl-names = "default";
pinctrl-0 = <&mcpdm_pins>;
status = "okay";
};
&mcpdm {
clocks = <&twl6040>;
clock-names = "pdmclk";
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011-2013 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/input/input.h>
#include "elpida_ecb240abacn.dtsi"
#include "omap4-mcpdm.dtsi"
/ {
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
chosen {
stdout-path = &uart3;
};
aliases {
display0 = &dvi0;
display1 = &hdmi0;
ethernet = &ethernet;
};
leds: leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <
&led_wkgpio_pins
>;
heartbeat {
label = "pandaboard::status1";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
mmc {
label = "pandaboard::status2";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
};
};
gpio_keys: gpio_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <
&button_pins
>;
buttonS2 {
label = "button S2";
gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; /* gpio_121 */
linux,code = <BTN_0>;
wakeup-source;
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "PandaBoard";
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
/* HS USB Port 1 Power */
hsusb1_power: hsusb1_power_reg {
compatible = "regulator-fixed";
regulator-name = "hsusb1_vbus";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; /* gpio_1 */
startup-delay-us = <70000>;
enable-active-high;
/*
* boot-on is required along with always-on as the
* regulator framework doesn't enable the regulator
* if boot-on is not there.
*/
regulator-always-on;
regulator-boot-on;
};
/* HS USB Host PHY on PORT 1 */
hsusb1_phy: hsusb1_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
#phy-cells = <0>;
vcc-supply = <&hsusb1_power>;
clocks = <&auxclk3_ck>;
clock-names = "main_clk";
clock-frequency = <19200000>;
};
/* regulator for wl12xx on sdio5 */
wl12xx_vmmc: wl12xx_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
tfp410: encoder0 {
compatible = "ti,tfp410";
powerdown-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; /* gpio_0 */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tfp410_in: endpoint {
remote-endpoint = <&dpi_out>;
};
};
port@1 {
reg = <1>;
tfp410_out: endpoint {
remote-endpoint = <&dvi_connector_in>;
};
};
};
};
dvi0: connector0 {
compatible = "dvi-connector";
label = "dvi";
digital;
ddc-i2c-bus = <&i2c3>;
port {
dvi_connector_in: endpoint {
remote-endpoint = <&tfp410_out>;
};
};
};
tpd12s015: encoder1 {
compatible = "ti,tpd12s015";
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
<&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
<&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector1 {
compatible = "hdmi-connector";
label = "hdmi";
type = "a";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&dss_dpi_pins
&tfp410_pins
&dss_hdmi_pins
&tpd12s015_pins
&hsusbb1_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
>;
};
dss_dpi_pins: pinmux_dss_dpi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x162, PIN_OUTPUT | MUX_MODE5) /* dispc2_data23 */
OMAP4_IOPAD(0x164, PIN_OUTPUT | MUX_MODE5) /* dispc2_data22 */
OMAP4_IOPAD(0x166, PIN_OUTPUT | MUX_MODE5) /* dispc2_data21 */
OMAP4_IOPAD(0x168, PIN_OUTPUT | MUX_MODE5) /* dispc2_data20 */
OMAP4_IOPAD(0x16a, PIN_OUTPUT | MUX_MODE5) /* dispc2_data19 */
OMAP4_IOPAD(0x16c, PIN_OUTPUT | MUX_MODE5) /* dispc2_data18 */
OMAP4_IOPAD(0x16e, PIN_OUTPUT | MUX_MODE5) /* dispc2_data15 */
OMAP4_IOPAD(0x170, PIN_OUTPUT | MUX_MODE5) /* dispc2_data14 */
OMAP4_IOPAD(0x172, PIN_OUTPUT | MUX_MODE5) /* dispc2_data13 */
OMAP4_IOPAD(0x174, PIN_OUTPUT | MUX_MODE5) /* dispc2_data12 */
OMAP4_IOPAD(0x176, PIN_OUTPUT | MUX_MODE5) /* dispc2_data11 */
OMAP4_IOPAD(0x1b4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data10 */
OMAP4_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data9 */
OMAP4_IOPAD(0x1b8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data16 */
OMAP4_IOPAD(0x1ba, PIN_OUTPUT | MUX_MODE5) /* dispc2_data17 */
OMAP4_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE5) /* dispc2_hsync */
OMAP4_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE5) /* dispc2_pclk */
OMAP4_IOPAD(0x1c0, PIN_OUTPUT | MUX_MODE5) /* dispc2_vsync */
OMAP4_IOPAD(0x1c2, PIN_OUTPUT | MUX_MODE5) /* dispc2_de */
OMAP4_IOPAD(0x1c4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data8 */
OMAP4_IOPAD(0x1c6, PIN_OUTPUT | MUX_MODE5) /* dispc2_data7 */
OMAP4_IOPAD(0x1c8, PIN_OUTPUT | MUX_MODE5) /* dispc2_data6 */
OMAP4_IOPAD(0x1ca, PIN_OUTPUT | MUX_MODE5) /* dispc2_data5 */
OMAP4_IOPAD(0x1cc, PIN_OUTPUT | MUX_MODE5) /* dispc2_data4 */
OMAP4_IOPAD(0x1ce, PIN_OUTPUT | MUX_MODE5) /* dispc2_data3 */
OMAP4_IOPAD(0x1d0, PIN_OUTPUT | MUX_MODE5) /* dispc2_data2 */
OMAP4_IOPAD(0x1d2, PIN_OUTPUT | MUX_MODE5) /* dispc2_data1 */
OMAP4_IOPAD(0x1d4, PIN_OUTPUT | MUX_MODE5) /* dispc2_data0 */
>;
};
tfp410_pins: pinmux_tfp410_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x184, PIN_OUTPUT | MUX_MODE3) /* gpio_0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
>;
};
hsusbb1_pins: pinmux_hsusbb1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0c2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_clk.usbb1_ulpiphy_clk */
OMAP4_IOPAD(0x0c4, PIN_OUTPUT | MUX_MODE4) /* usbb1_ulpitll_stp.usbb1_ulpiphy_stp */
OMAP4_IOPAD(0x0c6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dir.usbb1_ulpiphy_dir */
OMAP4_IOPAD(0x0c8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_nxt.usbb1_ulpiphy_nxt */
OMAP4_IOPAD(0x0ca, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat0.usbb1_ulpiphy_dat0 */
OMAP4_IOPAD(0x0cc, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat1.usbb1_ulpiphy_dat1 */
OMAP4_IOPAD(0x0ce, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat2.usbb1_ulpiphy_dat2 */
OMAP4_IOPAD(0x0d0, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat3.usbb1_ulpiphy_dat3 */
OMAP4_IOPAD(0x0d2, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat4.usbb1_ulpiphy_dat4 */
OMAP4_IOPAD(0x0d4, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat5.usbb1_ulpiphy_dat5 */
OMAP4_IOPAD(0x0d6, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat6.usbb1_ulpiphy_dat6 */
OMAP4_IOPAD(0x0d8, PIN_INPUT_PULLDOWN | MUX_MODE4) /* usbb1_ulpitll_dat7.usbb1_ulpiphy_dat7 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
/*
* wl12xx GPIO outputs for WLAN_EN, BT_EN, FM_EN, BT_WAKEUP
* REVISIT: Are the pull-ups needed for GPIO 48 and 49?
*/
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x066, PIN_OUTPUT | MUX_MODE3) /* gpmc_a19.gpio_43 */
OMAP4_IOPAD(0x06c, PIN_OUTPUT | MUX_MODE3) /* gpmc_a22.gpio_46 */
OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a24.gpio_48 */
OMAP4_IOPAD(0x072, PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_a25.gpio_49 */
>;
};
/* wl12xx GPIO inputs and SDIO pins */
wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x078, PIN_INPUT | MUX_MODE3) /* gpmc_ncs2.gpio_52 */
OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>;
};
button_pins: pinmux_button_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x114, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_121 */
>;
};
};
&omap4_pmx_wkup {
led_wkgpio_pins: pinmux_leds_wkpins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE3) /* gpio_wk7 */
OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* IRQ# = 7 */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
};
twl6040: twl@4b {
compatible = "ti,twl6040";
#clock-cells = <0>;
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
/* IRQ# = 119 */
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
};
};
#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <100000>;
/*
* Display monitor features are burnt in their EEPROM as EDID data.
* The EEPROM is connected as I2C slave device.
*/
eeprom@50 {
compatible = "ti,eeprom";
reg = <0x50>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
status = "disabled";
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
interrupts-extended = <&wakeupgen GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core 0x10e>;
non-removable;
bus-width = <4>;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
/* gpio_53 with gpmc_ncs3 pad as wakeup */
interrupts-extended = <&gpio2 21 IRQ_TYPE_LEVEL_HIGH>,
<&omap4_pmx_core 0x3a>;
interrupt-names = "irq", "wakeup";
ref-clock-frequency = <38400000>;
};
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&uart2 {
interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART2_RX>;
};
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
};
&uart4 {
interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART4_RX>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
&usbhshost {
port1-mode = "ehci-phy";
};
&usbhsehci {
phys = <&hsusb1_phy>;
#address-cells = <1>;
#size-cells = <0>;
hub@1 {
compatible = "usb424,9514";
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
ethernet: usbether@1 {
compatible = "usb424,ec00";
reg = <1>;
};
};
};
&dss {
status = "ok";
port {
dpi_out: endpoint {
remote-endpoint = <&tfp410_in>;
data-lines = <24>;
};
};
};
&dsi2 {
status = "ok";
vdd-supply = <&vcxio>;
};
&hdmi {
status = "ok";
vdda-supply = <&vdac>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "omap4460.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard-ES";
compatible = "ti,omap4-panda-es", "ti,omap4-panda", "ti,omap4460", "ti,omap4430", "ti,omap4";
};
/* Audio routing is differnet between PandaBoard4430 and PandaBoardES */
&sound {
ti,model = "PandaBoardES";
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"AFML", "Line In",
"AFMR", "Line In";
};
/* PandaboardES has external pullups on SCL & SDA */
&dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
&omap4_pmx_core {
led_gpio_pins: gpio_led_pmx {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0f6, PIN_OUTPUT | MUX_MODE3) /* gpio_110 */
>;
};
button_pins: pinmux_button_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x11b, PIN_INPUT_PULLUP | MUX_MODE3) /* gpio_113 */
>;
};
};
&led_wkgpio_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x05c, PIN_OUTPUT | MUX_MODE3) /* gpio_wk8 */
>;
};
&leds {
pinctrl-0 = <
&led_gpio_pins
&led_wkgpio_pins
>;
heartbeat {
gpios = <&gpio4 14 GPIO_ACTIVE_HIGH>;
};
mmc {
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
};
&gpio_keys {
buttonS2 {
gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; /* gpio_113 */
};
};
&gpio1_target {
ti,no-reset-on-init;
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "omap443x.dtsi"
#include "omap4-panda-common.dtsi"
/ {
model = "TI OMAP4 PandaBoard";
compatible = "ti,omap4-panda", "ti,omap4430", "ti,omap4";
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap4-sdp.dts"
/* SDP boards with 4430 ES2.3+ or 4460 have external pullups on SCL & SDA */
&dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "omap443x.dtsi"
#include "elpida_ecb240abacn.dtsi"
#include "omap4-mcpdm.dtsi"
/ {
model = "TI OMAP4 SDP board";
compatible = "ti,omap4-sdp", "ti,omap4430", "ti,omap4";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x40000000>; /* 1 GB */
};
aliases {
display0 = &lcd0;
display1 = &lcd1;
display2 = &hdmi0;
};
vdd_eth: fixedregulator-vdd-eth {
pinctrl-names = "default";
pinctrl-0 = <&enet_enable_gpio>;
compatible = "regulator-fixed";
regulator-name = "VDD_ETH";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 16 GPIO_ACTIVE_HIGH>; /* gpio line 48 */
enable-active-high;
regulator-boot-on;
startup-delay-us = <25000>;
};
vbat: fixedregulator-vbat {
compatible = "regulator-fixed";
regulator-name = "VBAT";
regulator-min-microvolt = <3750000>;
regulator-max-microvolt = <3750000>;
regulator-boot-on;
};
leds {
compatible = "gpio-leds";
debug0 {
label = "omap4:green:debug0";
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; /* 61 */
};
debug1 {
label = "omap4:green:debug1";
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; /* 30 */
};
debug2 {
label = "omap4:green:debug2";
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; /* 7 */
};
debug3 {
label = "omap4:green:debug3";
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; /* 8 */
};
debug4 {
label = "omap4:green:debug4";
gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>; /* 50 */
};
user1 {
label = "omap4:blue:user";
gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* 169 */
};
user2 {
label = "omap4:red:user";
gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; /* 170 */
};
user3 {
label = "omap4:green:user";
gpios = <&gpio5 11 GPIO_ACTIVE_HIGH>; /* 139 */
};
};
pwmleds {
compatible = "pwm-leds";
kpad {
label = "omap4::keypad";
pwms = <&twl_pwm 0 7812500>;
max-brightness = <127>;
};
charging {
label = "omap4:green:chrg";
pwms = <&twl_pwmled 0 7812500>;
max-brightness = <255>;
};
};
backlight {
compatible = "pwm-backlight";
pwms = <&twl_pwm 1 7812500>;
brightness-levels = <
0 10 20 30 40
50 60 70 80 90
100 110 120 127
>;
default-brightness-level = <13>;
};
sound {
compatible = "ti,abe-twl6040";
ti,model = "SDP4430";
ti,jack-detection = <1>;
ti,mclk-freq = <38400000>;
ti,mcpdm = <&mcpdm>;
ti,dmic = <&dmic>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Earphone Spk", "EP",
"Ext Spk", "HFL",
"Ext Spk", "HFR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"Vibrator", "VIBRAL",
"Vibrator", "VIBRAR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"MAINMIC", "Main Handset Mic",
"Main Handset Mic", "Main Mic Bias",
"SUBMIC", "Sub Handset Mic",
"Sub Handset Mic", "Main Mic Bias",
"AFML", "Line In",
"AFMR", "Line In",
"DMic", "Digital Mic",
"Digital Mic", "Digital Mic1 Bias";
};
/* regulator for wl12xx on sdio5 */
wl12xx_vmmc: wl12xx_vmmc {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_gpio>;
compatible = "regulator-fixed";
regulator-name = "vwl1271";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio2 22 GPIO_ACTIVE_HIGH>;
startup-delay-us = <70000>;
enable-active-high;
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>, /* 60, CT CP HPD */
<&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
<&gpio2 31 GPIO_ACTIVE_HIGH>; /* 63, HPD */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "c";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
};
&omap4_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&dss_hdmi_pins
&tpd12s015_pins
>;
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x118, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_cts.uart2_cts */
OMAP4_IOPAD(0x11a, PIN_OUTPUT | MUX_MODE0) /* uart2_rts.uart2_rts */
OMAP4_IOPAD(0x11c, PIN_INPUT_PULLUP | MUX_MODE0) /* uart2_rx.uart2_rx */
OMAP4_IOPAD(0x11e, PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x140, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_cts_rctx.uart3_cts_rctx */
OMAP4_IOPAD(0x142, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_sd.uart3_rts_sd */
OMAP4_IOPAD(0x144, PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
OMAP4_IOPAD(0x146, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */
>;
};
uart4_pins: pinmux_uart4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x15c, PIN_INPUT | MUX_MODE0) /* uart4_rx.uart4_rx */
OMAP4_IOPAD(0x15e, PIN_OUTPUT | MUX_MODE0) /* uart4_tx.uart4_tx */
>;
};
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x120, PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
OMAP4_IOPAD(0x1a0, PIN_INPUT | MUX_MODE0) /* sys_nirq2.sys_nirq2 */
>;
};
dmic_pins: pinmux_dmic_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x110, PIN_OUTPUT | MUX_MODE0) /* abe_dmic_clk1.abe_dmic_clk1 */
OMAP4_IOPAD(0x112, PIN_INPUT | MUX_MODE0) /* abe_dmic_din1.abe_dmic_din1 */
OMAP4_IOPAD(0x114, PIN_INPUT | MUX_MODE0) /* abe_dmic_din2.abe_dmic_din2 */
OMAP4_IOPAD(0x116, PIN_INPUT | MUX_MODE0) /* abe_dmic_din3.abe_dmic_din3 */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_clkx.abe_mcbsp1_clkx */
OMAP4_IOPAD(0x100, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dr.abe_mcbsp1_dr */
OMAP4_IOPAD(0x102, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp1_dx.abe_mcbsp1_dx */
OMAP4_IOPAD(0x104, PIN_INPUT | MUX_MODE0) /* abe_mcbsp1_fsx.abe_mcbsp1_fsx */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x0f6, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_clkx.abe_mcbsp2_clkx */
OMAP4_IOPAD(0x0f8, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dr.abe_mcbsp2_dr */
OMAP4_IOPAD(0x0fa, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abe_mcbsp2_dx.abe_mcbsp2_dx */
OMAP4_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* abe_mcbsp2_fsx.abe_mcbsp2_fsx */
>;
};
mcspi1_pins: pinmux_mcspi1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x132, PIN_INPUT | MUX_MODE0) /* mcspi1_clk.mcspi1_clk */
OMAP4_IOPAD(0x134, PIN_INPUT | MUX_MODE0) /* mcspi1_somi.mcspi1_somi */
OMAP4_IOPAD(0x136, PIN_INPUT | MUX_MODE0) /* mcspi1_simo.mcspi1_simo */
OMAP4_IOPAD(0x138, PIN_INPUT | MUX_MODE0) /* mcspi1_cs0.mcspi1_cs0 */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x09a, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP4_IOPAD(0x09c, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_scl.hdmi_scl */
OMAP4_IOPAD(0x09e, PIN_INPUT_PULLUP | MUX_MODE0) /* hdmi_sda.hdmi_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x062, PIN_OUTPUT | MUX_MODE3) /* gpmc_a17.gpio_41 */
OMAP4_IOPAD(0x088, PIN_OUTPUT | MUX_MODE3) /* gpmc_nbe1.gpio_60 */
OMAP4_IOPAD(0x098, PIN_INPUT_PULLDOWN | MUX_MODE3) /* hdmi_hpd.gpio_63 */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x122, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP4_IOPAD(0x124, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
i2c2_pins: pinmux_i2c2_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x126, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_scl */
OMAP4_IOPAD(0x128, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c2_sda */
>;
};
i2c3_pins: pinmux_i2c3_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12a, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_scl */
OMAP4_IOPAD(0x12c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c3_sda */
>;
};
i2c4_pins: pinmux_i2c4_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x12e, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_scl */
OMAP4_IOPAD(0x130, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c4_sda */
>;
};
/* wl12xx GPIO output for WLAN_EN */
wl12xx_gpio: pinmux_wl12xx_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x07c, PIN_OUTPUT | MUX_MODE3) /* gpmc_nwp.gpio_54 */
>;
};
/* wl12xx GPIO inputs and SDIO pins */
wl12xx_pins: pinmux_wl12xx_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x07a, PIN_INPUT | MUX_MODE3) /* gpmc_ncs3.gpio_53 */
OMAP4_IOPAD(0x148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_clk.sdmmc5_clk */
OMAP4_IOPAD(0x14a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_cmd.sdmmc5_cmd */
OMAP4_IOPAD(0x14c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat0.sdmmc5_dat0 */
OMAP4_IOPAD(0x14e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat1.sdmmc5_dat1 */
OMAP4_IOPAD(0x150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat2.sdmmc5_dat2 */
OMAP4_IOPAD(0x152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc5_dat3.sdmmc5_dat3 */
>;
};
/* gpio_48 for ENET_ENABLE */
enet_enable_gpio: pinmux_enet_enable_gpio {
pinctrl-single,pins = <
OMAP4_IOPAD(0x070, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* gpmc_a24.gpio_48 */
>;
};
ks8851_pins: pinmux_ks8851_pins {
pinctrl-single,pins = <
/* ENET_INT */
OMAP4_IOPAD(0x054, PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ad10.gpio_34 */
/*
* Misterious pin which makes the ethernet working
* The legacy board file requested this pin on boot
* (ETH_KS8851_QUART) and set it to high, similarly to
* the ENET_ENABLE pin.
* We could use gpio-hog to keep it high, but let's use
* it as a reset GPIO for ks8851.
*/
OMAP4_IOPAD(0x13a, PIN_OUTPUT_PULLUP | MUX_MODE3) /* mcspi1_cs1.gpio_138 */
>;
};
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
twl: twl@48 {
reg = <0x48>;
/* SPI = 0, IRQ# = 7, 4 = active high level-sensitive */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_1N cascaded to gic */
};
twl6040: twl@4b {
compatible = "ti,twl6040";
#clock-cells = <0>;
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
/* SPI = 0, IRQ# = 119, 4 = active high level-sensitive */
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; /* IRQ_SYS_2N cascaded to gic */
ti,audpwron-gpio = <&gpio4 31 GPIO_ACTIVE_HIGH>; /* gpio line 127 */
vio-supply = <&v1v8>;
v2v1-supply = <&v2v1>;
enable-active-high;
/* regulators for vibra motor */
vddvibl-supply = <&vbat>;
vddvibr-supply = <&vbat>;
vibra {
/* Vibra driver, motor resistance parameters */
ti,vibldrv-res = <8>;
ti,vibrdrv-res = <3>;
ti,viblmotor-res = <10>;
ti,vibrmotor-res = <10>;
};
};
};
#include "twl6030.dtsi"
#include "twl6030_omap4.dtsi"
&i2c2 {
pinctrl-names = "default";
pinctrl-0 = <&i2c2_pins>;
clock-frequency = <400000>;
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&i2c3_pins>;
clock-frequency = <400000>;
/*
* Temperature Sensor
* http://www.ti.com/lit/ds/symlink/tmp105.pdf
*/
tmp105@48 {
compatible = "ti,tmp105";
reg = <0x48>;
};
/*
* Ambient Light Sensor
* http://www.rohm.com/products/databook/sensor/pdf/bh1780gli-e.pdf
*/
bh1780@29 {
compatible = "rohm,bh1780";
reg = <0x29>;
};
};
&i2c4 {
pinctrl-names = "default";
pinctrl-0 = <&i2c4_pins>;
clock-frequency = <400000>;
/*
* 3-Axis Digital Compass
* http://www.sparkfun.com/datasheets/Sensors/Magneto/HMC5843.pdf
*/
hmc5843@1e {
compatible = "honeywell,hmc5843";
reg = <0x1e>;
};
};
&mcspi1 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi1_pins>;
eth@0 {
pinctrl-names = "default";
pinctrl-0 = <&ks8851_pins>;
compatible = "ks8851";
spi-max-frequency = <24000000>;
reg = <0>;
interrupt-parent = <&gpio2>;
interrupts = <2 IRQ_TYPE_LEVEL_LOW>; /* gpio line 34 */
vdd-supply = <&vdd_eth>;
reset-gpios = <&gpio5 10 GPIO_ACTIVE_HIGH>;
};
};
&mmc1 {
vmmc-supply = <&vmmc>;
bus-width = <8>;
};
&mmc2 {
vmmc-supply = <&vaux1>;
bus-width = <8>;
ti,non-removable;
};
&mmc3 {
status = "disabled";
};
&mmc4 {
status = "disabled";
};
&mmc5 {
pinctrl-names = "default";
pinctrl-0 = <&wl12xx_pins>;
vmmc-supply = <&wl12xx_vmmc>;
non-removable;
bus-width = <4>;
cap-power-off-card;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1281";
reg = <2>;
interrupt-parent = <&gpio1>;
interrupts = <21 IRQ_TYPE_LEVEL_HIGH>; /* gpio 53 */
ref-clock-frequency = <26000000>;
tcxo-clock-frequency = <26000000>;
};
};
&emif1 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&emif2 {
cs1-used;
device-handle = <&elpida_ECB240ABACN>;
};
&keypad {
keypad,num-rows = <8>;
keypad,num-columns = <8>;
linux,keymap = <0x00000012 /* KEY_E */
0x00010013 /* KEY_R */
0x00020014 /* KEY_T */
0x00030066 /* KEY_HOME */
0x0004003f /* KEY_F5 */
0x000500f0 /* KEY_UNKNOWN */
0x00060017 /* KEY_I */
0x0007002a /* KEY_LEFTSHIFT */
0x01000020 /* KEY_D*/
0x01010021 /* KEY_F */
0x01020022 /* KEY_G */
0x010300e7 /* KEY_SEND */
0x01040040 /* KEY_F6 */
0x010500f0 /* KEY_UNKNOWN */
0x01060025 /* KEY_K */
0x0107001c /* KEY_ENTER */
0x0200002d /* KEY_X */
0x0201002e /* KEY_C */
0x0202002f /* KEY_V */
0x0203006b /* KEY_END */
0x02040041 /* KEY_F7 */
0x020500f0 /* KEY_UNKNOWN */
0x02060034 /* KEY_DOT */
0x0207003a /* KEY_CAPSLOCK */
0x0300002c /* KEY_Z */
0x0301004e /* KEY_KPLUS */
0x03020030 /* KEY_B */
0x0303003b /* KEY_F1 */
0x03040042 /* KEY_F8 */
0x030500f0 /* KEY_UNKNOWN */
0x03060018 /* KEY_O */
0x03070039 /* KEY_SPACE */
0x04000011 /* KEY_W */
0x04010015 /* KEY_Y */
0x04020016 /* KEY_U */
0x0403003c /* KEY_F2 */
0x04040073 /* KEY_VOLUMEUP */
0x040500f0 /* KEY_UNKNOWN */
0x04060026 /* KEY_L */
0x04070069 /* KEY_LEFT */
0x0500001f /* KEY_S */
0x05010023 /* KEY_H */
0x05020024 /* KEY_J */
0x0503003d /* KEY_F3 */
0x05040043 /* KEY_F9 */
0x05050072 /* KEY_VOLUMEDOWN */
0x05060032 /* KEY_M */
0x0507006a /* KEY_RIGHT */
0x06000010 /* KEY_Q */
0x0601001e /* KEY_A */
0x06020031 /* KEY_N */
0x0603009e /* KEY_BACK */
0x0604000e /* KEY_BACKSPACE */
0x060500f0 /* KEY_UNKNOWN */
0x06060019 /* KEY_P */
0x06070067 /* KEY_UP */
0x07000094 /* KEY_PROG1 */
0x07010095 /* KEY_PROG2 */
0x070200ca /* KEY_PROG3 */
0x070300cb /* KEY_PROG4 */
0x0704003e /* KEY_F4 */
0x070500f0 /* KEY_UNKNOWN */
0x07060160 /* KEY_OK */
0x0707006c>; /* KEY_DOWN */
linux,input-no-autorepeat;
};
&uart2 {
interrupts-extended = <&wakeupgen GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART2_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
};
&uart3 {
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART3_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
};
&uart4 {
interrupts-extended = <&wakeupgen GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
&omap4_pmx_core OMAP4_UART4_RX>;
pinctrl-names = "default";
pinctrl-0 = <&uart4_pins>;
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&dmic {
pinctrl-names = "default";
pinctrl-0 = <&dmic_pins>;
status = "okay";
};
&twl_usb_comparator {
usb-supply = <&vusb>;
};
&usb_otg_hs {
interface-type = <1>;
mode = <3>;
power = <50>;
};
&dss {
status = "ok";
};
&dsi1 {
status = "ok";
vdd-supply = <&vcxio>;
port {
dsi1_out_ep: endpoint {
remote-endpoint = <&lcd0_in>;
lanes = <0 1 2 3 4 5>;
};
};
lcd0: display {
compatible = "tpo,taal", "panel-dsi-cm";
label = "lcd0";
reset-gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */
port {
lcd0_in: endpoint {
remote-endpoint = <&dsi1_out_ep>;
};
};
};
};
&dsi2 {
status = "ok";
vdd-supply = <&vcxio>;
port {
dsi2_out_ep: endpoint {
remote-endpoint = <&lcd1_in>;
lanes = <0 1 2 3 4 5>;
};
};
lcd1: display {
compatible = "tpo,taal", "panel-dsi-cm";
label = "lcd1";
reset-gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* 104 */
port {
lcd1_in: endpoint {
remote-endpoint = <&dsi2_out_ep>;
};
};
};
};
&hdmi {
status = "ok";
vdda-supply = <&vdac>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};

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// SPDX-License-Identifier: GPL-2.0+
/*
* U-Boot additions
*
* (C) Copyright 2020 Tero Kristo <t-kristo@ti.com>
*/
&l4_cfg {
segment@0 {
/* SCM Core */
target-module@2000 {
compatible = "simple-bus";
};
/* USB HS */
target-module@64000 {
compatible = "simple-bus";
};
};
};
&l4_per {
segment@0 {
/* UART3 */
target-module@20000 {
compatible = "simple-bus";
};
/* I2C1 */
target-module@70000 {
compatible = "simple-bus";
};
/* MMC1 */
target-module@9c000 {
compatible = "simple-bus";
};
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/clock/omap4.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap4.h>
/ {
compatible = "ti,omap4430", "ti,omap4";
interrupt-parent = <&wakeupgen>;
#address-cells = <1>;
#size-cells = <1>;
chosen { };
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x0>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
};
cpu@1 {
compatible = "arm,cortex-a9";
device_type = "cpu";
next-level-cache = <&L2>;
reg = <0x1>;
};
};
/*
* Note that 4430 needs cross trigger interface (CTI) supported
* before we can configure the interrupts. This means sampling
* events are not supported for pmu. Note that 4460 does not use
* CTI, see also 4460.dtsi.
*/
pmu {
compatible = "arm,cortex-a9-pmu";
ti,hwmods = "debugss";
};
gic: interrupt-controller@48241000 {
compatible = "arm,cortex-a9-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48241000 0x1000>,
<0x48240100 0x0100>;
interrupt-parent = <&gic>;
};
L2: l2-cache-controller@48242000 {
compatible = "arm,pl310-cache";
reg = <0x48242000 0x1000>;
cache-unified;
cache-level = <2>;
};
local-timer@48240600 {
compatible = "arm,cortex-a9-twd-timer";
clocks = <&mpu_periphclk>;
reg = <0x48240600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_EDGE_RISING)>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0x48281000 0x1000>;
interrupt-parent = <&gic>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
dsp {
compatible = "ti,omap3-c64";
};
iva {
compatible = "ti,ivahd";
ti,hwmods = "iva";
};
};
/*
* XXX: Use a flat representation of the OMAP4 interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap4-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0x44000000 0x1000>,
<0x44800000 0x2000>,
<0x45000000 0x1000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_wkup: interconnect@4a300000 {
};
l4_cfg: interconnect@4a000000 {
};
l4_per: interconnect@48000000 {
};
l4_abe: interconnect@40100000 {
};
ocmcram: sram@40304000 {
compatible = "mmio-sram";
reg = <0x40304000 0xa000>; /* 40k */
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
ti,no-idle-on-init;
clocks = <&l3_div_ck>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
ti,hwmods = "iss";
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-delay-us = <2>;
clocks = <&iss_clkctrl OMAP4_ISS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x52000000 0x1000000>;
/* No child device binding, driver in staging */
};
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ducati_clkctrl OMAP4_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
target-module@4012c000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x4012c000 0x4>,
<0x4012c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <SYSC_OMAP4_SOFTRESET>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&abe_clkctrl OMAP4_SLIMBUS1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x4012c000 0x1000>, /* MPU */
<0x4902c000 0x4902c000 0x1000>; /* L3 */
/* No child device binding or driver in mainline */
};
dmm@4e000000 {
compatible = "ti,omap4-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
ti,hwmods = "dmm";
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d";
reg = <0x4c000000 0x100>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d";
reg = <0x4d000000 0x100>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <1>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
aes1_target: target-module@4b501000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b501080 0x4>,
<0x4b501084 0x4>,
<0x4b501088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b501000 0x1000>;
aes1: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 111>, <&sdma 110>;
dma-names = "tx", "rx";
};
};
aes2_target: target-module@4b701000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4b701080 0x4>,
<0x4b701084 0x4>,
<0x4b701088 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_AES2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b701000 0x1000>;
aes2: aes@0 {
compatible = "ti,omap4-aes";
reg = <0 0xa0>;
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 114>, <&sdma 113>;
dma-names = "tx", "rx";
};
};
sham_target: target-module@4b100000 {
compatible = "ti,sysc-omap3-sham", "ti,sysc";
reg = <0x4b100100 0x4>,
<0x4b100110 0x4>,
<0x4b100114 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
/* Domains (P, C): l4per_pwrdm, l4_secure_clkdm */
clocks = <&l4_secure_clkctrl OMAP4_SHA2MD5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x4b100000 0x1000>;
sham: sham@0 {
compatible = "ti,omap4-sham";
reg = <0 0x300>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 119>;
dma-names = "rx";
};
};
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v2";
regulator-name = "abb_mpu";
#address-cells = <0>;
#size-cells = <0>;
ti,tranxdone-status-mask = <0x80>;
clocks = <&sys_clkin_ck>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
status = "disabled";
};
abb_iva: regulator-abb-iva {
compatible = "ti,abb-v2";
regulator-name = "abb_iva";
#address-cells = <0>;
#size-cells = <0>;
ti,tranxdone-status-mask = <0x80000000>;
clocks = <&sys_clkin_ck>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
status = "disabled";
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
clocks = <&l3_gfx_clkctrl OMAP4_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
/*
* DSS is only using l3 mapping without l4 as noted in the TRM
* "10.1.3 DSS Register Manual" for omap4460.
*/
target-module@58000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000000 4>,
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 0>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x58000000 0x1000000>;
dss: dss@0 {
compatible = "ti,omap4-dss";
reg = <0 0x80>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000000>;
target-module@1000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x1000 0x4>,
<0x1010 0x4>,
<0x1014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x1000>;
dispc@0 {
compatible = "ti,omap4-dispc";
reg = <0 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@2000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2000 0x4>,
<0x2010 0x4>,
<0x2014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
rfbi: encoder@0 {
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>, <&l3_div_ck>;
clock-names = "fck", "ick";
};
};
target-module@3000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x3000 0x4>;
reg-names = "rev";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "sys_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x3000 0x1000>;
venc: encoder@0 {
compatible = "ti,omap4-venc";
reg = <0 0x1000>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 11>;
clock-names = "fck";
};
};
target-module@4000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x4000 0x4>,
<0x4010 0x4>,
<0x4014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4000 0x1000>;
dsi1: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
target-module@5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>,
<0x5010 0x4>,
<0x5014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5000 0x1000>;
dsi2: encoder@0 {
compatible = "ti,omap4-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x20>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
};
};
target-module@6000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x6000 0x4>,
<0x6010 0x4>;
reg-names = "rev", "sysc";
/*
* Has SYSC_IDLE_SMART and SYSC_IDLE_SMART_WKUP
* but HDMI audio will fail with them.
*/
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x6000 0x2000>;
hdmi: encoder@0 {
compatible = "ti,omap4-hdmi";
reg = <0 0x200>,
<0x200 0x100>,
<0x300 0x100>,
<0x400 0x1000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 9>,
<&l3_dss_clkctrl OMAP4_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
};
};
};
};
};
#include "omap4-l4.dtsi"
#include "omap4-l4-abe.dtsi"
#include "omap44xx-clocks.dtsi"
&prm {
prm_tesla: prm@400 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
};
prm_core: prm@700 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
};
prm_ivahd: prm@f00 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0xf00 0x100>;
#reset-cells = <1>;
};
prm_device: prm@1b00 {
compatible = "ti,omap4-prm-inst", "ti,omap-prm-inst";
reg = <0x1b00 0x40>;
#reset-cells = <1>;
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&prm_clocks {
bandgap_fclk: bandgap_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&sys_32k_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
};
};

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/*
* Device Tree Source for OMAP443x SoC
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap4.dtsi"
/ {
cpus {
cpu0: cpu@0 {
/* OMAP443x variants OPP50-OPPNT */
operating-points = <
/* kHz uV */
300000 1025000
600000 1200000
800000 1313000
1008000 1375000
>;
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
};
ocp {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4>;
compatible = "ti,omap4430-bandgap";
#thermal-sensor-cells = <0>;
};
};
ocp {
abb_mpu: regulator-abb-mpu {
status = "okay";
reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>;
reg-names = "base-address", "int-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1025000 0 0 0 0 0
1200000 0 0 0 0 0
1313000 0 0 0 0 0
1375000 1 0 0 0 0
1389000 1 0 0 0 0
>;
};
/* Default unused, just provide register info for record */
abb_iva: regulator-abb-iva {
reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>;
reg-names = "base-address", "int-address";
};
};
};
&cpu_thermal {
coefficients = <0 20000>;
};
/include/ "omap443x-clocks.dtsi"

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/*
* Device Tree Source for OMAP4460 SoC
*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "omap4.dtsi"
/ {
cpus {
/* OMAP446x 'standard device' variants OPP50 to OPPTurbo */
cpu0: cpu@0 {
operating-points = <
/* kHz uV */
350000 1025000
700000 1200000
920000 1313000
>;
clock-latency = <300000>; /* From legacy driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "debugss";
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
};
ocp {
bandgap: bandgap@4a002260 {
reg = <0x4a002260 0x4
0x4a00232C 0x4
0x4a002378 0x18>;
compatible = "ti,omap4460-bandgap";
interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; /* talert */
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; /* tshut */
#thermal-sensor-cells = <0>;
};
abb_mpu: regulator-abb-mpu {
status = "okay";
reg = <0x4a307bd0 0x8>, <0x4a306014 0x4>,
<0x4A002268 0x4>;
reg-names = "base-address", "int-address",
"efuse-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1025000 0 0 0 0 0
1200000 0 0 0 0 0
1313000 0 0 0x100000 0x40000 0
1375000 1 0 0 0 0
1389000 1 0 0 0 0
>;
};
abb_iva: regulator-abb-iva {
status = "okay";
reg = <0x4a307bd8 0x8>, <0x4a306010 0x4>,
<0x4A002268 0x4>;
reg-names = "base-address", "int-address",
"efuse-address";
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
950000 0 0 0 0 0
1140000 0 0 0 0 0
1291000 0 0 0x200000 0 0
1375000 1 0 0 0 0
1376000 1 0 0 0 0
>;
};
};
};
&cpu_thermal {
coefficients = <348 (-9301)>;
};
/* Only some L4 CFG interconnect ranges are different on 4460 */
&l4_cfg_segment_300000 {
ranges = <0x00000000 0x00300000 0x020000>, /* ap 67 */
<0x00040000 0x00340000 0x001000>, /* ap 68 */
<0x00020000 0x00320000 0x004000>, /* ap 71 */
<0x00024000 0x00324000 0x002000>, /* ap 72 */
<0x00026000 0x00326000 0x001000>, /* ap 73 */
<0x00027000 0x00327000 0x001000>, /* ap 74 */
<0x00028000 0x00328000 0x001000>, /* ap 75 */
<0x00029000 0x00329000 0x001000>, /* ap 76 */
<0x00030000 0x00330000 0x010000>, /* ap 77 */
<0x0002a000 0x0032a000 0x002000>, /* ap 90 */
<0x0002c000 0x0032c000 0x004000>, /* ap 91 */
<0x00010000 0x00310000 0x008000>, /* ap 92 */
<0x00018000 0x00318000 0x004000>, /* ap 93 */
<0x0001c000 0x0031c000 0x002000>, /* ap 94 */
<0x0001e000 0x0031e000 0x002000>; /* ap 95 */
};
&l4_cfg_target_0 {
ranges = <0x00000000 0x00000000 0x00010000>,
<0x00010000 0x00010000 0x00008000>,
<0x00018000 0x00018000 0x00004000>,
<0x0001c000 0x0001c000 0x00002000>,
<0x0001e000 0x0001e000 0x00002000>,
<0x00020000 0x00020000 0x00004000>,
<0x00024000 0x00024000 0x00002000>,
<0x00026000 0x00026000 0x00001000>,
<0x00027000 0x00027000 0x00001000>,
<0x00028000 0x00028000 0x00001000>,
<0x00029000 0x00029000 0x00001000>,
<0x0002a000 0x0002a000 0x00002000>,
<0x0002c000 0x0002c000 0x00004000>,
<0x00030000 0x00030000 0x00010000>;
};
/include/ "omap446x-clocks.dtsi"

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Device Tree Source for OMAP4 clock data
*
* Copyright (C) 2013 Texas Instruments, Inc.
*/
&prm_clocks {
div_ts_ck: div_ts_ck@1888 {
#clock-cells = <0>;
compatible = "ti,divider-clock";
clocks = <&l4_wkup_clk_mux_ck>;
ti,bit-shift = <24>;
reg = <0x1888>;
ti,dividers = <8>, <16>, <32>;
};
bandgap_ts_fclk: bandgap_ts_fclk@1888 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
clocks = <&div_ts_ck>;
ti,bit-shift = <8>;
reg = <0x1888>;
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*/
#include "omap5.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
aliases {
display0 = &hdmi0;
};
chosen {
stdout-path = &uart3;
};
vmain: fixedregulator-vmain {
compatible = "regulator-fixed";
regulator-name = "vmain";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vsys_cobra: fixedregulator-vsys_cobra {
compatible = "regulator-fixed";
regulator-name = "vsys_cobra";
vin-supply = <&vmain>;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
vdds_1v8_main: fixedregulator-vdds_1v8_main {
compatible = "regulator-fixed";
regulator-name = "vdds_1v8_main";
vin-supply = <&smps7_reg>;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vmmcsd_fixed: fixedregulator-mmcsd {
compatible = "regulator-fixed";
regulator-name = "vmmcsd_fixed";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
};
mmc3_pwrseq: sdhci0_pwrseq {
compatible = "mmc-pwrseq-simple";
clocks = <&clk32kgaudio>;
clock-names = "ext_clock";
};
vmmcsdio_fixed: fixedregulator-mmcsdio {
compatible = "regulator-fixed";
regulator-name = "vmmcsdio_fixed";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio5 12 GPIO_ACTIVE_HIGH>; /* gpio140 WLAN_EN */
enable-active-high;
startup-delay-us = <70000>;
pinctrl-names = "default";
pinctrl-0 = <&wlan_pins>;
};
/* HS USB Host PHY on PORT 2 */
hsusb2_phy: hsusb2_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
clocks = <&auxclk1_ck>;
clock-names = "main_clk";
clock-frequency = <19200000>;
#phy-cells = <0>;
};
/* HS USB Host PHY on PORT 3 */
hsusb3_phy: hsusb3_phy {
compatible = "usb-nop-xceiv";
reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
#phy-cells = <0>;
};
tpd12s015: encoder {
compatible = "ti,tpd12s015";
pinctrl-names = "default";
pinctrl-0 = <&tpd12s015_pins>;
/* gpios defined in the board specific dts */
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tpd12s015_in: endpoint {
remote-endpoint = <&hdmi_out>;
};
};
port@1 {
reg = <1>;
tpd12s015_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
type = "b";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&tpd12s015_out>;
};
};
};
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "omap5-uevm";
ti,jack-detection;
ti,mclk-freq = <19200000>;
ti,mcpdm = <&mcpdm>;
ti,twl6040 = <&twl6040>;
/* Audio routing */
ti,audio-routing =
"Headset Stereophone", "HSOL",
"Headset Stereophone", "HSOR",
"Line Out", "AUXL",
"Line Out", "AUXR",
"HSMIC", "Headset Mic",
"Headset Mic", "Headset Mic Bias",
"AFML", "Line In",
"AFMR", "Line In";
};
};
&gpio8 {
/* TI trees use GPIO instead of msecure, see also muxing */
p234 {
gpio-hog;
gpios = <10 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "gpio8_234/msecure";
};
};
&omap5_pmx_core {
pinctrl-names = "default";
pinctrl-0 = <
&usbhost_pins
&led_gpio_pins
>;
twl6040_pins: pinmux_twl6040_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
>;
};
mcpdm_pins: pinmux_mcpdm_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x182, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abe_clks.abe_clks */
OMAP5_IOPAD(0x19c, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_ul_data.abemcpdm_ul_data */
OMAP5_IOPAD(0x19e, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_dl_data.abemcpdm_dl_data */
OMAP5_IOPAD(0x1a0, PIN_INPUT_PULLUP | MUX_MODE0) /* abemcpdm_frame.abemcpdm_frame */
OMAP5_IOPAD(0x1a2, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcpdm_lb_clk.abemcpdm_lb_clk */
>;
};
mcbsp1_pins: pinmux_mcbsp1_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x18c, PIN_INPUT | MUX_MODE1) /* abedmic_clk2.abemcbsp1_fsx */
OMAP5_IOPAD(0x18e, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* abedmic_clk3.abemcbsp1_dx */
OMAP5_IOPAD(0x190, PIN_INPUT | MUX_MODE1) /* abeslimbus1_clock.abemcbsp1_clkx */
OMAP5_IOPAD(0x192, PIN_INPUT_PULLDOWN | MUX_MODE1) /* abeslimbus1_data.abemcbsp1_dr */
>;
};
mcbsp2_pins: pinmux_mcbsp2_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x194, PIN_INPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dr.abemcbsp2_dr */
OMAP5_IOPAD(0x196, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* abemcbsp2_dx.abemcbsp2_dx */
OMAP5_IOPAD(0x198, PIN_INPUT | MUX_MODE0) /* abemcbsp2_fsx.abemcbsp2_fsx */
OMAP5_IOPAD(0x19a, PIN_INPUT | MUX_MODE0) /* abemcbsp2_clkx.abemcbsp2_clkx */
>;
};
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1f2, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl */
OMAP5_IOPAD(0x1f4, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda */
>;
};
mcspi2_pins: pinmux_mcspi2_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x0fc, PIN_INPUT | MUX_MODE0) /* mcspi2_clk */
OMAP5_IOPAD(0x0fe, PIN_INPUT | MUX_MODE0) /* mcspi2_simo */
OMAP5_IOPAD(0x100, PIN_INPUT_PULLUP | MUX_MODE0) /* mcspi2_somi */
OMAP5_IOPAD(0x102, PIN_OUTPUT | MUX_MODE0) /* mcspi2_cs0 */
>;
};
mcspi3_pins: pinmux_mcspi3_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x0b8, PIN_INPUT | MUX_MODE1) /* mcspi3_somi */
OMAP5_IOPAD(0x0ba, PIN_INPUT | MUX_MODE1) /* mcspi3_cs0 */
OMAP5_IOPAD(0x0bc, PIN_INPUT | MUX_MODE1) /* mcspi3_simo */
OMAP5_IOPAD(0x0be, PIN_INPUT | MUX_MODE1) /* mcspi3_clk */
>;
};
mmc3_pins: pinmux_mmc3_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x01a4, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_clk */
OMAP5_IOPAD(0x01a6, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_cmd */
OMAP5_IOPAD(0x01a8, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data0 */
OMAP5_IOPAD(0x01aa, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data1 */
OMAP5_IOPAD(0x01ac, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data2 */
OMAP5_IOPAD(0x01ae, PIN_INPUT_PULLUP | MUX_MODE0) /* wlsdio_data3 */
>;
};
wlan_pins: pinmux_wlan_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1bc, PIN_OUTPUT | MUX_MODE6) /* mcspi1_clk.gpio5_140 */
>;
};
/* TI trees use GPIO mode; msecure mode does not work reliably? */
palmas_msecure_pins: palmas_msecure_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x180, PIN_OUTPUT | MUX_MODE6) /* gpio8_234 */
>;
};
usbhost_pins: pinmux_usbhost_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x0c4, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_strobe */
OMAP5_IOPAD(0x0c6, PIN_INPUT | MUX_MODE0) /* usbb2_hsic_data */
OMAP5_IOPAD(0x1de, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_strobe */
OMAP5_IOPAD(0x1e0, PIN_INPUT | MUX_MODE0) /* usbb3_hsic_data */
OMAP5_IOPAD(0x0b0, PIN_OUTPUT | MUX_MODE6) /* gpio3_80 HUB_NRESET */
OMAP5_IOPAD(0x0ae, PIN_OUTPUT | MUX_MODE6) /* gpio3_79 ETH_NRESET */
>;
};
led_gpio_pins: pinmux_led_gpio_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1d6, PIN_OUTPUT | MUX_MODE6) /* uart3_cts_rctx.gpio5_153 */
>;
};
uart1_pins: pinmux_uart1_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x0a0, PIN_OUTPUT | MUX_MODE0) /* uart1_tx.uart1_cts */
OMAP5_IOPAD(0x0a2, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_tx.uart1_cts */
OMAP5_IOPAD(0x0a4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rx.uart1_rts */
OMAP5_IOPAD(0x0a6, PIN_OUTPUT | MUX_MODE0) /* uart1_rx.uart1_rts */
>;
};
uart3_pins: pinmux_uart3_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1da, PIN_OUTPUT | MUX_MODE0) /* uart3_rts_irsd.uart3_tx_irtx */
OMAP5_IOPAD(0x1dc, PIN_INPUT_PULLUP | MUX_MODE0) /* uart3_rx_irrx.uart3_usbb3_hsic */
>;
};
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1b0, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_rx.uart5_rx */
OMAP5_IOPAD(0x1b2, PIN_OUTPUT | MUX_MODE0) /* uart5_tx.uart5_tx */
OMAP5_IOPAD(0x1b4, PIN_INPUT_PULLUP | MUX_MODE0) /* uart5_cts.uart5_rts */
OMAP5_IOPAD(0x1b6, PIN_OUTPUT | MUX_MODE0) /* uart5_cts.uart5_rts */
>;
};
dss_hdmi_pins: pinmux_dss_hdmi_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x13c, PIN_INPUT | MUX_MODE0) /* hdmi_cec.hdmi_cec */
OMAP5_IOPAD(0x140, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_scl.hdmi_ddc_scl */
OMAP5_IOPAD(0x142, PIN_INPUT | MUX_MODE0) /* hdmi_ddc_sda.hdmi_ddc_sda */
>;
};
tpd12s015_pins: pinmux_tpd12s015_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x13e, PIN_INPUT_PULLDOWN | MUX_MODE6) /* hdmi_hpd.gpio7_193 */
>;
};
};
&omap5_pmx_wkup {
pinctrl-names = "default";
pinctrl-0 = <
&usbhost_wkup_pins
>;
palmas_sys_nirq_pins: pinmux_palmas_sys_nirq_pins {
pinctrl-single,pins = <
/* sys_nirq1 is pulled down as the SoC is inverting it for GIC */
OMAP5_IOPAD(0x068, PIN_INPUT_PULLUP | MUX_MODE0)
>;
};
usbhost_wkup_pins: pinmux_usbhost_wkup_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x05a, PIN_OUTPUT | MUX_MODE0) /* fref_clk1_out, USB hub clk */
>;
};
wlcore_irq_pin: pinmux_wlcore_irq_pin {
pinctrl-single,pins = <
OMAP5_IOPAD(0x40, PIN_INPUT | MUX_MODE6) /* llia_wakereqin.gpio1_wk14 */
>;
};
};
&mmc1 {
vmmc-supply = <&ldo9_reg>;
bus-width = <4>;
};
&mmc2 {
vmmc-supply = <&vmmcsd_fixed>;
bus-width = <8>;
ti,non-removable;
};
&mmc3 {
vmmc-supply = <&vmmcsdio_fixed>;
mmc-pwrseq = <&mmc3_pwrseq>;
bus-width = <4>;
non-removable;
cap-power-off-card;
pinctrl-names = "default";
pinctrl-0 = <&mmc3_pins>;
interrupts-extended = <&wakeupgen GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH
&omap5_pmx_core 0x16a>;
#address-cells = <1>;
#size-cells = <0>;
wlcore: wlcore@2 {
compatible = "ti,wl1271";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&wlcore_irq_pin>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>; /* gpio 14 */
ref-clock-frequency = <26000000>;
};
};
&mmc4 {
status = "disabled";
};
&mmc5 {
status = "disabled";
};
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
palmas: palmas@48 {
compatible = "ti,palmas";
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_LOW>;
reg = <0x48>;
interrupt-controller;
#interrupt-cells = <2>;
ti,system-power-controller;
ti,mux-pad1 = <0xa1>;
ti,mux-pad2 = <0x1b>;
pinctrl-names = "default";
pinctrl-0 = <&palmas_sys_nirq_pins &palmas_msecure_pins>;
palmas_gpio: gpio {
compatible = "ti,palmas-gpio";
gpio-controller;
#gpio-cells = <2>;
};
extcon_usb3: palmas_usb {
compatible = "ti,palmas-usb-vid";
ti,enable-vbus-detection;
ti,enable-id-detection;
ti,wakeup;
id-gpios = <&palmas_gpio 0 GPIO_ACTIVE_HIGH>;
};
clk32kgaudio: palmas_clk32k@1 {
compatible = "ti,palmas-clk32kgaudio";
#clock-cells = <0>;
};
rtc {
compatible = "ti,palmas-rtc";
interrupt-parent = <&palmas>;
interrupts = <8 IRQ_TYPE_NONE>;
ti,backup-battery-chargeable;
ti,backup-battery-charge-high-current;
};
gpadc: gpadc {
compatible = "ti,palmas-gpadc";
interrupts = <18 0
16 0
17 0>;
#io-channel-cells = <1>;
ti,channel0-current-microamp = <5>;
ti,channel3-current-microamp = <10>;
};
palmas_pmic {
compatible = "ti,palmas-pmic";
interrupt-parent = <&palmas>;
interrupts = <14 IRQ_TYPE_NONE>;
interrupt-names = "short-irq";
ti,ldo6-vibrator;
smps123-in-supply = <&vsys_cobra>;
smps45-in-supply = <&vsys_cobra>;
smps6-in-supply = <&vsys_cobra>;
smps7-in-supply = <&vsys_cobra>;
smps8-in-supply = <&vsys_cobra>;
smps9-in-supply = <&vsys_cobra>;
smps10_out2-in-supply = <&vsys_cobra>;
smps10_out1-in-supply = <&vsys_cobra>;
ldo1-in-supply = <&vsys_cobra>;
ldo2-in-supply = <&vsys_cobra>;
ldo3-in-supply = <&vdds_1v8_main>;
ldo4-in-supply = <&vdds_1v8_main>;
ldo5-in-supply = <&vsys_cobra>;
ldo6-in-supply = <&vdds_1v8_main>;
ldo7-in-supply = <&vsys_cobra>;
ldo8-in-supply = <&vsys_cobra>;
ldo9-in-supply = <&vmmcsd_fixed>;
ldoln-in-supply = <&vsys_cobra>;
ldousb-in-supply = <&vsys_cobra>;
regulators {
smps123_reg: smps123 {
/* VDD_OPP_MPU */
regulator-name = "smps123";
regulator-min-microvolt = < 600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
};
smps45_reg: smps45 {
/* VDD_OPP_MM */
regulator-name = "smps45";
regulator-min-microvolt = < 600000>;
regulator-max-microvolt = <1310000>;
regulator-always-on;
regulator-boot-on;
};
smps6_reg: smps6 {
/* VDD_DDR3 - over VDD_SMPS6 */
regulator-name = "smps6";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
smps7_reg: smps7 {
/* VDDS_1v8_OMAP over VDDS_1v8_MAIN */
regulator-name = "smps7";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
smps8_reg: smps8 {
/* VDD_OPP_CORE */
regulator-name = "smps8";
regulator-min-microvolt = < 600000>;
regulator-max-microvolt = <1310000>;
regulator-always-on;
regulator-boot-on;
};
smps9_reg: smps9 {
/* VDDA_2v1_AUD over VDD_2v1 */
regulator-name = "smps9";
regulator-min-microvolt = <2100000>;
regulator-max-microvolt = <2100000>;
ti,smps-range = <0x80>;
};
smps10_out2_reg: smps10_out2 {
/* VBUS_5V_OTG */
regulator-name = "smps10_out2";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
regulator-boot-on;
};
smps10_out1_reg: smps10_out1 {
/* VBUS_5V_OTG */
regulator-name = "smps10_out1";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
ldo1_reg: ldo1 {
/* VDDAPHY_CAM: vdda_csiport */
regulator-name = "ldo1";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo2_reg: ldo2 {
/* VCC_2V8_DISP: Does not go anywhere */
regulator-name = "ldo2";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
/* Unused */
status = "disabled";
};
ldo3_reg: ldo3 {
/* VDDAPHY_MDM: vdda_lli */
regulator-name = "ldo3";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
regulator-boot-on;
/* Only if Modem is used */
status = "disabled";
};
ldo4_reg: ldo4 {
/* VDDAPHY_DISP: vdda_dsiport/hdmi */
regulator-name = "ldo4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo5_reg: ldo5 {
/* VDDA_1V8_PHY: usb/sata/hdmi.. */
regulator-name = "ldo5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldo6_reg: ldo6 {
/* VDDS_1V2_WKUP: hsic/ldo_emu_wkup */
regulator-name = "ldo6";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
ldo7_reg: ldo7 {
/* VDD_VPP: vpp1 */
regulator-name = "ldo7";
regulator-min-microvolt = <2000000>;
regulator-max-microvolt = <2000000>;
/* Only for efuse reprograming! */
status = "disabled";
};
ldo8_reg: ldo8 {
/* VDD_3v0: Does not go anywhere */
regulator-name = "ldo8";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
/* Unused */
status = "disabled";
};
ldo9_reg: ldo9 {
/* VCC_DV_SDIO: vdds_sdcard */
regulator-name = "ldo9";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
};
ldoln_reg: ldoln {
/* VDDA_1v8_REF: vdds_osc/mm_l4per.. */
regulator-name = "ldoln";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
ldousb_reg: ldousb {
/* VDDA_3V_USB: VDDA_USBHS33 */
regulator-name = "ldousb";
regulator-min-microvolt = <3250000>;
regulator-max-microvolt = <3250000>;
regulator-always-on;
regulator-boot-on;
};
regen3_reg: regen3 {
/* REGEN3 controls LDO9 supply to card */
regulator-name = "regen3";
regulator-always-on;
regulator-boot-on;
};
};
};
palmas_power_button: palmas_power_button {
compatible = "ti,palmas-pwrbutton";
interrupt-parent = <&palmas>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
wakeup-source;
};
};
twl6040: twl@4b {
compatible = "ti,twl6040";
#clock-cells = <0>;
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&twl6040_pins>;
/* sys_nirq/ext_sys_irq pins get inverted at mpuss wakeupgen */
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_LOW>;
/* audpwron gpio defined in the board specific dts */
vio-supply = <&smps7_reg>;
v2v1-supply = <&smps9_reg>;
enable-active-high;
clocks = <&clk32kgaudio>, <&fref_xtal_ck>;
clock-names = "clk32k", "mclk";
};
};
&mcpdm_module {
/* Module on the SoC needs external clock from the PMIC */
pinctrl-names = "default";
pinctrl-0 = <&mcpdm_pins>;
status = "okay";
};
&mcpdm {
clocks = <&twl6040>;
clock-names = "pdmclk";
};
&mcbsp1 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp1_pins>;
status = "okay";
};
&mcbsp2 {
pinctrl-names = "default";
pinctrl-0 = <&mcbsp2_pins>;
status = "okay";
};
&usbhshost {
port2-mode = "ehci-hsic";
port3-mode = "ehci-hsic";
};
&usbhsehci {
phys = <0 &hsusb2_phy &hsusb3_phy>;
};
&usb3 {
extcon = <&extcon_usb3>;
vbus-supply = <&smps10_out1_reg>;
};
&dwc3 {
extcon = <&extcon_usb3>;
dr_mode = "otg";
};
&mcspi1 {
};
&mcspi2 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi2_pins>;
};
&mcspi3 {
pinctrl-names = "default";
pinctrl-0 = <&mcspi3_pins>;
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&uart3_pins>;
interrupts-extended = <&wakeupgen GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<&omap5_pmx_core 0x19c>;
};
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
};
&cpu0 {
cpu0-supply = <&smps123_reg>;
};
&dss {
status = "ok";
};
&hdmi {
status = "ok";
/* vdda-supply populated in board specific dts file */
pinctrl-names = "default";
pinctrl-0 = <&dss_hdmi_pins>;
port {
hdmi_out: endpoint {
remote-endpoint = <&tpd12s015_in>;
};
};
};

449
arch/arm/dts/omap5-l4-abe.dtsi Normal file
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@ -0,0 +1,449 @@
&l4_abe { /* 0x40100000 */
compatible = "ti,omap5-l4-abe", "simple-bus";
reg = <0x40100000 0x400>,
<0x40100400 0x400>;
reg-names = "la", "ap";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x00000000 0x40100000 0x100000>, /* segment 0 */
<0x49000000 0x49000000 0x100000>;
segment@0 { /* 0x40100000 */
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges =
/* CPU to L4 ABE mapping */
<0x00000000 0x00000000 0x000400>, /* ap 0 */
<0x00000400 0x00000400 0x000400>, /* ap 1 */
<0x00022000 0x00022000 0x001000>, /* ap 2 */
<0x00023000 0x00023000 0x001000>, /* ap 3 */
<0x00024000 0x00024000 0x001000>, /* ap 4 */
<0x00025000 0x00025000 0x001000>, /* ap 5 */
<0x00026000 0x00026000 0x001000>, /* ap 6 */
<0x00027000 0x00027000 0x001000>, /* ap 7 */
<0x00028000 0x00028000 0x001000>, /* ap 8 */
<0x00029000 0x00029000 0x001000>, /* ap 9 */
<0x0002a000 0x0002a000 0x001000>, /* ap 10 */
<0x0002b000 0x0002b000 0x001000>, /* ap 11 */
<0x0002e000 0x0002e000 0x001000>, /* ap 12 */
<0x0002f000 0x0002f000 0x001000>, /* ap 13 */
<0x00030000 0x00030000 0x001000>, /* ap 14 */
<0x00031000 0x00031000 0x001000>, /* ap 15 */
<0x00032000 0x00032000 0x001000>, /* ap 16 */
<0x00033000 0x00033000 0x001000>, /* ap 17 */
<0x00038000 0x00038000 0x001000>, /* ap 18 */
<0x00039000 0x00039000 0x001000>, /* ap 19 */
<0x0003a000 0x0003a000 0x001000>, /* ap 20 */
<0x0003b000 0x0003b000 0x001000>, /* ap 21 */
<0x0003c000 0x0003c000 0x001000>, /* ap 22 */
<0x0003d000 0x0003d000 0x001000>, /* ap 23 */
<0x0003e000 0x0003e000 0x001000>, /* ap 24 */
<0x0003f000 0x0003f000 0x001000>, /* ap 25 */
<0x00080000 0x00080000 0x010000>, /* ap 26 */
<0x00080000 0x00080000 0x001000>, /* ap 27 */
<0x000a0000 0x000a0000 0x010000>, /* ap 28 */
<0x000a0000 0x000a0000 0x001000>, /* ap 29 */
<0x000c0000 0x000c0000 0x010000>, /* ap 30 */
<0x000c0000 0x000c0000 0x001000>, /* ap 31 */
<0x000f1000 0x000f1000 0x001000>, /* ap 32 */
<0x000f2000 0x000f2000 0x001000>, /* ap 33 */
/* L3 to L4 ABE mapping */
<0x49000000 0x49000000 0x000400>, /* ap 0 */
<0x49000400 0x49000400 0x000400>, /* ap 1 */
<0x49022000 0x49022000 0x001000>, /* ap 2 */
<0x49023000 0x49023000 0x001000>, /* ap 3 */
<0x49024000 0x49024000 0x001000>, /* ap 4 */
<0x49025000 0x49025000 0x001000>, /* ap 5 */
<0x49026000 0x49026000 0x001000>, /* ap 6 */
<0x49027000 0x49027000 0x001000>, /* ap 7 */
<0x49028000 0x49028000 0x001000>, /* ap 8 */
<0x49029000 0x49029000 0x001000>, /* ap 9 */
<0x4902a000 0x4902a000 0x001000>, /* ap 10 */
<0x4902b000 0x4902b000 0x001000>, /* ap 11 */
<0x4902e000 0x4902e000 0x001000>, /* ap 12 */
<0x4902f000 0x4902f000 0x001000>, /* ap 13 */
<0x49030000 0x49030000 0x001000>, /* ap 14 */
<0x49031000 0x49031000 0x001000>, /* ap 15 */
<0x49032000 0x49032000 0x001000>, /* ap 16 */
<0x49033000 0x49033000 0x001000>, /* ap 17 */
<0x49038000 0x49038000 0x001000>, /* ap 18 */
<0x49039000 0x49039000 0x001000>, /* ap 19 */
<0x4903a000 0x4903a000 0x001000>, /* ap 20 */
<0x4903b000 0x4903b000 0x001000>, /* ap 21 */
<0x4903c000 0x4903c000 0x001000>, /* ap 22 */
<0x4903d000 0x4903d000 0x001000>, /* ap 23 */
<0x4903e000 0x4903e000 0x001000>, /* ap 24 */
<0x4903f000 0x4903f000 0x001000>, /* ap 25 */
<0x49080000 0x49080000 0x010000>, /* ap 26 */
<0x49080000 0x49080000 0x001000>, /* ap 27 */
<0x490a0000 0x490a0000 0x010000>, /* ap 28 */
<0x490a0000 0x490a0000 0x001000>, /* ap 29 */
<0x490c0000 0x490c0000 0x010000>, /* ap 30 */
<0x490c0000 0x490c0000 0x001000>, /* ap 31 */
<0x490f1000 0x490f1000 0x001000>, /* ap 32 */
<0x490f2000 0x490f2000 0x001000>; /* ap 33 */
target-module@22000 { /* 0x40122000, ap 2 02.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2208c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_MCBSP1_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x22000 0x1000>,
<0x49022000 0x49022000 0x1000>;
mcbsp1: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49022000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 33>,
<&sdma 34>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@24000 { /* 0x40124000, ap 4 04.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2408c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_MCBSP2_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x24000 0x1000>,
<0x49024000 0x49024000 0x1000>;
mcbsp2: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49024000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 17>,
<&sdma 18>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@26000 { /* 0x40126000, ap 6 06.0 */
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2608c 0x4>;
reg-names = "sysc";
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_MCBSP3_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x26000 0x1000>,
<0x49026000 0x49026000 0x1000>;
mcbsp3: mcbsp@0 {
compatible = "ti,omap4-mcbsp";
reg = <0x0 0xff>, /* MPU private access */
<0x49026000 0xff>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common";
ti,buffer-size = <128>;
dmas = <&sdma 19>,
<&sdma 20>;
dma-names = "tx", "rx";
status = "disabled";
};
};
target-module@28000 { /* 0x40128000, ap 8 08.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x28000 0x1000>,
<0x49028000 0x49028000 0x1000>;
};
target-module@2a000 { /* 0x4012a000, ap 10 0a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2a000 0x1000>,
<0x4902a000 0x4902a000 0x1000>;
};
target-module@2e000 { /* 0x4012e000, ap 12 0c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x2e000 0x4>,
<0x2e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_DMIC_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x2e000 0x1000>,
<0x4902e000 0x4902e000 0x1000>;
dmic: dmic@0 {
compatible = "ti,omap4-dmic";
reg = <0x0 0x7f>, /* MPU private access */
<0x4902e000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 67>;
dma-names = "up_link";
status = "disabled";
};
};
target-module@30000 { /* 0x40130000, ap 14 0e.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x30000 0x1000>,
<0x49030000 0x49030000 0x1000>;
};
mcpdm_module: target-module@32000 { /* 0x40132000, ap 16 10.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x32000 0x4>,
<0x32010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_MCPDM_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x32000 0x1000>,
<0x49032000 0x49032000 0x1000>;
/* Must be only enabled for boards with pdmclk wired */
status = "disabled";
mcpdm: mcpdm@0 {
compatible = "ti,omap4-mcpdm";
reg = <0x0 0x7f>, /* MPU private access */
<0x49032000 0x7f>; /* L3 Interconnect */
reg-names = "mpu", "dma";
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 65>,
<&sdma 66>;
dma-names = "up_link", "dn_link";
};
};
target-module@38000 { /* 0x40138000, ap 18 12.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x38000 0x4>,
<0x38010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x38000 0x1000>,
<0x49038000 0x49038000 0x1000>;
timer5: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x49038000 0x80>;
clocks = <&abe_clkctrl OMAP5_TIMER5_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
};
};
target-module@3a000 { /* 0x4013a000, ap 20 14.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3a000 0x4>,
<0x3a010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3a000 0x1000>,
<0x4903a000 0x4903a000 0x1000>;
timer6: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903a000 0x80>;
clocks = <&abe_clkctrl OMAP5_TIMER6_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
};
};
target-module@3c000 { /* 0x4013c000, ap 22 16.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3c000 0x4>,
<0x3c010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3c000 0x1000>,
<0x4903c000 0x4903c000 0x1000>;
timer7: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903c000 0x80>;
clocks = <&abe_clkctrl OMAP5_TIMER7_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
};
};
target-module@3e000 { /* 0x4013e000, ap 24 18.0 */
compatible = "ti,sysc-omap4-timer", "ti,sysc";
reg = <0x3e000 0x4>,
<0x3e010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
SYSC_OMAP4_SOFTRESET)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
/* Domains (V, P, C): core, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x3e000 0x1000>,
<0x4903e000 0x4903e000 0x1000>;
timer8: timer@0 {
compatible = "ti,omap5430-timer";
reg = <0x0 0x80>,
<0x4903e000 0x80>;
clocks = <&abe_clkctrl OMAP5_TIMER8_CLKCTRL 24>;
clock-names = "fck";
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
ti,timer-dsp;
ti,timer-pwm;
};
};
target-module@80000 { /* 0x40180000, ap 26 1a.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x80000 0x10000>,
<0x49080000 0x49080000 0x10000>;
};
target-module@a0000 { /* 0x401a0000, ap 28 1c.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xa0000 0x10000>,
<0x490a0000 0x490a0000 0x10000>;
};
target-module@c0000 { /* 0x401c0000, ap 30 1e.0 */
compatible = "ti,sysc";
status = "disabled";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xc0000 0x10000>,
<0x490c0000 0x490c0000 0x10000>;
};
target-module@f1000 { /* 0x401f1000, ap 32 20.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0xf1000 0x4>,
<0xf1010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
/* Domains (V, P, C): iva, abe_pwrdm, abe_clkdm */
clocks = <&abe_clkctrl OMAP5_AESS_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xf1000 0x1000>,
<0x490f1000 0x490f1000 0x1000>;
};
};
};

2437
arch/arm/dts/omap5-l4.dtsi Normal file
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File diff suppressed because it is too large Load Diff

42
arch/arm/dts/omap5-u-boot.dtsi
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@ -7,6 +7,7 @@
* Based on "dra7.dtsi"
*/
#ifdef CONFIG_DRA7XX
/{
chosen {
tick-timer = &timer2;
@ -105,3 +106,44 @@
&i2c1 {
u-boot,dm-spl;
};
#else /* OMAP54XX */
&l4_cfg {
segment@0 {
/* SCM Core */
target-module@2000 {
compatible = "simple-bus";
};
/* USB HS */
target-module@64000 {
compatible = "simple-bus";
};
};
};
&l4_per {
segment@0 {
/* UART3 */
target-module@20000 {
compatible = "simple-bus";
};
/* I2C1 */
target-module@70000 {
compatible = "simple-bus";
};
/* MMC1 */
target-module@9c000 {
compatible = "simple-bus";
};
/* MMC2 */
target-module@b4000 {
compatible = "simple-bus";
};
};
};
#endif

200
arch/arm/dts/omap5-uevm.dts Normal file
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@ -0,0 +1,200 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*/
/dts-v1/;
#include "omap5-board-common.dtsi"
/ {
model = "TI OMAP5 uEVM board";
compatible = "ti,omap5-uevm", "ti,omap5";
memory@80000000 {
device_type = "memory";
reg = <0 0x80000000 0 0x7f000000>; /* 2032 MB */
};
aliases {
ethernet = &ethernet;
};
leds {
compatible = "gpio-leds";
led1 {
label = "omap5:blue:usr1";
gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>; /* gpio5_153 D1 LED */
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
evm_keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&evm_keys_pins>;
#address-cells = <7>;
#size-cells = <0>;
btn1 {
label = "BTN1";
linux,code = <169>;
gpios = <&gpio3 19 GPIO_ACTIVE_LOW>; /* gpio3_83 */
wakeup-source;
autorepeat;
debounce-interval = <50>;
};
};
evm_leds {
compatible = "gpio-leds";
led1 {
label = "omap5:red:led";
gpios = <&gpio9 17 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led2 {
label = "omap5:green:led";
gpios = <&gpio9 18 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";
};
led3 {
label = "omap5:blue:led";
gpios = <&gpio9 19 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc2";
default-state = "off";
};
led4 {
label = "omap5:green:led1";
gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led5 {
label = "omap5:green:led2";
gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
default-state = "off";
};
led6 {
label = "omap5:green:led3";
gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led7 {
label = "omap5:green:led4";
gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "default-on";
default-state = "off";
};
led8 {
label = "omap5:green:led5";
gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
};
};
&hdmi {
vdda-supply = <&ldo4_reg>;
};
&i2c1 {
eeprom@50 {
compatible = "atmel,24c02";
reg = <0x50>;
};
};
&i2c5 {
pinctrl-names = "default";
pinctrl-0 = <&i2c5_pins>;
clock-frequency = <400000>;
gpio9: gpio@22 {
compatible = "ti,tca6424";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
};
};
&mmc1 {
pinctrl-names = "default";
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio5 24 GPIO_ACTIVE_LOW>; /* gpio5_152 */
};
&omap5_pmx_core {
evm_keys_pins: pinmux_evm_keys_gpio_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x0b6, PIN_INPUT | MUX_MODE6) /* gpio3_83 */
>;
};
i2c5_pins: pinmux_i2c5_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1c6, PIN_INPUT | MUX_MODE0) /* i2c5_scl */
OMAP5_IOPAD(0x1c8, PIN_INPUT | MUX_MODE0) /* i2c5_sda */
>;
};
mmc1_pins: pinmux_mmc1_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1d4, PIN_INPUT_PULLUP | MUX_MODE6) /* gpio5_152 */
>;
};
};
&tpd12s015 {
gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>, /* TCA6424A P01, CT CP HPD */
<&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
<&gpio7 1 GPIO_ACTIVE_HIGH>; /* GPIO 193, HPD */
};
&twl6040 {
ti,audpwron-gpio = <&gpio5 13 GPIO_ACTIVE_HIGH>; /* gpio line 141 */
};
&twl6040_pins {
pinctrl-single,pins = <
OMAP5_IOPAD(0x1be, PIN_OUTPUT | MUX_MODE6) /* mcspi1_somi.gpio5_141 */
>;
};
&usbhsehci {
#address-cells = <1>;
#size-cells = <0>;
hub@2 {
compatible = "usb424,3503";
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
ethernet: usbether@3 {
compatible = "usb424,9730";
reg = <3>;
};
};
&wlcore {
compatible = "ti,wl1837";
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
*
* Based on "omap4.dtsi"
*/
#include <dt-bindings/bus/ti-sysc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/omap.h>
#include <dt-bindings/clock/omap5.h>
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "ti,omap5";
interrupt-parent = <&wakeupgen>;
chosen { };
aliases {
i2c0 = &i2c1;
i2c1 = &i2c2;
i2c2 = &i2c3;
i2c3 = &i2c4;
i2c4 = &i2c5;
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
serial5 = &uart6;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x0>;
operating-points = <
/* kHz uV */
1000000 1060000
1500000 1250000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
operating-points = <
/* kHz uV */
1000000 1060000
1500000 1250000
>;
clocks = <&dpll_mpu_ck>;
clock-names = "cpu";
clock-latency = <300000>; /* From omap-cpufreq driver */
/* cooling options */
#cooling-cells = <2>; /* min followed by max */
};
};
thermal-zones {
#include "omap4-cpu-thermal.dtsi"
#include "omap5-gpu-thermal.dtsi"
#include "omap5-core-thermal.dtsi"
};
timer {
compatible = "arm,armv7-timer";
/* PPI secure/nonsecure IRQ */
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
interrupt-parent = <&gic>;
};
pmu {
compatible = "arm,cortex-a15-pmu";
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
};
gic: interrupt-controller@48211000 {
compatible = "arm,cortex-a15-gic";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48211000 0 0x1000>,
<0 0x48212000 0 0x2000>,
<0 0x48214000 0 0x2000>,
<0 0x48216000 0 0x2000>;
interrupt-parent = <&gic>;
};
wakeupgen: interrupt-controller@48281000 {
compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
interrupt-controller;
#interrupt-cells = <3>;
reg = <0 0x48281000 0 0x1000>;
interrupt-parent = <&gic>;
};
/*
* The soc node represents the soc top level view. It is used for IPs
* that are not memory mapped in the MPU view or for the MPU itself.
*/
soc {
compatible = "ti,omap-infra";
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
sram = <&ocmcram>;
};
};
/*
* XXX: Use a flat representation of the OMAP3 interconnect.
* The real OMAP interconnect network is quite complex.
* Since it will not bring real advantage to represent that in DT for
* the moment, just use a fake OCP bus entry to represent the whole bus
* hierarchy.
*/
ocp {
compatible = "ti,omap5-l3-noc", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xc0000000>;
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
reg = <0 0x44000000 0 0x2000>,
<0 0x44800000 0 0x3000>,
<0 0x45000000 0 0x4000>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
l4_wkup: interconnect@4ae00000 {
};
l4_cfg: interconnect@4a000000 {
};
l4_per: interconnect@48000000 {
};
l4_abe: interconnect@40100000 {
};
ocmcram: sram@40300000 {
compatible = "mmio-sram";
reg = <0x40300000 0x20000>; /* 128k */
};
gpmc: gpmc@50000000 {
compatible = "ti,omap4430-gpmc";
reg = <0x50000000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&sdma 4>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
ti,hwmods = "gpmc";
clocks = <&l3_iclk_div>;
clock-names = "fck";
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
target-module@55082000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x55082000 0x4>,
<0x55082010 0x4>,
<0x55082014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
clocks = <&ipu_clkctrl OMAP5_MMU_IPU_CLKCTRL 0>;
clock-names = "fck";
resets = <&prm_core 2>;
reset-names = "rstctrl";
ranges = <0x0 0x55082000 0x100>;
#size-cells = <1>;
#address-cells = <1>;
mmu_ipu: mmu@0 {
compatible = "ti,omap4-iommu";
reg = <0x0 0x100>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
#iommu-cells = <0>;
ti,iommu-bus-err-back;
};
};
dmm@4e000000 {
compatible = "ti,omap5-dmm";
reg = <0x4e000000 0x800>;
interrupts = <0 113 0x4>;
ti,hwmods = "dmm";
};
emif1: emif@4c000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif1";
ti,no-idle-on-init;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4c000000 0x400>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
emif2: emif@4d000000 {
compatible = "ti,emif-4d5";
ti,hwmods = "emif2";
ti,no-idle-on-init;
phy-type = <2>; /* DDR PHY type: Intelli PHY */
reg = <0x4d000000 0x400>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
hw-caps-read-idle-ctrl;
hw-caps-ll-interface;
hw-caps-temp-alert;
};
bandgap: bandgap@4a0021e0 {
reg = <0x4a0021e0 0xc
0x4a00232c 0xc
0x4a002380 0x2c
0x4a0023C0 0x3c>;
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
compatible = "ti,omap5430-bandgap";
#thermal-sensor-cells = <1>;
};
/* OCP2SCP3 */
sata: sata@4a141100 {
compatible = "snps,dwc-ahci";
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
phys = <&sata_phy>;
phy-names = "sata-phy";
clocks = <&l3init_clkctrl OMAP5_SATA_CLKCTRL 8>;
ti,hwmods = "sata";
ports-implemented = <0x1>;
};
target-module@56000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x5600fe00 0x4>,
<0x5600fe10 0x4>;
reg-names = "rev", "sysc";
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
clocks = <&gpu_clkctrl OMAP5_GPU_CLKCTRL 0>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x56000000 0x2000000>;
/*
* Closed source PowerVR driver, no child device
* binding or driver in mainline
*/
};
target-module@58000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x58000000 4>,
<0x58000014 4>;
reg-names = "rev", "syss";
ti,syss-mask = <1>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 0>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 11>;
clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x58000000 0x1000000>;
dss: dss@0 {
compatible = "ti,omap5-dss";
reg = <0 0x80>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x1000000>;
target-module@1000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x1000 0x4>,
<0x1010 0x4>,
<0x1014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x1000 0x1000>;
dispc@0 {
compatible = "ti,omap5-dispc";
reg = <0 0x1000>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@2000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x2000 0x4>,
<0x2010 0x4>,
<0x2014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
rfbi: encoder@0 {
compatible = "ti,omap5-rfbi";
reg = <0 0x100>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>, <&l3_iclk_div>;
clock-names = "fck", "ick";
};
};
target-module@5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x5000 0x4>,
<0x5010 0x4>,
<0x5014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x5000 0x1000>;
dsi1: encoder@0 {
compatible = "ti,omap5-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x40>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@9000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x9000 0x4>,
<0x9010 0x4>,
<0x9014 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
SYSC_OMAP2_ENAWAKEUP |
SYSC_OMAP2_SOFTRESET |
SYSC_OMAP2_AUTOIDLE)>;
ti,syss-mask = <1>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x9000 0x1000>;
dsi2: encoder@0 {
compatible = "ti,omap5-dsi";
reg = <0 0x200>,
<0x200 0x40>,
<0x300 0x40>;
reg-names = "proto", "phy", "pll";
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck";
};
};
target-module@40000 {
compatible = "ti,sysc-omap4", "ti,sysc";
reg = <0x40000 0x4>,
<0x40010 0x4>;
reg-names = "rev", "sysc";
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>,
<SYSC_IDLE_SMART_WKUP>;
ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 8>;
clock-names = "fck", "dss_clk";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x40000 0x40000>;
hdmi: encoder@0 {
compatible = "ti,omap5-hdmi";
reg = <0 0x200>,
<0x200 0x80>,
<0x300 0x80>,
<0x20000 0x19000>;
reg-names = "wp", "pll", "phy", "core";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 9>,
<&dss_clkctrl OMAP5_DSS_CORE_CLKCTRL 10>;
clock-names = "fck", "sys_clk";
dmas = <&sdma 76>;
dma-names = "audio_tx";
};
};
};
};
abb_mpu: regulator-abb-mpu {
compatible = "ti,abb-v2";
regulator-name = "abb_mpu";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
<0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
reg-names = "base-address", "int-address",
"efuse-address", "ldo-address";
ti,tranxdone-status-mask = <0x80>;
/* LDOVBBMPU_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBMPU_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1060000 0 0x0 0 0x02000000 0x01F00000
1250000 0 0x4 0 0x02000000 0x01F00000
>;
};
abb_mm: regulator-abb-mm {
compatible = "ti,abb-v2";
regulator-name = "abb_mm";
#address-cells = <0>;
#size-cells = <0>;
clocks = <&sys_clkin>;
ti,settling-time = <50>;
ti,clock-cycles = <16>;
reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
<0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
reg-names = "base-address", "int-address",
"efuse-address", "ldo-address";
ti,tranxdone-status-mask = <0x80000000>;
/* LDOVBBMM_MUX_CTRL */
ti,ldovbb-override-mask = <0x400>;
/* LDOVBBMM_VSET_OUT */
ti,ldovbb-vset-mask = <0x1F>;
/*
* NOTE: only FBB mode used but actual vset will
* determine final biasing
*/
ti,abb_info = <
/*uV ABB efuse rbb_m fbb_m vset_m*/
1025000 0 0x0 0 0x02000000 0x01F00000
1120000 0 0x4 0 0x02000000 0x01F00000
>;
};
};
};
&cpu_thermal {
polling-delay = <500>; /* milliseconds */
coefficients = <65 (-1791)>;
};
#include "omap5-l4.dtsi"
#include "omap54xx-clocks.dtsi"
&gpu_thermal {
coefficients = <117 (-2992)>;
};
&core_thermal {
coefficients = <0 2000>;
};
#include "omap5-l4-abe.dtsi"
#include "omap54xx-clocks.dtsi"
&prm {
prm_dsp: prm@400 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x400 0x100>;
#reset-cells = <1>;
};
prm_core: prm@700 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x700 0x100>;
#reset-cells = <1>;
};
prm_iva: prm@1200 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1200 0x100>;
#reset-cells = <1>;
};
prm_device: prm@1c00 {
compatible = "ti,omap5-prm-inst", "ti,omap-prm-inst";
reg = <0x1c00 0x100>;
#reset-cells = <1>;
};
};

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// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*/
/*
* Integrated Power Management Chip
* http://www.ti.com/lit/ds/symlink/twl6030.pdf
*/
&twl {
compatible = "ti,twl6030";
interrupt-controller;
#interrupt-cells = <1>;
rtc {
compatible = "ti,twl4030-rtc";
interrupts = <11>;
};
vaux1: regulator-vaux1 {
compatible = "ti,twl6030-vaux1";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vaux2: regulator-vaux2 {
compatible = "ti,twl6030-vaux2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2800000>;
};
vaux3: regulator-vaux3 {
compatible = "ti,twl6030-vaux3";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
};
vmmc: regulator-vmmc {
compatible = "ti,twl6030-vmmc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <3000000>;
};
vpp: regulator-vpp {
compatible = "ti,twl6030-vpp";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2500000>;
};
vusim: regulator-vusim {
compatible = "ti,twl6030-vusim";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2900000>;
};
vdac: regulator-vdac {
compatible = "ti,twl6030-vdac";
};
vana: regulator-vana {
compatible = "ti,twl6030-vana";
};
vcxio: regulator-vcxio {
compatible = "ti,twl6030-vcxio";
regulator-always-on;
};
vusb: regulator-vusb {
compatible = "ti,twl6030-vusb";
};
v1v8: regulator-v1v8 {
compatible = "ti,twl6030-v1v8";
regulator-always-on;
};
v2v1: regulator-v2v1 {
compatible = "ti,twl6030-v2v1";
regulator-always-on;
};
twl_usb_comparator: usb-comparator {
compatible = "ti,twl6030-usb";
interrupts = <4>, <10>;
};
twl_pwm: pwm {
/* provides two PWMs (id 0, 1 for PWM1 and PWM2) */
compatible = "ti,twl6030-pwm";
#pwm-cells = <2>;
};
twl_pwmled: pwmled {
/* provides one PWM (id 0 for Charging indicator LED) */
compatible = "ti,twl6030-pwmled";
#pwm-cells = <2>;
};
gpadc {
compatible = "ti,twl6030-gpadc";
interrupts = <3>;
#io-channel-cells = <1>;
};
};

35
arch/arm/dts/twl6030_omap4.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
*/
&twl {
/*
* On most OMAP4 platforms, the twl6030 IRQ line is connected
* to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
* connected to the fref_clk0_out.sys_drm_msecure line.
* Therefore, configure the defaults for the SYS_NIRQ1 and
* fref_clk0_out.sys_drm_msecure pins here.
*/
pinctrl-names = "default";
pinctrl-0 = <
&twl6030_pins
&twl6030_wkup_pins
>;
};
&omap4_pmx_wkup {
twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x054, PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
>;
};
};
&omap4_pmx_core {
twl6030_pins: pinmux_twl6030_pins {
pinctrl-single,pins = <
OMAP4_IOPAD(0x19e, WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
>;
};
};

10
arch/arm/dts/zynqmp-e-a2197-00-revA.dts
View File

@ -2,7 +2,7 @@
/*
* dts file for Xilinx Versal a2197 RevA System Controller
*
* (C) Copyright 2019, Xilinx, Inc.
* (C) Copyright 2019 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
@ -421,14 +421,14 @@
temperature-stability = <50>;
factory-fout = <156250000>;
clock-frequency = <156250000>;
clock-output-names = "si570_hsdp_clk";
clock-output-names = "si570_zsfp_clk";
};
};
i2c@6 { /* USER_SI570_1 */
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
si570_user1_clk: clock-generator@5d { /* u205 */
si570_user1: clock-generator@5d { /* u205 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x5f>;
@ -510,7 +510,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
si570_ddr_dimm2: clock-generator@60 { /* u3 */
si570_lpddr4clk2: clock-generator@60 { /* u3 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;
@ -524,7 +524,7 @@
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
si570_lpddr4: clock-generator@60 { /* u4 */
si570_lpddr4clk1: clock-generator@60 { /* u4 */
#clock-cells = <0>;
compatible = "silabs,si570";
reg = <0x60>;

2
arch/arm/dts/zynqmp-mini-qspi.dts
View File

@ -70,7 +70,7 @@
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <10000000>;
spi-max-frequency = <108000000>;
};
};

117
arch/arm/dts/zynqmp-topic-miamimp-xilinx-xdp-v1r1.dts Normal file
View File

@ -0,0 +1,117 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* dts file for Topic XDP (Xilinx Drone Platform)
*
* (C) Copyright 2016, Topic Embedded Products BV
* Mike Looijmans <mike.looijmans@topic.nl>
*/
/dts-v1/;
#include "zynqmp.dtsi"
#include "zynqmp-clk-ccf.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/phy/phy.h>
/ {
model = "Topic Miamimp ZynqMP XDP v1r1";
compatible = "topic,miamimp-xdp-v1r1", "topic,miamimp-xdp",
"topic,miamimp", "xlnx,zynqmp";
aliases {
gpio0 = &gpio;
i2c0 = &i2c0;
i2c1 = &i2c1;
mmc0 = &sdhci0;
mmc1 = &sdhci1;
rtc0 = &rtc;
serial0 = &uart1;
serial1 = &uart0;
serial2 = &dcc;
spi0 = &qspi;
usb0 = &usb0;
};
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
};
&dcc {
status = "okay";
};
&gpio {
status = "okay";
};
&gpu {
status = "okay";
};
&qspi {
status = "okay";
is-dual = <1>;
flash@0 {
compatible = "st,m25p80", "n25q256a";
m25p,fast-read;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-frequency = <166000000>;
#address-cells = <1>;
#size-cells = <1>;
is-dual = <1>;
partition@0 {
label = "qspi-boot-bin";
reg = <0x00000 0x60000>;
};
partition@60000 {
label = "qspi-u-boot-itb";
reg = <0x60000 0x100000>;
};
partition@160000 {
label = "qspi-u-boot-env";
reg = <0x160000 0x20000>;
};
partition@200000 {
label = "qspi-rootfs";
reg = <0x200000 0x1e00000>;
};
};
};
&rtc {
status = "okay";
};
/* eMMC device */
&sdhci0 {
status = "okay";
non-removable;
disable-wp; /* We don't have a write-protect detection */
bus-width = <8>;
xlnx,mio_bank = <0>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
xlnx,mio_bank = <1>;
disable-wp; /* We don't have a write-protect detection */
bus-width = <4>;
};
&uart0 {
status = "okay";
};
&uart1 {
status = "okay";
};

1
arch/arm/lib/Makefile
View File

@ -43,6 +43,7 @@ obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o
obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o
obj-$(CONFIG_SEMIHOSTING) += semihosting.o
obj-y += bdinfo.o
obj-y += sections.o
obj-y += stack.o
ifdef CONFIG_CPU_V7M

51
arch/arm/lib/bdinfo.c Normal file
View File

@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* ARM-specific information for the 'bd' command
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
void arch_print_bdinfo(void)
{
bd_t *bd = gd->bd;
bdinfo_print_num("arch_number", bd->bi_arch_number);
#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
if (gd->arch.secure_ram & MEM_RESERVE_SECURE_SECURED) {
bdinfo_print_num("Secure ram",
gd->arch.secure_ram &
MEM_RESERVE_SECURE_ADDR_MASK);
}
#endif
#ifdef CONFIG_RESV_RAM
if (gd->arch.resv_ram)
bdinfo_print_num("Reserved ram", gd->arch.resv_ram);
#endif
#if !(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
bdinfo_print_num("TLB addr", gd->arch.tlb_addr);
#endif
bdinfo_print_num("irq_sp", gd->irq_sp); /* irq stack pointer */
bdinfo_print_num("sp start ", gd->start_addr_sp);
/*
* TODO: Currently only support for davinci SOC's is added.
* Remove this check once all the board implement this.
*/
#ifdef CONFIG_CLOCKS
printf("ARM frequency = %ld MHz\n", bd->bi_arm_freq);
printf("DSP frequency = %ld MHz\n", bd->bi_dsp_freq);
printf("DDR frequency = %ld MHz\n", bd->bi_ddr_freq);
#endif
#ifdef CONFIG_BOARD_TYPES
printf("Board Type = %ld\n", gd->board_type);
#endif
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
printf("Early malloc usage: %lx / %x\n", gd->malloc_ptr,
CONFIG_VAL(SYS_MALLOC_F_LEN));
#endif
}

2
arch/arm/mach-at91/include/mach/at91rm9200.h
View File

@ -5,8 +5,6 @@
#ifndef __AT91RM9200_H__
#define __AT91RM9200_H__
#define CONFIG_AT91_GPIO /* and require always gpio features */
/* Periperial Identifiers */
#define ATMEL_ID_SYS 1 /* System Peripheral */

7
arch/arm/mach-davinci/include/mach/sdmmc_defs.h
View File

@ -152,6 +152,13 @@ struct davinci_mmc {
struct mmc_config cfg;
};
#define DAVINCI_MAX_BLOCKS (32)
struct davinci_mmc_plat {
struct davinci_mmc_regs *reg_base; /* Register base address */
struct mmc_config cfg;
struct mmc mmc;
};
int davinci_mmc_init(bd_t *bis, struct davinci_mmc *host);
#endif /* _SDMMC_DEFS_H */

2
arch/arm/mach-imx/Kconfig
View File

@ -52,6 +52,8 @@ config IMX_HAB
config CSF_SIZE
hex "Maximum size for Command Sequence File (CSF) binary"
depends on IMX_HAB
default 0x2000 if ARCH_IMX8M
default 0x2060
help
Define the maximum size for Command Sequence File (CSF) binary

2
arch/arm/mach-imx/spl_qspi.cfg
View File

@ -12,6 +12,6 @@ BOOT_FROM qspi
/*
* Secure boot support
*/
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif

1
arch/arm/mach-omap2/Kconfig
View File

@ -181,7 +181,6 @@ source "board/BuR/brppt1/Kconfig"
source "board/siemens/draco/Kconfig"
source "board/siemens/pxm2/Kconfig"
source "board/siemens/rut/Kconfig"
source "board/ti/ti814x/Kconfig"
source "board/ti/ti816x/Kconfig"
source "board/ti/am43xx/Kconfig"
source "board/ti/am335x/Kconfig"

2
arch/arm/mach-socfpga/include/mach/misc.h
View File

@ -20,7 +20,7 @@ extern struct bsel bsel_str[];
#ifdef CONFIG_FPGA
void socfpga_fpga_add(void *fpga_desc);
#else
inline void socfpga_fpga_add(void *fpga_desc) {}
static inline void socfpga_fpga_add(void *fpga_desc) {}
#endif
#ifdef CONFIG_TARGET_SOCFPGA_GEN5

1
arch/arm/mach-tegra/Kconfig
View File

@ -58,7 +58,6 @@ config TEGRA_COMMON
select MISC
select OF_CONTROL
select SPI
select VIDCONSOLE_AS_LCD if DM_VIDEO
imply CMD_DM
imply CRC32_VERIFY

20
arch/arm/mach-tegra/ivc.c
View File

@ -124,11 +124,11 @@ static inline int tegra_ivc_channel_empty(struct tegra_ivc *ivc,
{
/*
* This function performs multiple checks on the same values with
* security implications, so create snapshots with ACCESS_ONCE() to
* security implications, so create snapshots with READ_ONCE() to
* ensure that these checks use the same values.
*/
uint32_t w_count = ACCESS_ONCE(ch->w_count);
uint32_t r_count = ACCESS_ONCE(ch->r_count);
uint32_t w_count = READ_ONCE(ch->w_count);
uint32_t r_count = READ_ONCE(ch->r_count);
/*
* Perform an over-full check to prevent denial of service attacks where
@ -153,14 +153,14 @@ static inline int tegra_ivc_channel_full(struct tegra_ivc *ivc,
* Invalid cases where the counters indicate that the queue is over
* capacity also appear full.
*/
return (ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count)) >=
return (READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count)) >=
ivc->nframes;
}
static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
{
ACCESS_ONCE(ivc->rx_channel->r_count) =
ACCESS_ONCE(ivc->rx_channel->r_count) + 1;
WRITE_ONCE(ivc->rx_channel->r_count,
READ_ONCE(ivc->rx_channel->r_count) + 1);
if (ivc->r_pos == ivc->nframes - 1)
ivc->r_pos = 0;
@ -170,8 +170,8 @@ static inline void tegra_ivc_advance_rx(struct tegra_ivc *ivc)
static inline void tegra_ivc_advance_tx(struct tegra_ivc *ivc)
{
ACCESS_ONCE(ivc->tx_channel->w_count) =
ACCESS_ONCE(ivc->tx_channel->w_count) + 1;
WRITE_ONCE(ivc->tx_channel->w_count,
READ_ONCE(ivc->tx_channel->w_count) + 1);
if (ivc->w_pos == ivc->nframes - 1)
ivc->w_pos = 0;
@ -232,7 +232,7 @@ static inline uint32_t tegra_ivc_channel_avail_count(struct tegra_ivc *ivc,
* comment in tegra_ivc_channel_empty() for an explanation about
* special over-full considerations.
*/
return ACCESS_ONCE(ch->w_count) - ACCESS_ONCE(ch->r_count);
return READ_ONCE(ch->w_count) - READ_ONCE(ch->r_count);
}
int tegra_ivc_read_get_next_frame(struct tegra_ivc *ivc, void **frame)
@ -358,7 +358,7 @@ int tegra_ivc_channel_notified(struct tegra_ivc *ivc)
/* Copy the receiver's state out of shared memory. */
offset = offsetof(struct tegra_ivc_channel_header, w_count);
tegra_ivc_invalidate_counter(ivc, ivc->rx_channel, offset);
peer_state = ACCESS_ONCE(ivc->rx_channel->state);
peer_state = READ_ONCE(ivc->rx_channel->state);
if (peer_state == ivc_state_sync) {
/*

4
arch/m68k/config.mk
View File

@ -3,10 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := m68k-elf-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x20000
PLATFORM_CPPFLAGS += -D__M68K__

1
arch/m68k/lib/Makefile
View File

@ -7,6 +7,7 @@
## if the user asked for it
lib-$(CONFIG_USE_PRIVATE_LIBGCC) += lshrdi3.o muldi3.o ashldi3.o
obj-y += bdinfo.o
obj-$(CONFIG_CMD_BOOTM) += bootm.o
obj-y += cache.o
obj-y += interrupts.o

34
arch/m68k/lib/bdinfo.c Normal file
View File

@ -0,0 +1,34 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PPC-specific information for the 'bd' command
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
void arch_print_bdinfo(void)
{
bd_t *bd = gd->bd;
#if defined(CONFIG_SYS_INIT_RAM_ADDR)
bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
#endif
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_SYS_MBAR)
bdinfo_print_num("mbar", bd->bi_mbar_base);
#endif
bdinfo_print_mhz("cpufreq", bd->bi_intfreq);
if (IS_ENABLED(CONFIG_PCI))
bdinfo_print_mhz("pcifreq", bd->bi_pcifreq);
#ifdef CONFIG_EXTRA_CLOCK
bdinfo_print_mhz("flbfreq", bd->bi_flbfreq);
bdinfo_print_mhz("inpfreq", bd->bi_inpfreq);
bdinfo_print_mhz("vcofreq", bd->bi_vcofreq);
#endif
}

4
arch/microblaze/config.mk
View File

@ -6,10 +6,6 @@
# (C) Copyright 2004 Atmark Techno, Inc.
# Yasushi SHOJI <yashi@atmark-techno.com>
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := mb-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x80F00000
PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__

4
arch/nds32/config.mk
View File

@ -8,10 +8,6 @@
# Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
#
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := nds32le-linux-
endif
CONFIG_STANDALONE_LOAD_ADDR = 0x300000
LDFLAGS_STANDALONE += -T $(srctree)/examples/standalone/nds32.lds

20
arch/nds32/include/asm/u-boot.h
View File

@ -19,26 +19,10 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/u-boot-nds32.h>
typedef struct bd_info {
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned char bi_enetaddr[6];
struct /* RAM configuration */
{
unsigned long start;
unsigned long size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_NDS32

4
arch/nios2/config.mk
View File

@ -4,10 +4,6 @@
# Psyent Corporation <www.psyent.com>
# Scott McNutt <smcnutt@psyent.com>
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := nios2-elf-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x02000000
PLATFORM_CPPFLAGS += -D__NIOS2__

4
arch/powerpc/config.mk
View File

@ -3,10 +3,6 @@
# (C) Copyright 2000-2010
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := ppc_8xx-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000
LDFLAGS_FINAL += --gc-sections
LDFLAGS_FINAL += --bss-plt

108
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -24,45 +24,6 @@ config TARGET_SOCRATES
bool "Support socrates"
select ARCH_MPC8544
config TARGET_B4420QDS
bool "Support B4420QDS"
select ARCH_B4420
select SUPPORT_SPL
select PHYS_64BIT
imply PANIC_HANG
config TARGET_B4860QDS
bool "Support B4860QDS"
select ARCH_B4860
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE if !SPL_BUILD
imply PANIC_HANG
config TARGET_BSC9131RDB
bool "Support BSC9131RDB"
select ARCH_BSC9131
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
config TARGET_BSC9132QDS
bool "Support BSC9132QDS"
select ARCH_BSC9132
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select BOARD_EARLY_INIT_F
select FSL_DDR_INTERACTIVE
config TARGET_C29XPCIE
bool "Support C29XPCIE"
select ARCH_C29X
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select SUPPORT_TPL
select PHYS_64BIT
imply PANIC_HANG
config TARGET_P3041DS
bool "Support P3041DS"
select PHYS_64BIT
@ -95,14 +56,6 @@ config TARGET_P5040DS
imply CMD_SATA
imply PANIC_HANG
config TARGET_MPC8536DS
bool "Support MPC8536DS"
select ARCH_MPC8536
# Use DDR3 controller with DDR2 DIMMs on this board
select SYS_FSL_DDRC_GEN3
imply CMD_SATA
imply FSL_SATA
config TARGET_MPC8541CDS
bool "Support MPC8541CDS"
select ARCH_MPC8541
@ -156,14 +109,6 @@ config TARGET_P1010RDB_PB
imply CMD_SATA
imply PANIC_HANG
config TARGET_P1022DS
bool "Support P1022DS"
select ARCH_P1022
select SUPPORT_SPL
select SUPPORT_TPL
imply CMD_SATA
imply FSL_SATA
config TARGET_P1023RDB
bool "Support P1023RDB"
select ARCH_P1023
@ -243,10 +188,6 @@ config TARGET_P2020RDB
imply CMD_SATA
imply SATA_SIL
config TARGET_P1_TWR
bool "Support p1_twr"
select ARCH_P1025
config TARGET_P2041RDB
bool "Support P2041RDB"
select ARCH_P2041
@ -260,16 +201,6 @@ config TARGET_QEMU_PPCE500
select ARCH_QEMU_E500
select PHYS_64BIT
config TARGET_T1024QDS
bool "Support T1024QDS"
select ARCH_T1024
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_EEPROM
imply CMD_SATA
imply FSL_SATA
config TARGET_T1023RDB
bool "Support T1023RDB"
select ARCH_T1023
@ -290,16 +221,6 @@ config TARGET_T1024RDB
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_T1040QDS
bool "Support T1040QDS"
select ARCH_T1040
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply CMD_SATA
imply PANIC_HANG
config TARGET_T1040RDB
bool "Support T1040RDB"
select ARCH_T1040
@ -371,15 +292,6 @@ config TARGET_T2081QDS
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
select FSL_DDR_INTERACTIVE
config TARGET_T4160QDS
bool "Support T4160QDS"
select ARCH_T4160
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
imply CMD_SATA
imply PANIC_HANG
config TARGET_T4160RDB
bool "Support T4160RDB"
select ARCH_T4160
@ -387,16 +299,6 @@ config TARGET_T4160RDB
select PHYS_64BIT
imply PANIC_HANG
config TARGET_T4240QDS
bool "Support T4240QDS"
select ARCH_T4240
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
imply CMD_SATA
imply PANIC_HANG
config TARGET_T4240RDB
bool "Support T4240RDB"
select ARCH_T4240
@ -1595,12 +1497,7 @@ config SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to
eLBC controller).
source "board/freescale/b4860qds/Kconfig"
source "board/freescale/bsc9131rdb/Kconfig"
source "board/freescale/bsc9132qds/Kconfig"
source "board/freescale/c29xpcie/Kconfig"
source "board/freescale/corenet_ds/Kconfig"
source "board/freescale/mpc8536ds/Kconfig"
source "board/freescale/mpc8541cds/Kconfig"
source "board/freescale/mpc8544ds/Kconfig"
source "board/freescale/mpc8548cds/Kconfig"
@ -1609,19 +1506,14 @@ source "board/freescale/mpc8568mds/Kconfig"
source "board/freescale/mpc8569mds/Kconfig"
source "board/freescale/mpc8572ds/Kconfig"
source "board/freescale/p1010rdb/Kconfig"
source "board/freescale/p1022ds/Kconfig"
source "board/freescale/p1023rdb/Kconfig"
source "board/freescale/p1_p2_rdb_pc/Kconfig"
source "board/freescale/p1_twr/Kconfig"
source "board/freescale/p2041rdb/Kconfig"
source "board/freescale/qemu-ppce500/Kconfig"
source "board/freescale/t102xqds/Kconfig"
source "board/freescale/t102xrdb/Kconfig"
source "board/freescale/t1040qds/Kconfig"
source "board/freescale/t104xrdb/Kconfig"
source "board/freescale/t208xqds/Kconfig"
source "board/freescale/t208xrdb/Kconfig"
source "board/freescale/t4qds/Kconfig"
source "board/freescale/t4rdb/Kconfig"
source "board/gdsys/p1022/Kconfig"
source "board/keymile/Kconfig"

2
arch/powerpc/lib/Makefile
View File

@ -15,6 +15,8 @@ MINIMAL=y
endif
endif
obj-y += bdinfo.o
ifdef MINIMAL
obj-y += cache.o time.o
ifndef CONFIG_TIMER

46
arch/powerpc/lib/bdinfo.c Normal file
View File

@ -0,0 +1,46 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PPC-specific information for the 'bd' command
*
* (C) Copyright 2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <init.h>
DECLARE_GLOBAL_DATA_PTR;
void __weak board_detail(void)
{
/* Please define board_detail() for your PPC platform */
}
void arch_print_bdinfo(void)
{
bd_t *bd = gd->bd;
#if defined(CONFIG_SYS_INIT_RAM_ADDR)
bdinfo_print_num("sramstart", (ulong)bd->bi_sramstart);
bdinfo_print_num("sramsize", (ulong)bd->bi_sramsize);
#endif
bdinfo_print_mhz("busfreq", bd->bi_busfreq);
#if defined(CONFIG_MPC8xx) || defined(CONFIG_E500)
bdinfo_print_num("immr_base", bd->bi_immr_base);
#endif
bdinfo_print_num("bootflags", bd->bi_bootflags);
bdinfo_print_mhz("intfreq", bd->bi_intfreq);
#ifdef CONFIG_ENABLE_36BIT_PHYS
if (IS_ENABLED(CONFIG_PHYS_64BIT))
puts("addressing = 36-bit\n");
else
puts("addressing = 32-bit\n");
#endif
board_detail();
#if defined(CONFIG_CPM2)
bdinfo_print_mhz("cpmfreq", bd->bi_cpmfreq);
bdinfo_print_mhz("vco", bd->bi_vco);
bdinfo_print_mhz("sccfreq", bd->bi_sccfreq);
bdinfo_print_mhz("brgfreq", bd->bi_brgfreq);
#endif
}

14
arch/riscv/Kconfig
View File

@ -20,6 +20,9 @@ config TARGET_QEMU_VIRT
config TARGET_SIFIVE_FU540
bool "Support SiFive FU540 Board"
config TARGET_SIPEED_MAIX
bool "Support Sipeed Maix Board"
endchoice
config SYS_ICACHE_OFF
@ -53,6 +56,7 @@ source "board/AndesTech/ax25-ae350/Kconfig"
source "board/emulation/qemu-riscv/Kconfig"
source "board/microchip/mpfs_icicle/Kconfig"
source "board/sifive/fu540/Kconfig"
source "board/sipeed/maix/Kconfig"
# platform-specific options below
source "arch/riscv/cpu/ax25/Kconfig"
@ -269,6 +273,16 @@ config XIP
config SHOW_REGS
bool "Show registers on unhandled exception"
config RISCV_PRIV_1_9
bool "Use version 1.9 of the RISC-V priviledged specification"
help
Older versions of the RISC-V priviledged specification had
separate counter enable CSRs for each privilege mode. Writing
to the unified mcounteren CSR on a processor implementing the
old specification will result in an illegal instruction
exception. In addition to counter CSR changes, the way virtual
memory is configured was also changed.
config STACK_SIZE_SHIFT
int
default 14

15
arch/riscv/cpu/cpu.c
View File

@ -91,13 +91,28 @@ int arch_cpu_init_dm(void)
* Enable perf counters for cycle, time,
* and instret counters only
*/
#ifdef CONFIG_RISCV_PRIV_1_9
csr_write(CSR_MSCOUNTEREN, GENMASK(2, 0));
csr_write(CSR_MUCOUNTEREN, GENMASK(2, 0));
#else
csr_write(CSR_MCOUNTEREN, GENMASK(2, 0));
#endif
/* Disable paging */
if (supports_extension('s'))
#ifdef CONFIG_RISCV_PRIV_1_9
csr_read_clear(CSR_MSTATUS, SR_VM);
#else
csr_write(CSR_SATP, 0);
#endif
}
#ifdef CONFIG_SMP
ret = riscv_init_ipi();
if (ret)
return ret;
#endif
return 0;
}

2
arch/riscv/cpu/start.S
View File

@ -65,6 +65,8 @@ _start:
#else
li t0, SIE_SSIE
#endif
/* Clear any pending IPIs */
csrc MODE_PREFIX(ip), t0
csrs MODE_PREFIX(ie), t0
#endif

1
arch/riscv/dts/Makefile
View File

@ -2,6 +2,7 @@
dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_SIFIVE_FU540) += hifive-unleashed-a00.dtb
dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
targets += $(dtb-y)

4
arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
View File

@ -8,6 +8,10 @@
/ {
aliases {
cpu1 = &cpu1;
cpu2 = &cpu2;
cpu3 = &cpu3;
cpu4 = &cpu4;
spi0 = &qspi0;
spi2 = &qspi2;
};

47
arch/riscv/dts/k210-maix-bit.dts Normal file
View File

@ -0,0 +1,47 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
*/
/dts-v1/;
#include "k210.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Sipeed Maix Bit 2.0";
compatible = "sipeed,maix-bitm", "sipeed,maix-bit", "kendryte,k210";
chosen {
stdout-path = "serial0:115200";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
status = "disabled";
simple-audio-card,cpu {
sound-dai = <&i2s0 0>;
};
simple-audio-card,codec {
sound-dai = <&mic>;
};
};
mic: mic {
#sound-dai-cells = <0>;
compatible = "memsensing,msm61s4030h0";
status = "disabled";
};
};
&uarths0 {
status = "okay";
};
&i2s0 {
#sound-dai-cells = <1>;
};

594
arch/riscv/dts/k210.dtsi Normal file
View File

@ -0,0 +1,594 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
*/
#include <dt-bindings/clock/k210-sysctl.h>
#include <dt-bindings/mfd/k210-sysctl.h>
#include <dt-bindings/reset/k210-sysctl.h>
/ {
/*
* Although the K210 is a 64-bit CPU, the address bus is only 32-bits
* wide, and the upper half of all addresses is ignored.
*/
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210";
aliases {
dma0 = &dmac0;
gpio0 = &gpio0;
gpio1 = &gpio1_0;
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
pinctrl0 = &fpioa;
serial0 = &uarths0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
spi0 = &spi0;
spi1 = &spi1;
spi2 = &spi2;
spi3 = &spi3;
timer0 = &timer0;
timer1 = &timer1;
timer2 = &timer2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <7800000>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "kendryte,k210", "sifive,rocket0", "riscv";
reg = <0>;
riscv,isa = "rv64imafdgc";
mmu-type = "sv39";
i-cache-block-size = <64>;
i-cache-size = <0x8000>;
d-cache-block-size = <64>;
d-cache-size = <0x8000>;
clocks = <&sysclk K210_CLK_CPU>;
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "kendryte,k210", "sifive,rocket0", "riscv";
reg = <1>;
riscv,isa = "rv64imafdgc";
mmu-type = "sv39";
i-cache-block-size = <64>;
i-cache-size = <0x8000>;
d-cache-block-size = <64>;
d-cache-size = <0x8000>;
clocks = <&sysclk K210_CLK_CPU>;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
};
sram: memory@80000000 {
device_type = "memory";
compatible = "kendryte,k210-sram";
reg = <0x80000000 0x400000>,
<0x80400000 0x200000>,
<0x80600000 0x200000>;
reg-names = "sram0", "sram1", "airam";
clocks = <&sysclk K210_CLK_SRAM0>,
<&sysclk K210_CLK_SRAM1>,
<&sysclk K210_CLK_PLL1>;
clock-names = "sram0", "sram1", "airam";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ai_reserved: ai@80600000 {
reg = <0x80600000 0x200000>;
reusable;
};
};
clocks {
in0: osc {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210-soc", "simple-bus";
ranges;
interrupt-parent = <&plic0>;
debug0: debug@0 {
compatible = "kendryte,k210-debug", "riscv,debug";
reg = <0x0 0x1000>;
};
rom0: nvmem@1000 {
reg = <0x1000 0x1000>;
read-only;
};
clint0: interrupt-controller@2000000 {
#interrupt-cells = <1>;
compatible = "kendryte,k210-clint", "riscv,clint0";
reg = <0x2000000 0xC000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
<&cpu1_intc 3>, <&cpu1_intc 7>;
clocks = <&sysclk K210_CLK_CPU>;
};
plic0: interrupt-controller@C000000 {
#interrupt-cells = <1>;
compatible = "kendryte,k210-plic", "riscv,plic0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
<&cpu1_intc 9>, <&cpu1_intc 11>;
riscv,ndev = <65>;
riscv,max-priority = <7>;
};
uarths0: serial@38000000 {
compatible = "kendryte,k210-uarths", "sifive,uart0";
reg = <0x38000000 0x1000>;
interrupts = <33>;
clocks = <&sysclk K210_CLK_CPU>;
status = "disabled";
};
gpio0: gpio-controller@38001000 {
#interrupt-cells = <2>;
#gpio-cells = <2>;
compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
interrupts = <34 35 36 37 38 39 40 41
42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57
58 59 60 61 62 63 64 65>;
gpio-controller;
ngpios = <32>;
status = "disabled";
};
kpu0: kpu@40800000 {
compatible = "kendryte,k210-kpu";
reg = <0x40800000 0xc00000>;
interrupts = <25>;
clocks = <&sysclk K210_CLK_AI>;
memory-region = <&ai_reserved>;
status = "disabled";
};
fft0: fft@42000000 {
compatible = "kendryte,k210-fft";
reg = <0x42000000 0x400000>;
interrupts = <26>;
clocks = <&sysclk K210_CLK_FFT>;
resets = <&sysrst K210_RST_FFT>;
status = "disabled";
};
dmac0: dma-controller@50000000 {
compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
interrupts = <27 28 29 30 31 32>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
resets = <&sysrst K210_RST_DMA>;
dma-channels = <6>;
snps,dma-masters = <2>;
snps,data-width = <5>;
snps,block-size = <0x400000 0x400000 0x400000
0x400000 0x400000 0x400000>;
snps,axi-max-burst-len = <256>;
status = "disabled";
};
apb0: bus@50200000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB0>;
gpio1: gpio-controller@50200000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-gpio",
"snps,dw-apb-gpio";
reg = <0x50200000 0x80>;
clocks = <&sysclk K210_CLK_GPIO>;
resets = <&sysrst K210_RST_GPIO>;
status = "disabled";
gpio1_0: gpio1@0 {
#gpio-cells = <2>;
#interrupt-cells = <2>;
compatible = "snps,dw-apb-gpio-port";
reg = <0>;
interrupt-controller;
interrupts = <23>;
gpio-controller;
snps,nr-gpios = <8>;
};
};
uart1: serial@50210000 {
compatible = "kendryte,k210-uart",
"snps,dw-apb-uart";
reg = <0x50210000 0x100>;
interrupts = <11>;
clocks = <&sysclk K210_CLK_UART1>;
resets = <&sysrst K210_RST_UART1>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
status = "disabled";
};
uart2: serial@50220000 {
compatible = "kendryte,k210-uart",
"snps,dw-apb-uart";
reg = <0x50220000 0x100>;
interrupts = <12>;
clocks = <&sysclk K210_CLK_UART2>;
resets = <&sysrst K210_RST_UART2>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
status = "disabled";
};
uart3: serial@50230000 {
compatible = "kendryte,k210-uart",
"snps,dw-apb-uart";
reg = <0x50230000 0x100>;
interrupts = <13>;
clocks = <&sysclk K210_CLK_UART3>;
resets = <&sysrst K210_RST_UART3>;
reg-io-width = <4>;
reg-shift = <2>;
dcd-override;
dsr-override;
cts-override;
ri-override;
status = "disabled";
};
spi2: spi@50240000 {
compatible = "kendryte,k120-spislave",
"snps,dw-apb-ssi";
spi-slave;
reg = <0x50240000 0x100>;
interrupts = <2>;
clocks = <&sysclk K210_CLK_SPI2>;
resets = <&sysrst K210_RST_SPI2>;
spi-max-frequency = <25000000>;
status = "disabled";
};
i2s0: i2s@50250000 {
compatible = "kendryte,k210-i2s",
"snps,designware-i2s";
reg = <0x50250000 0x200>;
interrupts = <5>;
clocks = <&sysclk K210_CLK_I2S0>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S0>;
status = "disabled";
};
apu0: sound@520250200 {
compatible = "kendryte,k210-apu";
reg = <0x50250200 0x200>;
status = "disabled";
};
i2s1: i2s@50260000 {
compatible = "kendryte,k210-i2s",
"snps,designware-i2s";
reg = <0x50260000 0x200>;
interrupts = <6>;
clocks = <&sysclk K210_CLK_I2S1>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S1>;
status = "disabled";
};
i2s2: i2s@50270000 {
compatible = "kendryte,k210-i2s",
"snps,designware-i2s";
reg = <0x50270000 0x200>;
interrupts = <7>;
clocks = <&sysclk K210_CLK_I2S2>;
clock-names = "i2sclk";
resets = <&sysrst K210_RST_I2S2>;
status = "disabled";
};
i2c0: i2c@50280000 {
compatible = "kendryte,k210-i2c",
"snps,designware-i2c";
reg = <0x50280000 0x100>;
interrupts = <8>;
clocks = <&sysclk K210_CLK_I2C0>;
resets = <&sysrst K210_RST_I2C0>;
status = "disabled";
};
i2c1: i2c@50290000 {
compatible = "kendryte,k210-i2c",
"snps,designware-i2c";
reg = <0x50290000 0x100>;
interrupts = <9>;
clocks = <&sysclk K210_CLK_I2C1>;
resets = <&sysrst K210_RST_I2C1>;
status = "disabled";
};
i2c2: i2c@502A0000 {
compatible = "kendryte,k210-i2c",
"snps,designware-i2c";
reg = <0x502A0000 0x100>;
interrupts = <10>;
clocks = <&sysclk K210_CLK_I2C2>;
resets = <&sysrst K210_RST_I2C2>;
status = "disabled";
};
fpioa: pinmux@502B0000 {
compatible = "kendryte,k210-fpioa";
reg = <0x502B0000 0x100>;
clocks = <&sysclk K210_CLK_FPIOA>;
resets = <&sysrst K210_RST_FPIOA>;
status = "disabled";
};
sha256: sha256@502C0000 {
compatible = "kendryte,k210-sha256";
reg = <0x502C0000 0x100>;
clocks = <&sysclk K210_CLK_SHA>;
resets = <&sysrst K210_RST_SHA>;
status = "disabled";
};
timer0: timer@502D0000 {
compatible = "kendryte,k210-timer",
"snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
interrupts = <14 15>;
clocks = <&sysclk K210_CLK_TIMER0>;
clock-names = "timer";
resets = <&sysrst K210_RST_TIMER0>;
status = "disabled";
};
timer1: timer@502E0000 {
compatible = "kendryte,k210-timer",
"snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
interrupts = <16 17>;
clocks = <&sysclk K210_CLK_TIMER1>;
clock-names = "timer";
resets = <&sysrst K210_RST_TIMER1>;
status = "disabled";
};
timer2: timer@502F0000 {
compatible = "kendryte,k210-timer",
"snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
interrupts = <18 19>;
clocks = <&sysclk K210_CLK_TIMER2>;
clock-names = "timer";
resets = <&sysrst K210_RST_TIMER2>;
status = "disabled";
};
};
apb1: bus@50400000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB1>;
wdt0: watchdog@50400000 {
compatible = "kendryte,k210-wdt", "snps,dw-wdt";
reg = <0x50400000 0x100>;
interrupts = <21>;
clocks = <&sysclk K210_CLK_WDT0>;
resets = <&sysrst K210_RST_WDT0>;
status = "disabled";
};
wdt1: watchdog@50410000 {
compatible = "kendryte,k210-wdt", "snps,dw-wdt";
reg = <0x50410000 0x100>;
interrupts = <22>;
clocks = <&sysclk K210_CLK_WDT1>;
resets = <&sysrst K210_RST_WDT1>;
status = "disabled";
};
otp0: nvmem@50420000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210-otp";
reg = <0x50420000 0x100>,
<0x88000000 0x20000>;
reg-names = "reg", "mem";
clocks = <&sysclk K210_CLK_ROM>;
resets = <&sysrst K210_RST_ROM>;
read-only;
status = "disabled";
/* Bootloader */
firmware@00000 {
reg = <0x00000 0xC200>;
};
/*
* config string as described in RISC-V
* privileged spec 1.9
*/
config-1-9@1c000 {
reg = <0x1C000 0x1000>;
};
/*
* Device tree containing only registers,
* interrupts, and cpus
*/
fdt@1d000 {
reg = <0x1D000 0x2000>;
};
/* CPU/ROM credits */
credits@1f000 {
reg = <0x1F000 0x1000>;
};
};
dvp0: camera@50430000 {
compatible = "kendryte,k210-dvp";
reg = <0x50430000 0x100>;
interrupts = <24>;
clocks = <&sysclk K210_CLK_DVP>;
resets = <&sysrst K210_RST_DVP>;
status = "disabled";
};
sysctl: syscon@50440000 {
compatible = "kendryte,k210-sysctl",
"syscon", "simple-mfd";
reg = <0x50440000 0x100>;
reg-io-width = <4>;
sysclk: clock-controller {
#clock-cells = <1>;
compatible = "kendryte,k210-clk";
clocks = <&in0>;
};
sysrst: reset-controller {
compatible = "kendryte,k210-rst",
"syscon-reset";
#reset-cells = <1>;
regmap = <&sysctl>;
offset = <K210_SYSCTL_PERI_RESET>;
mask = <0x27FFFFFF>;
assert-high = <1>;
};
reboot {
compatible = "syscon-reboot";
regmap = <&sysctl>;
offset = <K210_SYSCTL_SOFT_RESET>;
mask = <1>;
value = <1>;
};
};
aes0: aes@50450000 {
compatible = "kendryte,k210-aes";
reg = <0x50450000 0x100>;
clocks = <&sysclk K210_CLK_AES>;
resets = <&sysrst K210_RST_AES>;
status = "disabled";
};
rtc: rtc@50460000 {
compatible = "kendryte,k210-rtc";
reg = <0x50460000 0x100>;
clocks = <&in0>;
resets = <&sysrst K210_RST_RTC>;
interrupts = <20>;
status = "disabled";
};
};
apb2: bus@52000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "kendryte,k210-apb", "simple-pm-bus";
ranges;
clocks = <&sysclk K210_CLK_APB2>;
spi0: spi@52000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
reg = <0x52000000 0x100>;
interrupts = <1>;
clocks = <&sysclk K210_CLK_SPI0>;
clock-names = "ssi_clk";
resets = <&sysrst K210_RST_SPI0>;
spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
status = "disabled";
};
spi1: spi@53000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
reg = <0x53000000 0x100>;
interrupts = <2>;
clocks = <&sysclk K210_CLK_SPI1>;
clock-names = "ssi_clk";
resets = <&sysrst K210_RST_SPI1>;
spi-max-frequency = <25000000>;
num-cs = <4>;
reg-io-width = <4>;
status = "disabled";
};
spi3: spi@54000000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "kendryte,k210-spi",
"snps,dw-apb-ssi";
reg = <0x54000000 0x200>;
interrupts = <4>;
clocks = <&sysclk K210_CLK_SPI3>;
clock-names = "ssi_clk";
resets = <&sysrst K210_RST_SPI3>;
/* Could possibly go up to 200 MHz */
spi-max-frequency = <100000000>;
num-cs = <4>;
reg-io-width = <4>;
status = "disabled";
};
};
};
};

40
arch/riscv/include/asm/csr.h
View File

@ -15,7 +15,11 @@
#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
#ifdef CONFIG_RISCV_PRIV_1_9
#define SR_PUM _AC(0x00040000, UL) /* Protect User Memory Access */
#else
#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
#endif
#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
#define SR_FS_OFF _AC(0x00000000, UL)
@ -29,6 +33,22 @@
#define SR_XS_CLEAN _AC(0x00010000, UL)
#define SR_XS_DIRTY _AC(0x00018000, UL)
#ifdef CONFIG_RISCV_PRIV_1_9
#define SR_VM _AC(0x1F000000, UL) /* Virtualization Management */
#define SR_VM_MODE_BARE _AC(0x00000000, UL) /* No translation or protection */
#define SR_VM_MODE_BB _AC(0x01000000, UL) /* Single base-and-bound */
/* Separate instruction and data base-and-bound */
#define SR_VM_MODE_BBID _AC(0x02000000, UL)
#ifndef CONFIG_64BIT
#define SR_VM_MODE_32 _AC(0x08000000, UL)
#define SR_VM_MODE SR_VM_MODE_32
#else
#define SR_VM_MODE_39 _AC(0x09000000, UL)
#define SR_VM_MODE_48 _AC(0x0A000000, UL)
#define SR_VM_MODE SR_VM_MODE_39
#endif
#endif
#ifndef CONFIG_64BIT
#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
#else
@ -36,6 +56,7 @@
#endif
/* SATP flags */
#ifndef CONFIG_RISCV_PRIV_1_9
#ifndef CONFIG_64BIT
#define SATP_PPN _AC(0x003FFFFF, UL)
#define SATP_MODE_32 _AC(0x80000000, UL)
@ -45,6 +66,7 @@
#define SATP_MODE_39 _AC(0x8000000000000000, UL)
#define SATP_MODE SATP_MODE_39
#endif
#endif
/* SCAUSE */
#define SCAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
@ -88,17 +110,35 @@
#define CSR_SCAUSE 0x142
#define CSR_STVAL 0x143
#define CSR_SIP 0x144
#ifdef CONFIG_RISCV_PRIV_1_9
#define CSR_SPTBR 0x180
#else
#define CSR_SATP 0x180
#endif
#define CSR_MSTATUS 0x300
#define CSR_MISA 0x301
#define CSR_MIE 0x304
#define CSR_MTVEC 0x305
#ifdef CONFIG_RISCV_PRIV_1_9
#define CSR_MUCOUNTEREN 0x320
#define CSR_MSCOUNTEREN 0x321
#define CSR_MHCOUNTEREN 0x322
#else
#define CSR_MCOUNTEREN 0x306
#endif
#define CSR_MSCRATCH 0x340
#define CSR_MEPC 0x341
#define CSR_MCAUSE 0x342
#define CSR_MTVAL 0x343
#define CSR_MIP 0x344
#ifdef CONFIG_RISCV_PRIV_1_9
#define CSR_MBASE 0x380
#define CSR_MBOUND 0x381
#define CSR_MIBASE 0x382
#define CSR_MIBOUND 0x383
#define CSR_MDBASE 0x384
#define CSR_MDBOUND 0x385
#endif
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82

2
arch/riscv/include/asm/global_data.h
View File

@ -11,6 +11,8 @@
#define __ASM_GBL_DATA_H
#include <asm/smp.h>
#include <asm/u-boot.h>
#include <compiler.h>
/* Architecture-specific global data */
struct arch_global_data {

43
arch/riscv/include/asm/smp.h
View File

@ -51,4 +51,47 @@ void handle_ipi(ulong hart);
*/
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait);
/**
* riscv_init_ipi() - Initialize inter-process interrupt (IPI) driver
*
* Platform code must provide this function. This function is called once after
* the cpu driver is initialized. No other riscv_*_ipi() calls will be made
* before this function is called.
*
* @return 0 if OK, -ve on error
*/
int riscv_init_ipi(void);
/**
* riscv_send_ipi() - Send inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of receiving hart
* @return 0 if OK, -ve on error
*/
int riscv_send_ipi(int hart);
/**
* riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of hart to be cleared
* @return 0 if OK, -ve on error
*/
int riscv_clear_ipi(int hart);
/**
* riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of hart to be checked
* @pending: Pointer to variable with result of the check,
* 1 if IPI is pending, 0 otherwise
* @return 0 if OK, -ve on error
*/
int riscv_get_ipi(int hart, int *pending);
#endif

19
arch/riscv/include/asm/u-boot.h
View File

@ -18,25 +18,10 @@
#ifndef _U_BOOT_H_
#define _U_BOOT_H_ 1
/* Use the generic board which requires a unified bd_info */
#include <asm-generic/u-boot.h>
#include <asm/u-boot-riscv.h>
typedef struct bd_info {
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
unsigned long bi_memsize; /* size of DRAM memory in bytes */
unsigned long bi_flashstart; /* start of FLASH memory */
unsigned long bi_flashsize; /* size of FLASH memory */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned char bi_enetaddr[6];
struct /* RAM configuration */
{
unsigned long start;
unsigned long size;
} bi_dram[CONFIG_NR_DRAM_BANKS];
} bd_t;
/* For image.h:image_check_target_arch() */
#define IH_ARCH_DEFAULT IH_ARCH_RISCV

34
arch/riscv/lib/andes_plic.c
View File

@ -30,20 +30,6 @@
#define SEND_IPI_TO_HART(hart) (0x80 >> (hart))
DECLARE_GLOBAL_DATA_PTR;
static int init_plic(void);
#define PLIC_BASE_GET(void) \
do { \
long *ret; \
\
if (!gd->arch.plic) { \
ret = syscon_get_first_range(RISCV_SYSCON_PLIC); \
if (IS_ERR(ret)) \
return PTR_ERR(ret); \
gd->arch.plic = ret; \
init_plic(); \
} \
} while (0)
static int enable_ipi(int hart)
{
@ -93,13 +79,21 @@ static int init_plic(void)
return -ENODEV;
}
int riscv_init_ipi(void)
{
long *ret = syscon_get_first_range(RISCV_SYSCON_PLIC);
if (IS_ERR(ret))
return PTR_ERR(ret);
gd->arch.plic = ret;
return init_plic();
}
int riscv_send_ipi(int hart)
{
unsigned int ipi;
unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
PLIC_BASE_GET();
ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
@ -110,8 +104,6 @@ int riscv_clear_ipi(int hart)
{
u32 source_id;
PLIC_BASE_GET();
source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plic, hart));
writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plic, hart));
@ -120,8 +112,6 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
PLIC_BASE_GET();
*pending = readl((void __iomem *)PENDING_REG(gd->arch.plic,
gd->arch.boot_hart));
*pending = !!(*pending & SEND_IPI_TO_HART(hart));

2
arch/riscv/lib/reset.c
View File

@ -7,6 +7,7 @@
#include <command.h>
#include <hang.h>
#ifndef CONFIG_SYSRESET
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
printf("resetting ...\n");
@ -16,3 +17,4 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
return 0;
}
#endif

5
arch/riscv/lib/sbi_ipi.c
View File

@ -8,6 +8,11 @@
#include <asm/encoding.h>
#include <asm/sbi.h>
int riscv_init_ipi(void)
{
return 0;
}
int riscv_send_ipi(int hart)
{
ulong mask;

33
arch/riscv/lib/sifive_clint.c
View File

@ -24,22 +24,8 @@
DECLARE_GLOBAL_DATA_PTR;
#define CLINT_BASE_GET(void) \
do { \
long *ret; \
\
if (!gd->arch.clint) { \
ret = syscon_get_first_range(RISCV_SYSCON_CLINT); \
if (IS_ERR(ret)) \
return PTR_ERR(ret); \
gd->arch.clint = ret; \
} \
} while (0)
int riscv_get_time(u64 *time)
{
CLINT_BASE_GET();
*time = readq((void __iomem *)MTIME_REG(gd->arch.clint));
return 0;
@ -47,17 +33,24 @@ int riscv_get_time(u64 *time)
int riscv_set_timecmp(int hart, u64 cmp)
{
CLINT_BASE_GET();
writeq(cmp, (void __iomem *)MTIMECMP_REG(gd->arch.clint, hart));
return 0;
}
int riscv_init_ipi(void)
{
long *ret = syscon_get_first_range(RISCV_SYSCON_CLINT);
if (IS_ERR(ret))
return PTR_ERR(ret);
gd->arch.clint = ret;
return 0;
}
int riscv_send_ipi(int hart)
{
CLINT_BASE_GET();
writel(1, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
@ -65,8 +58,6 @@ int riscv_send_ipi(int hart)
int riscv_clear_ipi(int hart)
{
CLINT_BASE_GET();
writel(0, (void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;
@ -74,8 +65,6 @@ int riscv_clear_ipi(int hart)
int riscv_get_ipi(int hart, int *pending)
{
CLINT_BASE_GET();
*pending = readl((void __iomem *)MSIP_REG(gd->arch.clint, hart));
return 0;

49
arch/riscv/lib/smp.c
View File

@ -12,38 +12,6 @@
DECLARE_GLOBAL_DATA_PTR;
/**
* riscv_send_ipi() - Send inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of receiving hart
* @return 0 if OK, -ve on error
*/
extern int riscv_send_ipi(int hart);
/**
* riscv_clear_ipi() - Clear inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of hart to be cleared
* @return 0 if OK, -ve on error
*/
extern int riscv_clear_ipi(int hart);
/**
* riscv_get_ipi() - Get status of inter-processor interrupt (IPI)
*
* Platform code must provide this function.
*
* @hart: Hart ID of hart to be checked
* @pending: Pointer to variable with result of the check,
* 1 if IPI is pending, 0 otherwise
* @return 0 if OK, -ve on error
*/
extern int riscv_get_ipi(int hart, int *pending);
static int send_ipi_many(struct ipi_data *ipi, int wait)
{
ofnode node, cpus;
@ -124,7 +92,7 @@ void handle_ipi(ulong hart)
*/
ret = riscv_clear_ipi(hart);
if (ret) {
pr_err("Cannot clear IPI of hart %ld\n", hart);
pr_err("Cannot clear IPI of hart %ld (error %d)\n", hart, ret);
return;
}
@ -133,14 +101,11 @@ void handle_ipi(ulong hart)
int smp_call_function(ulong addr, ulong arg0, ulong arg1, int wait)
{
int ret = 0;
struct ipi_data ipi;
struct ipi_data ipi = {
.addr = addr,
.arg0 = arg0,
.arg1 = arg1,
};
ipi.addr = addr;
ipi.arg0 = arg0;
ipi.arg1 = arg1;
ret = send_ipi_many(&ipi, wait);
return ret;
return send_ipi_many(&ipi, wait);
}

34
arch/sandbox/dts/test.dts
View File

@ -23,8 +23,8 @@
pci0 = &pci0;
pci1 = &pci1;
pci2 = &pci2;
remoteproc1 = &rproc_1;
remoteproc2 = &rproc_2;
remoteproc0 = &rproc_1;
remoteproc1 = &rproc_2;
rtc0 = &rtc_0;
rtc1 = &rtc_1;
spi0 = "/spi@0";
@ -830,6 +830,8 @@
hub {
compatible = "usb-hub";
usb,device-class = <9>;
#address-cells = <1>;
#size-cells = <0>;
hub-emul {
compatible = "sandbox,usb-hub";
#address-cells = <1>;
@ -858,6 +860,13 @@
};
};
usbstor@1 {
reg = <1>;
};
usbstor@3 {
reg = <3>;
};
};
};
@ -1049,6 +1058,27 @@
mdio: mdio-test {
compatible = "sandbox,mdio";
};
pm-bus-test {
compatible = "simple-pm-bus";
clocks = <&clk_sandbox 4>;
power-domains = <&pwrdom 1>;
};
resetc2: syscon-reset {
compatible = "syscon-reset";
#reset-cells = <1>;
regmap = <&syscon0>;
offset = <1>;
mask = <0x27FFFFFF>;
assert-high = <0>;
};
syscon-reset-test {
compatible = "sandbox,misc_sandbox";
resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
reset-names = "valid", "no_mask", "out_of_range";
};
};
#include "sandbox_pmic.dtsi"

1
arch/sandbox/include/asm/clk.h
View File

@ -21,6 +21,7 @@ enum sandbox_clk_id {
SANDBOX_CLK_ID_I2C,
SANDBOX_CLK_ID_UART1,
SANDBOX_CLK_ID_UART2,
SANDBOX_CLK_ID_BUS,
SANDBOX_CLK_ID_COUNT,
};

4
arch/sh/config.mk
View File

@ -3,10 +3,6 @@
# (C) Copyright 2000-2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifeq ($(CROSS_COMPILE),)
CROSS_COMPILE := sh4-linux-
endif
CONFIG_STANDALONE_LOAD_ADDR ?= 0x8C000000
ifeq ($(CPU),sh2)
LDFLAGS_STANDALONE += -EB

2
arch/x86/cpu/apollolake/Makefile
View File

@ -3,7 +3,6 @@
# Copyright 2019 Google LLC
obj-$(CONFIG_SPL_BUILD) += cpu_spl.o
obj-$(CONFIG_SPL_BUILD) += spl.o
obj-$(CONFIG_SPL_BUILD) += systemagent.o
obj-y += cpu_common.o
@ -12,6 +11,7 @@ obj-y += cpu.o
obj-y += punit.o
obj-y += fsp_bindings.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-y += fsp_m.o
endif
endif

2
arch/x86/cpu/config.mk
View File

@ -3,8 +3,6 @@
# (C) Copyright 2002
# Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
CROSS_COMPILE ?= i386-linux-
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START)
LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC)

2
arch/x86/include/asm/atomic.h
View File

@ -23,7 +23,7 @@ typedef struct { volatile int counter; } atomic_t;
*/
static inline int atomic_read(const atomic_t *v)
{
return ACCESS_ONCE((v)->counter);
return READ_ONCE((v)->counter);
}
/**

4
arch/x86/lib/Makefile
View File

@ -22,7 +22,6 @@ obj-y += init_helpers.o
obj-y += interrupts.o
obj-y += lpc-uclass.o
obj-y += mpspec.o
obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-y += northbridge-uclass.o
obj-$(CONFIG_I8259_PIC) += i8259.o
obj-$(CONFIG_I8254_TIMER) += i8254.o
@ -45,9 +44,12 @@ ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_CMD_ZBOOT) += zimage.o
endif
obj-$(CONFIG_USE_HOB) += hob.o
ifndef CONFIG_TPL_BUILD
obj-$(CONFIG_ENABLE_MRC_CACHE) += mrccache.o
obj-$(CONFIG_HAVE_FSP) += fsp/
obj-$(CONFIG_FSP_VERSION1) += fsp1/
obj-$(CONFIG_FSP_VERSION2) += fsp2/
endif
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TPL_BUILD

5
arch/x86/lib/fsp/fsp_graphics.c
View File

@ -98,6 +98,7 @@ static int fsp_video_probe(struct udevice *dev)
* For IGD, it seems to be always on BAR2.
*/
vesa->phys_base_ptr = dm_pci_read_bar32(dev, 2);
gd->fb_base = vesa->phys_base_ptr;
ret = vbe_setup_video_priv(vesa, uc_priv, plat);
if (ret)
@ -106,8 +107,8 @@ static int fsp_video_probe(struct udevice *dev)
mtrr_add_request(MTRR_TYPE_WRCOMB, vesa->phys_base_ptr, 256 << 20);
mtrr_commit(true);
printf("%dx%dx%d\n", uc_priv->xsize, uc_priv->ysize,
vesa->bits_per_pixel);
printf("%dx%dx%d @ %x\n", uc_priv->xsize, uc_priv->ysize,
vesa->bits_per_pixel, vesa->phys_base_ptr);
return 0;

1
arch/xtensa/config.mk
View File

@ -3,7 +3,6 @@
# (C) Copyright 2007 - 2013 Tensilica, Inc.
# (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
CROSS_COMPILE ?= xtensa-linux-
PLATFORM_CPPFLAGS += -D__XTENSA__ -mlongcalls -mforce-no-pic \
-ffunction-sections -fdata-sections

2
board/boundary/nitrogen6x/6x_upgrade.txt
View File

@ -1,4 +1,4 @@
setenv stdout serial,vga
setenv stdout serial,vidconsole
echo "check U-Boot" ;
setenv offset 0x400
if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk}:1 12000000 u-boot.nopadding ; then

5
board/congatec/cgtqmx6eval/cgtqmx6eval.c
View File

@ -627,6 +627,11 @@ int board_video_skip(void)
return 0;
}
int ipu_displays_init(void)
{
return board_video_skip();
}
static void setup_display(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

12
board/davinci/da8xxevm/omapl138_lcdk.c
View File

@ -368,8 +368,20 @@ U_BOOT_DEVICE(omapl138_uart) = {
.platdata = &serial_pdata,
};
static const struct davinci_mmc_plat mmc_platdata = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.cfg = {
.f_min = 200000,
.f_max = 25000000,
.voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
.host_caps = MMC_MODE_4BIT,
.b_max = DAVINCI_MAX_BLOCKS,
.name = "da830-mmc",
},
};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "davinci_mmc",
.platdata = &mmc_platdata,
};
void spl_board_init(void)

2
board/ea/mx7ulp_com/imximage.cfg
View File

@ -28,7 +28,7 @@ BOOT_FROM sd
PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
#else
#ifdef CONFIG_SECURE_BOOT
#ifdef CONFIG_IMX_HAB
CSF CONFIG_CSF_SIZE
#endif
/*

14
board/freescale/b4860qds/Kconfig
View File

@ -1,14 +0,0 @@
if TARGET_B4860QDS || TARGET_B4420QDS
config SYS_BOARD
default "b4860qds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "B4860QDS"
source "board/freescale/common/Kconfig"
endif

17
board/freescale/b4860qds/MAINTAINERS
View File

@ -1,17 +0,0 @@
B4860QDS BOARD
M: Ashish Kumar <ashish.kumar@nxp.com>
S: Maintained
F: board/freescale/b4860qds/
F: include/configs/B4860QDS.h
F: configs/B4420QDS_defconfig
F: configs/B4420QDS_NAND_defconfig
F: configs/B4420QDS_SPIFLASH_defconfig
F: configs/B4860QDS_defconfig
F: configs/B4860QDS_NAND_defconfig
F: configs/B4860QDS_SPIFLASH_defconfig
F: configs/B4860QDS_SRIO_PCIE_BOOT_defconfig
B4860QDS_SECURE_BOOT BOARD
M: Ruchika Gupta <ruchika.gupta@nxp.com>
S: Maintained
F: configs/B4860QDS_SECURE_BOOT_defconfig

16
board/freescale/b4860qds/Makefile
View File

@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright 2012 Freescale Semiconductor, Inc.
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
else
obj-y += b4860qds.o
obj-$(CONFIG_TARGET_B4860QDS) += eth_b4860qds.o
obj-$(CONFIG_TARGET_B4420QDS) += eth_b4860qds.o
obj-$(CONFIG_PCI) += pci.o
endif
obj-y += ddr.o
obj-y += law.o
obj-y += tlb.o

1276
board/freescale/b4860qds/b4860qds.c
View File

File diff suppressed because it is too large Load Diff

12
board/freescale/b4860qds/b4860qds.h
View File

@ -1,12 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#ifndef __CORENET_DS_H__
#define __CORENET_DS_H__
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
#endif

72
board/freescale/b4860qds/b4860qds_crossbar_con.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*/
#ifndef __CROSSBAR_CONNECTIONS_H__
#define __CROSSBAR_CONNECTIONS_H__
#define NUM_CON_VSC3316 8
#define NUM_CON_VSC3308 4
static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
{5, 11}, {4, 5}, {2, 6}, {12, 9} };
static int8_t vsc16_tx_sfp[8][2] = { {15, 7}, {0, 1}, {7, 8}, {9, 0},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static int8_t vsc16_tx_4sfp_sgmii_12_56[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {2, 14}, {12, 15},
{-1, -1}, {-1, -1} };
static const int8_t vsc16_tx_4sfp_sgmii_34[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {5, 14}, {4, 15},
{-1, -1}, {-1, -1} };
static int8_t vsc16_tx_sfp_sgmii_aurora[8][2] = { {15, 7}, {0, 1},
{7, 8}, {9, 0}, {5, 14},
{4, 15}, {2, 12}, {12, 13} };
#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_tx_sgmii_lane_cd[8][2] = { {5, 14}, {4, 15},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
{11, 11}, {5, 10}, {6, 3}, {9, 12} };
static int8_t vsc16_rx_sfp[8][2] = { {8, 15}, {0, 1}, {7, 8}, {1, 9},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static int8_t vsc16_rx_4sfp_sgmii_12_56[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 3}, {15, 12},
{-1, -1}, {-1, -1} };
static const int8_t vsc16_rx_4sfp_sgmii_34[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 11}, {15, 10},
{-1, -1}, {-1, -1} };
static int8_t vsc16_rx_sfp_sgmii_aurora[8][2] = { {8, 15}, {0, 1},
{7, 8}, {1, 9}, {14, 11},
{15, 10}, {13, 3}, {12, 12} };
#ifdef CONFIG_ARCH_B4420
static int8_t vsc16_rx_sgmii_lane_cd[8][2] = { {14, 11}, {15, 10},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
#endif
static const int8_t vsc16_rx_aurora[8][2] = { {13, 3}, {12, 12}, {-1, -1},
{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
static const int8_t vsc08_tx_sfp[4][2] = { {2, 1}, {3, 0}, {7, 6}, {1, 7} };
static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
static const int8_t vsc08_rx_sfp[4][2] = { {1, 3}, {0, 4}, {6, 7}, {7, 1} };
#endif

28
board/freescale/b4860qds/b4860qds_qixis.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2012 Freescale Semiconductor, Inc.
*/
#ifndef __B4860QDS_QIXIS_H__
#define __B4860QDS_QIXIS_H__
/* Definitions of QIXIS Registers for B4860QDS */
/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
#define BRDCFG4_EMISEL_MASK 0xE0
#define BRDCFG4_EMISEL_SHIFT 5
/* CLK */
#define QIXIS_CLK_66 0x0
#define QIXIS_CLK_100 0x1
#define QIXIS_CLK_125 0x2
#define QIXIS_CLK_133 0x3
#define QIXIS_SRDS1CLK_122 0x5a
#define QIXIS_SRDS1CLK_125 0x5e
/* SGMII */
#define PHY_BASE_ADDR 0x18
#define PORT_NUM 0x04
#define REGNUM 0x00
#endif

30
board/freescale/b4860qds/b4_pbi.cfg
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@ -1,30 +0,0 @@
#PBI commands
#Initialize CPC1
09010000 00200400
09138000 00000000
091380c0 00000100
#Configure CPC1 as 512KB SRAM
09010100 00000000
09010104 fff80009
09010f00 08000000
09010000 80000000
#Configure LAW for CPC1
09000d00 00000000
09000d04 fff80000
09000d08 81000012
#Configure alternate space
09000010 00000000
09000014 ff000000
09000018 81000000
#Configure SPI controller
09110000 80000403
09110020 2d170008
09110024 00100008
09110028 00100008
0911002c 00100008
#slowing down the MDC clock to make it <= 2.5 MHZ
094fc030 00008148
094fd030 00008148
#Flush PBL data
09138000 00000000
091380c0 00000000

7
board/freescale/b4860qds/b4_rcw.cfg
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@ -1,7 +0,0 @@
#PBL preamble and RCW header
aa55aa55 010e0100
# serdes protocol 0x2A_0x98
140e0018 0f001218 00000000 00000000
54980000 9000a000 e8104000 a9000000
01000000 00000000 00000000 0001b1f8
00000000 14000020 00000000 00000011

267
board/freescale/b4860qds/ddr.c
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// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <i2c.h>
#include <hwconfig.h>
#include <fsl_ddr.h>
#include <init.h>
#include <log.h>
#include <asm/mmu.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
#include <asm/fsl_law.h>
DECLARE_GLOBAL_DATA_PTR;
dimm_params_t ddr_raw_timing = {
.n_ranks = 2,
.rank_density = 2147483648u,
.capacity = 4294967296u,
.primary_sdram_width = 64,
.ec_sdram_width = 8,
.registered_dimm = 0,
.mirrored_dimm = 1,
.n_row_addr = 15,
.n_col_addr = 10,
.n_banks_per_sdram_device = 8,
.edc_config = 2, /* ECC */
.burst_lengths_bitmask = 0x0c,
.tckmin_x_ps = 1071,
.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
.taa_ps = 13910,
.twr_ps = 15000,
.trcd_ps = 13910,
.trrd_ps = 6000,
.trp_ps = 13910,
.tras_ps = 34000,
.trc_ps = 48910,
.trfc_ps = 260000,
.twtr_ps = 7500,
.trtp_ps = 7500,
.refresh_rate_ps = 7800000,
.tfaw_ps = 35000,
};
int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
unsigned int controller_number,
unsigned int dimm_number)
{
const char dimm_model[] = "RAW timing DDR";
if ((controller_number == 0) && (dimm_number == 0)) {
memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
}
return 0;
}
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 wrlvl_start;
u32 wrlvl_ctl_2;
u32 wrlvl_ctl_3;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
* ranks| mhz|adjst| start | ctl2 | ctl3 | |delay |
*/
{2, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
{2, 1666, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
{2, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
{1, 1350, 4, 7, 0x09080807, 0x07060607, 0xff, 2, 0},
{1, 1700, 4, 7, 0x09080806, 0x06050607, 0xff, 2, 0},
{1, 1900, 3, 7, 0x08070706, 0x06040507, 0xff, 2, 0},
{}
};
static const struct board_specific_parameters *udimms[] = {
udimm0,
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
ulong ddr_freq;
if (ctrl_num > 2) {
printf("Not supported controller number %d\n", ctrl_num);
return;
}
if (!pdimm->n_ranks)
return;
pbsp = udimms[0];
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm->n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->clk_adjust = pbsp->clk_adjust;
popts->wrlvl_start = pbsp->wrlvl_start;
popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->wrlvl_start = pbsp_highest->wrlvl_start;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
/*
* Write leveling override
*/
popts->wrlvl_override = 1;
popts->wrlvl_sample = 0xf;
/*
* Rtt and Rtt_WR override
*/
popts->rtt_override = 0;
/* Enable ZQ calibration */
popts->zq_en = 1;
/* DHC_EN =1, ODT = 75 Ohm */
popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
/* optimize cpo for erratum A-009942 */
popts->cpo_sample = 0x3e;
}
int dram_init(void)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
puts("Initializing....using SPD\n");
dram_size = fsl_ddr_sdram();
#else
dram_size = fsl_ddr_sdram_size();
#endif
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
gd->ram_size = dram_size;
return 0;
}
unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
unsigned int dbw_cap_adj[])
{
int i, j;
unsigned long long total_mem, current_mem_base, total_ctlr_mem;
unsigned long long rank_density, ctlr_density = 0;
current_mem_base = 0ull;
total_mem = 0;
/*
* This board has soldered DDR chips. DDRC1 has two rank.
* DDRC2 has only one rank.
* Assigning DDRC2 to lower address and DDRC1 to higher address.
*/
if (pinfo->memctl_opts[0].memctl_interleaving) {
rank_density = pinfo->dimm_params[0][0].rank_density >>
dbw_cap_adj[0];
ctlr_density = rank_density;
debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
rank_density, ctlr_density);
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
case FSL_DDR_CACHE_LINE_INTERLEAVING:
case FSL_DDR_PAGE_INTERLEAVING:
case FSL_DDR_BANK_INTERLEAVING:
case FSL_DDR_SUPERBANK_INTERLEAVING:
total_ctlr_mem = 2 * ctlr_density;
break;
default:
panic("Unknown interleaving mode");
}
pinfo->common_timing_params[i].base_address =
current_mem_base;
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem = current_mem_base + total_ctlr_mem;
debug("ctrl %d base 0x%llx\n", i, current_mem_base);
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
}
} else {
/*
* Simple linear assignment if memory
* controllers are not interleaved.
*/
for (i = CONFIG_SYS_NUM_DDR_CTLRS - 1; i >= 0; i--) {
total_ctlr_mem = 0;
pinfo->common_timing_params[i].base_address =
current_mem_base;
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
/* Compute DIMM base addresses. */
unsigned long long cap =
pinfo->dimm_params[i][j].capacity;
pinfo->dimm_params[i][j].base_address =
current_mem_base;
debug("ctrl %d dimm %d base 0x%llx\n",
i, j, current_mem_base);
current_mem_base += cap;
total_ctlr_mem += cap;
}
debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
pinfo->common_timing_params[i].total_mem =
total_ctlr_mem;
total_mem += total_ctlr_mem;
}
}
debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
return total_mem;
}

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board/freescale/b4860qds/eth_b4860qds.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2012 Freescale Semiconductor, Inc.
* Author: Sandeep Kumar Singh <sandeep@freescale.com>
*/
/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
/*
* This file handles the board muxing between the Fman Ethernet MACs and
* the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
* PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
* The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
* one Fman device on B4860. The SERDES configuration is used to determine
* where the SGMII and XAUI cards exist, and also which Fman MACs are routed
* to which PHYs. So for a given Fman MAC, there is one and only PHY it
* connects to. MACs cannot be routed to PHYs dynamically. This configuration
* is done at boot time by reading SERDES protocol from RCW.
*/
#include <common.h>
#include <log.h>
#include <net.h>
#include <netdev.h>
#include <asm/fsl_serdes.h>
#include <fm_eth.h>
#include <fsl_mdio.h>
#include <malloc.h>
#include <fdt_support.h>
#include <fsl_dtsec.h>
#include "../common/ngpixis.h"
#include "../common/fman.h"
#include "../common/qixis.h"
#include "b4860qds_qixis.h"
#define EMI_NONE 0xFFFFFFFF
#ifdef CONFIG_FMAN_ENET
/*
* Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
* lane at index is mapped to slot number n. A value of '0' will mean
* that the mapping must be determined dynamically, or that the lane maps to
* something other than a board slot
*/
static u8 lane_to_slot[] = {
0, 0, 0, 0,
0, 0, 0, 0,
1, 1, 1, 1,
0, 0, 0, 0
};
/*
* This function initializes the lane_to_slot[] array. It reads RCW to check
* if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
* lane_to_slot[] accordingly
*/
static void initialize_lane_to_slot(void)
{
unsigned int serdes2_prtcl;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
debug("Initializing lane to slot: Serdes2 protocol: %x\n",
serdes2_prtcl);
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: SGMII
* Lanes: E,F: Aur
* Lanes: G,H: SRIO
*/
case 0x91:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: SGMII
* Lanes: C,D: SRIO2
* Lanes: E,F,G,H: XAUI2
*/
case 0x93:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: SGMII
* Lanes: E,F,G,H: XAUI2
*/
case 0x98:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: XAUI2
* Lanes: E,F,G,H: XAUI2
*/
case 0x9a:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: PCI
* Lanes: C,D: SGMII
* Lanes: E,F,G,H: XAUI2
*/
case 0x9e:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B,C,D: PCI
* Lanes: E,F: SGMII 3&4
* Lanes: G,H: XFI
*/
case 0xc2:
/*
* Configuration:
* SERDES: 2
* Lanes: A,B: SGMII
* Lanes: C,D: SRIO2
* Lanes: E,F,G,H: XAUI2
*/
lane_to_slot[12] = 2;
lane_to_slot[13] = lane_to_slot[12];
lane_to_slot[14] = lane_to_slot[12];
lane_to_slot[15] = lane_to_slot[12];
break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
return;
}
#endif /* #ifdef CONFIG_FMAN_ENET */
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
struct memac_mdio_info memac_mdio_info;
struct memac_mdio_info tg_memac_mdio_info;
unsigned int i;
unsigned int serdes1_prtcl, serdes2_prtcl;
int qsgmii;
struct mii_dev *bus;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
if (!serdes1_prtcl) {
printf("SERDES1 is not enabled\n");
return 0;
}
serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
if (!serdes2_prtcl) {
printf("SERDES2 is not enabled\n");
return 0;
}
serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
printf("Initializing Fman\n");
initialize_lane_to_slot();
memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
/* Register the real 1G MDIO bus */
fm_memac_mdio_init(bis, &memac_mdio_info);
tg_memac_mdio_info.regs =
(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
/* Register the real 10G MDIO bus */
fm_memac_mdio_init(bis, &tg_memac_mdio_info);
/*
* Program the two on board DTSEC PHY addresses assuming that they are
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_ARCH_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
printf("Fman: Unsupported SerDes1 Protocol 0x%02x\n",
serdes1_prtcl);
break;
}
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
break;
case 0x48:
case 0x49:
debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
break;
case 0xb1:
case 0xb2:
case 0x8c:
case 0x8d:
debug("Set phy addresses on SGMII Riser for FM1_DTSEC1:%x\n",
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
/*
* XFI does not need a PHY to work, but to make U-Boot
* happy, assign a fake PHY address for a XFI port.
*/
fm_info_set_phy_address(FM1_10GEC1, 0);
fm_info_set_phy_address(FM1_10GEC2, 1);
break;
case 0x98:
/* XAUI in Slot1 and Slot2 */
debug("Set phy address of AMC2PEX-2S for FM1_10GEC1:%x\n",
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC1,
CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
debug("Set phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
case 0x9E:
/* XAUI in Slot2 */
debug("Sett phy address of AMC2PEX-2S for FM1_10GEC2:%x\n",
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2,
CONFIG_SYS_FM1_10GEC2_PHY_ADDR);
break;
default:
printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
serdes2_prtcl);
break;
}
/*set PHY address for QSGMII Riser Card on slot2*/
bus = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
qsgmii = is_qsgmii_riser_card(bus, PHY_BASE_ADDR, PORT_NUM, REGNUM);
if (qsgmii) {
switch (serdes2_prtcl) {
case 0xb2:
case 0x8d:
fm_info_set_phy_address(FM1_DTSEC3, PHY_BASE_ADDR);
fm_info_set_phy_address(FM1_DTSEC4, PHY_BASE_ADDR + 1);
break;
default:
break;
}
}
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_SGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: DTSEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
int idx = i - FM1_10GEC1;
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_XGMII:
fm_info_set_mdio(i,
miiphy_get_dev_by_name
(DEFAULT_FM_TGEC_MDIO_NAME));
break;
case PHY_INTERFACE_MODE_NONE:
fm_info_set_phy_address(i, 0);
break;
default:
printf("Fman1: TGEC%u set to unknown interface %i\n",
idx + 1, fm_info_get_enet_if(i));
fm_info_set_phy_address(i, 0);
break;
}
}
cpu_eth_init(bis);
#endif
return pci_eth_init(bis);
}
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
int phy;
char alias[32];
struct fixed_link f_link;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 prtcl2 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
prtcl2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
phy = fm_info_get_phy_address(port);
sprintf(alias, "phy_sgmii_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
fdt_status_okay_by_alias(fdt, alias);
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
/* check if it's XFI interface for 10g */
switch (prtcl2) {
case 0x80:
case 0x81:
case 0x82:
case 0x83:
case 0x84:
case 0x85:
case 0x86:
case 0x87:
case 0x88:
case 0x89:
case 0x8a:
case 0x8b:
case 0x8c:
case 0x8d:
case 0x8e:
case 0xb1:
case 0xb2:
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
break;
case 0x98: /* XAUI interface */
strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x9e: /* XAUI interface */
case 0x9a:
case 0x93:
case 0x91:
strcpy(alias, "phy_xaui_slot1");
fdt_status_okay_by_alias(fdt, alias);
break;
case 0x97: /* XAUI interface */
case 0xc3:
strcpy(alias, "phy_xaui_slot2");
fdt_status_okay_by_alias(fdt, alias);
break;
default:
break;
}
}
}
/*
* Set status to disabled for unused ethernet node
*/
void fdt_fixup_board_enet(void *fdt)
{
int i;
char alias[32];
for (i = FM1_DTSEC1; i <= FM1_10GEC2; i++) {
switch (fm_info_get_enet_if(i)) {
case PHY_INTERFACE_MODE_NONE:
sprintf(alias, "ethernet%u", i);
fdt_status_disabled_by_alias(fdt, alias);
break;
default:
break;
}
}
}

28
board/freescale/b4860qds/law.c
View File

@ -1,28 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <asm/fsl_law.h>
#include <asm/mmu.h>
struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_BMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
#endif
#ifdef CONFIG_SYS_QMAN_MEM_PHYS
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_IFC),
#endif
};
int num_law_entries = ARRAY_SIZE(law_table);

23
board/freescale/b4860qds/pci.c
View File

@ -1,23 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011-2012 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <command.h>
#include <init.h>
#include <pci.h>
#include <asm/fsl_pci.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <asm/fsl_serdes.h>
void pci_init_board(void)
{
fsl_pcie_init_board(0);
}
void pci_of_setup(void *blob, bd_t *bd)
{
FT_FSL_PCI_SETUP;
}

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