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x86: ivybridge: Enable PCI in early init

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Enable PCI so we can access devices that need to be set up before relocation.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2014-11-12 22:42:13 -07:00
parent 7430f10864
commit 6e5b12b614
4 changed files with 79 additions and 2 deletions
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1
arch/x86/cpu/ivybridge/Makefile
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@ -6,4 +6,5 @@
obj-y += car.o
obj-y += cpu.o
obj-y += pci.o
obj-y += sdram.o

6
arch/x86/cpu/ivybridge/cpu.c
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@ -12,6 +12,7 @@
#include <common.h>
#include <asm/cpu.h>
#include <asm/pci.h>
#include <asm/post.h>
#include <asm/processor.h>
@ -19,6 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
int arch_cpu_init(void)
{
struct pci_controller *hose;
int ret;
post_code(POST_CPU_INIT);
@ -28,6 +30,10 @@ int arch_cpu_init(void)
if (ret)
return ret;
ret = pci_early_init_hose(&hose);
if (ret)
return ret;
return 0;
}

60
arch/x86/cpu/ivybridge/pci.c Normal file
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@ -0,0 +1,60 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* (C) Copyright 2008,2009
* Graeme Russ, <graeme.russ@gmail.com>
*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <pci.h>
#include <asm/pci.h>
static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
struct pci_config_table *table)
{
u8 secondary;
hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
if (secondary != 0)
pci_hose_scan_bus(hose, secondary);
}
static struct pci_config_table pci_ivybridge_config_table[] = {
/* vendor, device, class, bus, dev, func */
{ PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
{}
};
void board_pci_setup_hose(struct pci_controller *hose)
{
hose->config_table = pci_ivybridge_config_table;
hose->first_busno = 0;
hose->last_busno = 0;
/* PCI memory space */
pci_set_region(hose->regions + 0,
CONFIG_PCI_MEM_BUS,
CONFIG_PCI_MEM_PHYS,
CONFIG_PCI_MEM_SIZE,
PCI_REGION_MEM);
/* PCI IO space */
pci_set_region(hose->regions + 1,
CONFIG_PCI_IO_BUS,
CONFIG_PCI_IO_PHYS,
CONFIG_PCI_IO_SIZE,
PCI_REGION_IO);
pci_set_region(hose->regions + 2,
CONFIG_PCI_PREF_BUS,
CONFIG_PCI_PREF_PHYS,
CONFIG_PCI_PREF_SIZE,
PCI_REGION_PREFETCH);
hose->region_count = 3;
}

14
include/configs/chromebook_link.h
View File

@ -45,8 +45,6 @@
#undef CONFIG_CMD_GPIO
#undef CONFIG_VIDEO
#undef CONFIG_CFB_CONSOLE
#undef CONFIG_SYS_EARLY_PCI_INIT
#undef CONFIG_PCI
#undef CONFIG_ICH_SPI
#undef CONFIG_SPI
#undef CONFIG_CMD_SPI
@ -55,6 +53,18 @@
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_SCSI
#define CONFIG_PCI_MEM_BUS 0xe0000000
#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
#define CONFIG_PCI_MEM_SIZE 0x10000000
#define CONFIG_PCI_PREF_BUS 0xd0000000
#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS
#define CONFIG_PCI_PREF_SIZE 0x10000000
#define CONFIG_PCI_IO_BUS 0x1000
#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
#define CONFIG_PCI_IO_SIZE 0xefff
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \
"stderr=vga,serial\0"