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Merge branch 'master' of git://git.denx.de/u-boot-arm

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* 'master' of git://git.denx.de/u-boot-arm: (145 commits)
  beagleboard: enable HUB power on all variants of the BeagleBoard
  dm3730: enable dpll5
  ehci-hcd: Allow cleanups to happen gracefully on a timeout.
  OMAP3: Add DSS driver for OMAP3
  led: Remove state-saving of led for toggle functionality and add toggle option to led command
  led: Fixed setting of STATUS_LED_BIT1 when led_name is 'all'
  led: correct off/on locations in structure
  led: added cmd_led to Makefile
  BeagleBoard: fix LED 0/1 in driver
  Corrected LED name match finding avoiding extraneous Usage printouts
  BeagleBoard: config: updated default configuration
  BeagleBoard: config: Enabled multibus support for I2C in configuration
  BeagleBoard: config: add optargs/buddy/camera
  BeagleBoard: config: increase command-line functionality
  BeagleBoard: config: make mtest run
  BeagleBoard: config: enable DSS
  BeagleBoard: config: enable asix driver and dhcp
  BeagleBoard: config: enable networking
  BeagleBoard: config: decrease bootdelay to 2 seconds
  BeagleBoard: config: use uImage.beagle for tftp
  BeagleBoard: config: hardcode MAC for onboard SMSC
  BeagleBoard: config: load kernel from MMC ext, not FAT
  BeagleBoard: Configure DVI/S-video
  BeagleBoard: Added userbutton command
  BeagleBoard: turn off clocks in ehci_stop
  USB: Remove __attribute__ ((packed)) for struct ehci_hccr and ehci_hcor
  beagleboard: add support for xM revision C
  beagle: pass expansionboard name in bootargs
  OMAP: Remove omapfb.debug=y from Beagle and Overo env settings
  OMAP3 Beagle Pin Mux initialization glitch fix
  da850: modifications for Logic PD Rev.3 AM18xx EVM
  da850: fix the channel number for EMAC teardown init
  da850: add support for Spectrum Digital AM18xx EVM
  da850: add support to wake up DSP during board init
  da850: modify the U-Boot prompt string
  da850: add NOR boot mode support
  da8xx: add support for multiple PLL controllers
  da850: indicate cache usage disable in config file
  dm365: modify boot prompt from dm365 to dm36x
  dm365: disable cache usage due to coherency issues
  dm6446: disable cache usage due to coherency issues
  OMAP3: Remove legacy mmc driver
  devkit8000: Use generic MMC driver
  TI OMAP3 SDP3430: Use generic MMC driver
  AM3517 CraneBoard: Use generic MMC driver
  OMAP3: pandora: Use generic MMC driver
  OMAP3: Zoom2: Use generic MMC driver
  OMAP3: Zoom1: Use generic MMC driver
  OMAP3: DIG297: Use generic MMC driver
  OMAP3: CM-T35: Use generic MMC driver
  am3517evm: Use generic MMC driver
  omap3evm: Use generic MMC driver
  omap3:clock: check cpu_family before enabling clks for IVA & CAM
  omap3:clock: configure GFX clock to 200MHz for AM/DM37x
  OMAP3/4: Increase console I/O buffer size
  PXA: vpac270: Remove re-defined CONFIG_SYS_TEXT_BASE
  PXA: Fix CSB226, fix monitor length
  PXA: Fix Lubbock, remove redundant parenthesis
  armv7: cache: remove flush on un-aligned invalidate
  armv7: stronger barrier for cache-maintenance operations
  omap: enable caches at system start-up
  arm: do not force d-cache enable on all boards
  ORIGEN: Add MMC SPL support
  ARMV7: Add support for Samsung ORIGEN board
  i2c:gpio:s5p: Enable I2C GPIO on the GONI target
  i2c:gpio:s5p: I2C GPIO Software implementation (via soft_i2c)
  Tegra2: Use clock and pinmux functions to simplify code
  Tegra2: Add additional pin multiplexing features
  Tegra2: Add more clock support
  Tegra2: Add microsecond timer function
  ARM: remove broken "at91rm9200dk" board
  ARM: remove broken "m501sk" board
  ARM: remove broken "kb9202" board
  ARM: remove broken "csb637" board
  ARM: remove broken "cmc_pu2" board
  ARM: remove broken "at91cap9adk" board
  ARM: remove broken "voiceblue" board
  ARM: remove broken "smdk2400" board
  ARM: remove broken "sbc2410x" board
  ARM: remove broken "netstar" board
  ARM: remove broken "mx1fs2" board
  ARM: remove broken "lpd7a40x" boards
  ARM: remove broken "edb93xx" boards
  ARM: remove broken "B2" board
  ARM: remove broken "armadillo" board
  ARM: remove broken "assabet" board
  ARM: versatile: drop warnings
  IMX: scb9328: drop warnings
  MX31: imx31_litekit: make use of GPIO framework
  MX31: mx31ads: make use of GPIO framework
  MX5: mx51evk: make use of GPIO framework
  MX35: mx35pdk: make use of GPIO framework
  MX5: mx53loco: make use of GPIO framework
  MX5: mx53evk: make use of GPIO framework
  MX5: vision2: make use of GPIO framework
  MX5: mx53smd: make use of GPIO framework
  MX5: mx53ard: make use of GPIO framework
  MX25: zmx25: make use of GPIO framework
  MX5: efikamx: make use of GPIO framework
  MX31: QONG: make use of GPIO framework
  MX35: make use of GPIO framework for MX35 processor
  MX5: make use of GPIO framework for MX5 processor
  MX31: make use of GPIO framework for MX31 processor
  MX25: make use of GPIO framework for MX25 processor
  IMX: uniform GPIO interface using GPIO framework
  MX: MX35 / MX5: uniform clock command with powerpc
  MX35: MX35PDK: support additional RAM on CSD1
  mx53: ddr3: Update DD3 initialization
  ARM: MX51: PLL errata workaround
  ARM: versatilepb : drop warnings due to double definitions
  omap4: increase SRAM budget to fix build error
  omap4: fix build warning due to signed unsigned comparison
  mkimage: Fix 'Unknown OMAP image type - 5'
  omap: fix gpio related build breaks
  gpio:samsung: s5p_ suffix add for GPIO functions (C210_universal)
  SMDKV310: MMC SPL: Remove unwanted dummy functions
  SMDKV310: Fix undefined reference error
  SMDKV310: Fix build error for smdkv310 board
  gpio:samsung s5p_ suffix add for GPIO functions
  mmc: S5P: Support DMA restarts at buffer boundaries
  SMDKV310: Fix host compilation of mkv310_image
  arm: fix bd pointer dereference prior initialization
  arm, lib/board.c: use gd->ram_size instead of bd->bi_memsize
  mx5: Remove CONFIG_L2_OFF and CONFIG_SYS_L2CACHE_OFF
  MX31: removed warnings due to clock.h
  integrator: convert to new build system
  integratorcp: make the board compile
  integratorap: remove hardcoded 32MB memory cmdline
  ...
This commit is contained in:
Wolfgang Denk
2011-09-04 21:12:18 +02:00
parent dc344589de 38a77c3adb
commit 6dfbf49c6d
275 changed files with 5025 additions and 16972 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/cpu/arm1136/mx35/generic.c
View File

@@ -417,8 +417,8 @@ int do_mx35_showclocks(cmd_tbl_t *cmdtp,
}
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks\n",
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks",
""
);

5
arch/arm/cpu/arm720t/cpu.c
View File

@@ -82,9 +82,4 @@ static void cache_flush (void)
asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (i));
}
#elif defined(CONFIG_INTEGRATOR) && defined(CONFIG_ARCH_INTEGRATOR)
/* No specific cache setup for IntegratorAP/CM720T as yet */
void icache_enable (void)
{
}
#endif

114
arch/arm/cpu/arm926ejs/at91/at91sam9m10g45_devices.c
View File

@@ -26,135 +26,131 @@
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/gpio.h>
#include <asm/arch/io.h>
#include <asm/io.h>
/*
* if CONFIG_AT91_GPIO_PULLUP ist set, keep pullups on on all
* peripheral pins. Good to have if hardware is soldered optionally
* or in case of SPI no slave is selected. Avoid lines to float
* needlessly. Use a short local PUP define.
*
* Due to errata "TXD floats when CTS is inactive" pullups are always
* on for TXD pins.
*/
#ifdef CONFIG_AT91_GPIO_PULLUP
# define PUP CONFIG_AT91_GPIO_PULLUP
#else
# define PUP 0
#endif
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 18, 0); /* RXD0 */
writel(1 << AT91SAM9G45_ID_US0, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, 0); /* RXD1 */
writel(1 << AT91SAM9G45_ID_US1, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 7, 0); /* RXD2 */
writel(1 << AT91SAM9G45_ID_US2, &pmc->pcer);
at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
}
void at91_serial3_hw_init(void)
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
writel(1 << AT91_ID_SYS, &pmc->pcer);
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
}
void at91_serial_hw_init(void)
{
#ifdef CONFIG_USART0
at91_serial0_hw_init();
#endif
#ifdef CONFIG_USART1
at91_serial1_hw_init();
#endif
#ifdef CONFIG_USART2
at91_serial2_hw_init();
#endif
#ifdef CONFIG_USART3 /* DBGU */
at91_serial3_hw_init();
#endif
}
#ifdef CONFIG_ATMEL_SPI
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* SPI0_SPCK */
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << AT91SAM9G45_ID_SPI0, &pmc->pcer);
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 3, 0);
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTB, 18, 0);
at91_set_b_periph(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_b_periph(AT91_PIO_PORTB, 19, 0);
at91_set_b_periph(AT91_PIO_PORTB, 19, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_b_periph(AT91_PIO_PORTD, 27, 0);
at91_set_b_periph(AT91_PIO_PORTD, 27, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 3, 0);
at91_set_pio_output(AT91_PIO_PORTB, 3, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTB, 18, 0);
at91_set_pio_output(AT91_PIO_PORTB, 18, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTB, 19, 0);
at91_set_pio_output(AT91_PIO_PORTB, 19, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTD, 27, 0);
at91_set_pio_output(AT91_PIO_PORTD, 27, 1);
}
}
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 14, 0); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, 0); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* SPI1_SPCK */
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << AT91SAM9G45_ID_SPI1, &pmc->pcer);
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 17, 0);
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 1)) {
at91_set_b_periph(AT91_PIO_PORTD, 28, 0);
at91_set_b_periph(AT91_PIO_PORTD, 28, 1);
}
if (cs_mask & (1 << 2)) {
at91_set_a_periph(AT91_PIO_PORTD, 18, 0);
at91_set_a_periph(AT91_PIO_PORTD, 18, 1);
}
if (cs_mask & (1 << 3)) {
at91_set_a_periph(AT91_PIO_PORTD, 19, 0);
at91_set_a_periph(AT91_PIO_PORTD, 19, 1);
}
if (cs_mask & (1 << 4)) {
at91_set_pio_output(AT91_PIO_PORTB, 17, 0);
at91_set_pio_output(AT91_PIO_PORTB, 17, 1);
}
if (cs_mask & (1 << 5)) {
at91_set_pio_output(AT91_PIO_PORTD, 28, 0);
at91_set_pio_output(AT91_PIO_PORTD, 28, 1);
}
if (cs_mask & (1 << 6)) {
at91_set_pio_output(AT91_PIO_PORTD, 18, 0);
at91_set_pio_output(AT91_PIO_PORTD, 18, 1);
}
if (cs_mask & (1 << 7)) {
at91_set_pio_output(AT91_PIO_PORTD, 19, 0);
at91_set_pio_output(AT91_PIO_PORTD, 19, 1);
}
}

30
arch/arm/cpu/arm926ejs/davinci/cpu.c
View File

@@ -37,6 +37,7 @@
#define PLLC_PLLDIV4 0x160
#define PLLC_PLLDIV5 0x164
#define PLLC_PLLDIV6 0x168
#define PLLC_PLLDIV7 0x16c
#define PLLC_PLLDIV8 0x170
#define PLLC_PLLDIV9 0x174
@@ -61,11 +62,9 @@
#endif
#ifdef CONFIG_SOC_DA8XX
const dv_reg * const sysdiv[7] = {
&davinci_pllc_regs->plldiv1, &davinci_pllc_regs->plldiv2,
&davinci_pllc_regs->plldiv3, &davinci_pllc_regs->plldiv4,
&davinci_pllc_regs->plldiv5, &davinci_pllc_regs->plldiv6,
&davinci_pllc_regs->plldiv7
unsigned int sysdiv[9] = {
PLLC_PLLDIV1, PLLC_PLLDIV2, PLLC_PLLDIV3, PLLC_PLLDIV4, PLLC_PLLDIV5,
PLLC_PLLDIV6, PLLC_PLLDIV7, PLLC_PLLDIV8, PLLC_PLLDIV9
};
int clk_get(enum davinci_clk_ids id)
@@ -74,19 +73,27 @@ int clk_get(enum davinci_clk_ids id)
int pllm;
int post_div;
int pll_out;
unsigned int pll_base;
pll_out = CONFIG_SYS_OSCIN_FREQ;
if (id == DAVINCI_AUXCLK_CLKID)
goto out;
if ((id >> 16) == 1)
pll_base = (unsigned int)davinci_pllc1_regs;
else
pll_base = (unsigned int)davinci_pllc0_regs;
id &= 0xFFFF;
/*
* Lets keep this simple. Combining operations can result in
* unexpected approximations
*/
pre_div = (readl(&davinci_pllc_regs->prediv) &
DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(&davinci_pllc_regs->pllm) + 1;
pre_div = (readl(pll_base + PLLC_PREDIV) &
DAVINCI_PLLC_DIV_MASK) + 1;
pllm = readl(pll_base + PLLC_PLLM) + 1;
pll_out /= pre_div;
pll_out *= pllm;
@@ -94,15 +101,16 @@ int clk_get(enum davinci_clk_ids id)
if (id == DAVINCI_PLLM_CLKID)
goto out;
post_div = (readl(&davinci_pllc_regs->postdiv) &
DAVINCI_PLLC_DIV_MASK) + 1;
post_div = (readl(pll_base + PLLC_POSTDIV) &
DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= post_div;
if (id == DAVINCI_PLLC_CLKID)
goto out;
pll_out /= (readl(sysdiv[id - 1]) & DAVINCI_PLLC_DIV_MASK) + 1;
pll_out /= (readl(pll_base + sysdiv[id - 1]) &
DAVINCI_PLLC_DIV_MASK) + 1;
out:
return pll_out;

26
arch/arm/cpu/armv7/cache_v7.c
View File

@@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
: : "r" (setway));
}
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
@@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
: : "r" (setway));
}
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
static void v7_maint_dcache_level_setway(u32 level, u32 operation)
@@ -181,21 +181,23 @@ static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)
u32 mva;
/*
* If start address is not aligned to cache-line flush the first
* line to prevent affecting somebody else's buffer
* If start address is not aligned to cache-line do not
* invalidate the first cache-line
*/
if (start & (line_len - 1)) {
v7_dcache_clean_inval_range(start, start + 1, line_len);
printf("ERROR: %s - start address is not aligned - 0x%08x\n",
__func__, start);
/* move to next cache line */
start = (start + line_len - 1) & ~(line_len - 1);
}
/*
* If stop address is not aligned to cache-line flush the last
* line to prevent affecting somebody else's buffer
* If stop address is not aligned to cache-line do not
* invalidate the last cache-line
*/
if (stop & (line_len - 1)) {
v7_dcache_clean_inval_range(stop, stop + 1, line_len);
printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
__func__, stop);
/* align to the beginning of this cache line */
stop &= ~(line_len - 1);
}
@@ -227,8 +229,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
break;
}
/* DMB to make sure the operation is complete */
CP15DMB;
/* DSB to make sure the operation is complete */
CP15DSB;
}
/* Invalidate TLB */

4
arch/arm/cpu/armv7/mx5/clock.c
View File

@@ -288,7 +288,7 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
/***************************************************/
U_BOOT_CMD(
clockinfo, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
"display clocks\n",
clocks, CONFIG_SYS_MAXARGS, 1, do_mx5_showclocks,
"display clocks",
""
);

38
arch/arm/cpu/armv7/mx5/lowlevel_init.S
View File

@@ -121,6 +121,35 @@
beq 1b
.endm
.macro setup_pll_errata pll, freq
ldr r2, =\pll
mov r1, #0x0
str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
ands r1, r1, #0x1
beq 1b
ldr r5, \freq
str r5, [r2, #PLL_DP_MFN] /* Modify MFN value */
str r5, [r2, #PLL_DP_HFS_MFN]
mov r1, #0x1
str r1, [r2, #PLL_DP_CONFIG] /* Reload MFN value */
2: ldr r1, [r2, #PLL_DP_CONFIG]
tst r1, #1
bne 2b
ldr r1, =100 /* Wait at least 4 us */
3: subs r1, r1, #1
bge 3b
mov r1, #0x2
str r1, [r2, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
.endm
.macro init_clock
ldr r0, =CCM_BASE_ADDR
@@ -157,7 +186,12 @@
mov r1, #0x4
str r1, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51_PLL_ERRATA)
setup_pll PLL1_BASE_ADDR, 864
setup_pll_errata PLL1_BASE_ADDR, W_DP_MFN_800_DIT
#else
setup_pll PLL1_BASE_ADDR, 800
#endif
#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
@@ -287,6 +321,10 @@ lowlevel_init:
mov pc,lr
/* Board level setting value */
W_DP_OP_864: .word DP_OP_864
W_DP_MFD_864: .word DP_MFD_864
W_DP_MFN_864: .word DP_MFN_864
W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
W_DP_OP_800: .word DP_OP_800
W_DP_MFD_800: .word DP_MFD_800
W_DP_MFN_800: .word DP_MFN_800

2
arch/arm/cpu/armv7/omap-common/gpio.c
View File

@@ -36,7 +36,7 @@
* published by the Free Software Foundation.
*/
#include <common.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
#include <asm/errno.h>

10
arch/arm/cpu/armv7/omap3/board.c
View File

@@ -38,7 +38,7 @@
#include <asm/arch/mem.h>
#include <asm/cache.h>
#include <asm/armv7.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
/* Declarations */
extern omap3_sysinfo sysinfo;
@@ -402,3 +402,11 @@ void v7_outer_cache_disable(void)
omap3_update_aux_cr(0, 0x2);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

17
arch/arm/cpu/armv7/omap3/clock.c
View File

@@ -399,7 +399,7 @@ static void dpll3_init_36xx(u32 sil_index, u32 clk_index)
/* L3 */
sr32(&prcm_base->clksel_core, 0, 2, CORE_L3_DIV);
/* GFX */
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV);
sr32(&prcm_base->clksel_gfx, 0, 3, GFX_DIV_36X);
/* RESET MGR */
sr32(&prcm_base->clksel_wkup, 1, 2, WKUP_RSM);
/* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */
@@ -579,6 +579,7 @@ void prcm_init(void)
dpll3_init_36xx(0, clk_index);
dpll4_init_36xx(0, clk_index);
dpll5_init_34xx(0, clk_index);
iva_init_36xx(0, clk_index);
mpu_init_36xx(0, clk_index);
@@ -607,7 +608,9 @@ void prcm_init(void)
dpll3_init_34xx(sil_index, clk_index);
dpll4_init_34xx(sil_index, clk_index);
dpll5_init_34xx(sil_index, clk_index);
iva_init_34xx(sil_index, clk_index);
if (get_cpu_family() != CPU_AM35XX)
iva_init_34xx(sil_index, clk_index);
mpu_init_34xx(sil_index, clk_index);
/* Lock MPU DPLL to set frequency */
@@ -674,7 +677,9 @@ void per_clocks_enable(void)
/* Enable the ICLK for 32K Sync Timer as its used in udelay */
sr32(&prcm_base->iclken_wkup, 2, 1, 0x1);
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
if (get_cpu_family() != CPU_AM35XX)
sr32(&prcm_base->fclken_iva2, 0, 32, FCK_IVA2_ON);
sr32(&prcm_base->fclken1_core, 0, 32, FCK_CORE1_ON);
sr32(&prcm_base->iclken1_core, 0, 32, ICK_CORE1_ON);
sr32(&prcm_base->iclken2_core, 0, 32, ICK_CORE2_ON);
@@ -682,8 +687,10 @@ void per_clocks_enable(void)
sr32(&prcm_base->iclken_wkup, 0, 32, ICK_WKUP_ON);
sr32(&prcm_base->fclken_dss, 0, 32, FCK_DSS_ON);
sr32(&prcm_base->iclken_dss, 0, 32, ICK_DSS_ON);
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
if (get_cpu_family() != CPU_AM35XX) {
sr32(&prcm_base->fclken_cam, 0, 32, FCK_CAM_ON);
sr32(&prcm_base->iclken_cam, 0, 32, ICK_CAM_ON);
}
sr32(&prcm_base->fclken_per, 0, 32, FCK_PER_ON);
sr32(&prcm_base->iclken_per, 0, 32, ICK_PER_ON);

10
arch/arm/cpu/armv7/omap4/board.c
View File

@@ -33,7 +33,7 @@
#include <asm/arch/sys_proto.h>
#include <asm/sizes.h>
#include <asm/arch/emif.h>
#include <asm/omap_gpio.h>
#include <asm/arch/gpio.h>
#include "omap4_mux_data.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -299,3 +299,11 @@ void v7_outer_cache_disable(void)
set_pl310_ctrl_reg(0);
}
#endif
#ifndef CONFIG_SYS_DCACHE_OFF
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
dcache_enable();
}
#endif

2
arch/arm/cpu/armv7/tegra2/Makefile
View File

@@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)lib$(SOC).o
SOBJS := lowlevel_init.o
COBJS := ap20.o board.o sys_info.o timer.o
COBJS := ap20.o board.o clock.o pinmux.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))

91
arch/arm/cpu/armv7/tegra2/ap20.c
View File

@@ -25,6 +25,7 @@
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/scu.h>
@@ -35,33 +36,32 @@ u32 s_first_boot = 1;
void init_pllx(void)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
struct clk_pll *pll = &clkrst->crc_pll[CLOCK_PLL_ID_XCPU];
u32 reg;
/* If PLLX is already enabled, just return */
reg = readl(&clkrst->crc_pllx_base);
if (reg & PLL_ENABLE)
if (readl(&pll->pll_base) & PLL_ENABLE_MASK)
return;
/* Set PLLX_MISC */
reg = CPCON; /* CPCON[11:8] = 0001 */
writel(reg, &clkrst->crc_pllx_misc);
writel(1 << PLL_CPCON_SHIFT, &pll->pll_misc);
/* Use 12MHz clock here */
reg = (PLL_BYPASS | PLL_DIVM);
reg |= (1000 << 8); /* DIVN = 0x3E8 */
writel(reg, &clkrst->crc_pllx_base);
reg = PLL_BYPASS_MASK | (12 << PLL_DIVM_SHIFT);
reg |= 1000 << PLL_DIVN_SHIFT;
writel(reg, &pll->pll_base);
reg |= PLL_ENABLE;
writel(reg, &clkrst->crc_pllx_base);
reg |= PLL_ENABLE_MASK;
writel(reg, &pll->pll_base);
reg &= ~PLL_BYPASS;
writel(reg, &clkrst->crc_pllx_base);
reg &= ~PLL_BYPASS_MASK;
writel(reg, &pll->pll_base);
}
static void enable_cpu_clock(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg, clk;
u32 clk;
/*
* NOTE:
@@ -83,27 +83,19 @@ static void enable_cpu_clock(int enable)
writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
}
/* Fetch the register containing the main CPU complex clock enable */
reg = readl(&clkrst->crc_clk_out_enb_l);
reg |= CLK_ENB_CPU;
/*
* Read the register containing the individual CPU clock enables and
* always stop the clock to CPU 1.
*/
clk = readl(&clkrst->crc_clk_cpu_cmplx);
clk |= CPU1_CLK_STP;
if (enable) {
/* Unstop the CPU clock */
clk &= ~CPU0_CLK_STP;
} else {
/* Stop the CPU clock */
clk |= CPU0_CLK_STP;
}
clk |= 1 << CPU1_CLK_STP_SHIFT;
/* Stop/Unstop the CPU clock */
clk &= ~CPU0_CLK_STP_MASK;
clk |= !enable << CPU0_CLK_STP_SHIFT;
writel(clk, &clkrst->crc_clk_cpu_cmplx);
writel(reg, &clkrst->crc_clk_out_enb_l);
clock_enable(PERIPH_ID_CPU);
}
static int is_cpu_powered(void)
@@ -178,9 +170,6 @@ static void enable_cpu_power_rail(void)
static void reset_A9_cpu(int reset)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg, cpu;
/*
* NOTE: Regardless of whether the request is to hold the CPU in reset
* or take it out of reset, every processor in the CPU complex
@@ -189,48 +178,22 @@ static void reset_A9_cpu(int reset)
* are multiple processors in the CPU complex.
*/
/* Hold CPU 1 in reset */
cpu = SET_DBGRESET1 | SET_DERESET1 | SET_CPURESET1;
writel(cpu, &clkrst->crc_cpu_cmplx_set);
/* Hold CPU 1 in reset, and CPU 0 if asked */
reset_cmplx_set_enable(1, crc_rst_cpu | crc_rst_de | crc_rst_debug, 1);
reset_cmplx_set_enable(0, crc_rst_cpu | crc_rst_de | crc_rst_debug,
reset);
reg = readl(&clkrst->crc_rst_dev_l);
if (reset) {
/* Now place CPU0 into reset */
cpu |= SET_DBGRESET0 | SET_DERESET0 | SET_CPURESET0;
writel(cpu, &clkrst->crc_cpu_cmplx_set);
/* Enable master CPU reset */
reg |= SWR_CPU_RST;
} else {
/* Take CPU0 out of reset */
cpu = CLR_DBGRESET0 | CLR_DERESET0 | CLR_CPURESET0;
writel(cpu, &clkrst->crc_cpu_cmplx_clr);
/* Disable master CPU reset */
reg &= ~SWR_CPU_RST;
}
writel(reg, &clkrst->crc_rst_dev_l);
/* Enable/Disable master CPU reset */
reset_set_enable(PERIPH_ID_CPU, reset);
}
static void clock_enable_coresight(int enable)
{
struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 rst, clk, src;
u32 rst, src;
rst = readl(&clkrst->crc_rst_dev_u);
clk = readl(&clkrst->crc_clk_out_enb_u);
if (enable) {
rst &= ~SWR_CSITE_RST;
clk |= CLK_ENB_CSITE;
} else {
rst |= SWR_CSITE_RST;
clk &= ~CLK_ENB_CSITE;
}
writel(clk, &clkrst->crc_clk_out_enb_u);
writel(rst, &clkrst->crc_rst_dev_u);
clock_set_enable(PERIPH_ID_CORESIGHT, enable);
reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
if (enable) {
/*

158
arch/arm/cpu/armv7/tegra2/clock.c Normal file
View File

@@ -0,0 +1,158 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 Clock control functions */
#include <asm/io.h>
#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/timer.h>
#include <asm/arch/tegra2.h>
#include <common.h>
#ifdef DEBUG
#define assert(x) \
({ if (!(x)) printf("Assertion failure '%s' %s line %d\n", \
#x, __FILE__, __LINE__); })
#else
#define assert(x)
#endif
/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field.
*/
enum clock_osc_freq clock_get_osc_freq(void)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 reg;
reg = readl(&clkrst->crc_osc_ctrl);
return (reg & OSC_FREQ_MASK) >> OSC_FREQ_SHIFT;
}
unsigned long clock_start_pll(enum clock_pll_id clkid, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 data;
struct clk_pll *pll;
assert(clock_pll_id_isvalid(clkid));
pll = &clkrst->crc_pll[clkid];
/*
* We cheat by treating all PLL (except PLLU) in the same fashion.
* This works only because:
* - same fields are always mapped at same offsets, except DCCON
* - DCCON is always 0, doesn't conflict
* - M,N, P of PLLP values are ignored for PLLP
*/
data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
writel(data, &pll->pll_misc);
data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
if (clkid == CLOCK_PLL_ID_USB)
data |= divp << PLLU_VCO_FREQ_SHIFT;
else
data |= divp << PLL_DIVP_SHIFT;
writel(data, &pll->pll_base);
/* calculate the stable time */
return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
}
void clock_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *clk = &clkrst->crc_clk_out_enb[PERIPH_REG(periph_id)];
u32 reg;
/* Enable/disable the clock to this peripheral */
assert(clock_periph_id_isvalid(periph_id));
reg = readl(clk);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, clk);
}
void clock_enable(enum periph_id clkid)
{
clock_set_enable(clkid, 1);
}
void clock_disable(enum periph_id clkid)
{
clock_set_enable(clkid, 0);
}
void reset_set_enable(enum periph_id periph_id, int enable)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 *reset = &clkrst->crc_rst_dev[PERIPH_REG(periph_id)];
u32 reg;
/* Enable/disable reset to the peripheral */
assert(clock_periph_id_isvalid(periph_id));
reg = readl(reset);
if (enable)
reg |= PERIPH_MASK(periph_id);
else
reg &= ~PERIPH_MASK(periph_id);
writel(reg, reset);
}
void reset_periph(enum periph_id periph_id, int us_delay)
{
/* Put peripheral into reset */
reset_set_enable(periph_id, 1);
udelay(us_delay);
/* Remove reset */
reset_set_enable(periph_id, 0);
udelay(us_delay);
}
void reset_cmplx_set_enable(int cpu, int which, int reset)
{
struct clk_rst_ctlr *clkrst =
(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
u32 mask;
/* Form the mask, which depends on the cpu chosen. Tegra2 has 2 */
assert(cpu >= 0 && cpu < 2);
mask = which << cpu;
/* either enable or disable those reset for that CPU */
if (reset)
writel(mask, &clkrst->crc_cpu_cmplx_set);
else
writel(mask, &clkrst->crc_cpu_cmplx_clr);
}

52
arch/arm/cpu/armv7/tegra2/pinmux.c Normal file
View File

@@ -0,0 +1,52 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 pin multiplexing functions */
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/pinmux.h>
#include <common.h>
void pinmux_set_tristate(enum pmux_pin pin, int enable)
{
struct pmux_tri_ctlr *pmt = (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
u32 *tri = &pmt->pmt_tri[TRISTATE_REG(pin)];
u32 reg;
reg = readl(tri);
if (enable)
reg |= TRISTATE_MASK(pin);
else
reg &= ~TRISTATE_MASK(pin);
writel(reg, tri);
}
void pinmux_tristate_enable(enum pmux_pin pin)
{
pinmux_set_tristate(pin, 1);
}
void pinmux_tristate_disable(enum pmux_pin pin)
{
pinmux_set_tristate(pin, 0);
}

18
arch/arm/cpu/armv7/tegra2/timer.c
View File

@@ -38,13 +38,12 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/tegra2.h>
#include <asm/arch/timer.h>
DECLARE_GLOBAL_DATA_PTR;
struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
/* counter runs at 1MHz */
#define TIMER_CLK (1000000)
#define TIMER_CLK 1000000
#define TIMER_LOAD_VAL 0xffffffff
/* timer without interrupts */
@@ -57,10 +56,10 @@ ulong get_timer(ulong base)
void __udelay(unsigned long usec)
{
long tmo = usec * (TIMER_CLK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->cntr_1us);
unsigned long now, last = timer_get_us();
while (tmo > 0) {
now = readl(&timer_base->cntr_1us);
now = timer_get_us();
if (last > now) /* count up timer overflow */
tmo -= TIMER_LOAD_VAL - last + now;
else
@@ -74,7 +73,7 @@ ulong get_timer_masked(void)
ulong now;
/* current tick value */
now = readl(&timer_base->cntr_1us) / (TIMER_CLK / CONFIG_SYS_HZ);
now = timer_get_us() / (TIMER_CLK / CONFIG_SYS_HZ);
if (now >= gd->lastinc) /* normal mode (non roll) */
/* move stamp forward with absolute diff ticks */
@@ -103,3 +102,10 @@ ulong get_tbclk(void)
{
return CONFIG_SYS_HZ;
}
unsigned long timer_get_us(void)
{
struct timerus *timer_base = (struct timerus *)NV_PA_TMRUS_BASE;
return readl(&timer_base->cntr_1us);
}

16
arch/arm/include/asm/arch-at91/at91sam9g45.h
View File

@@ -128,11 +128,25 @@
#define ATMEL_BASE_EHCI 0x00800000 /* USB Host controller (EHCI) */
#define ATMEL_BASE_VDEC 0x00900000 /* Video Decoder Controller */
/*
* External memory
*/
#define ATMEL_BASE_CS0 0x10000000
#define ATMEL_BASE_CS1 0x20000000
#define ATMEL_BASE_CS2 0x30000000
#define ATMEL_BASE_CS3 0x40000000
#define ATMEL_BASE_CS4 0x50000000
#define ATMEL_BASE_CS5 0x60000000
#define ATMEL_BASE_CS6 0x70000000
#define ATMEL_BASE_CS7 0x80000000
/*
* Other misc defines
*/
#define ATMEL_PIO_PORTS 5 /* this SoCs has 5 PIO */
#define ATMEL_BASE_PIO ATMEL_BASE_PIOA
#define ATMEL_PMC_UHP AT91SAM926x_PMC_UHP
#define ATMEL_ID_UHP ATMEL_ID_UHPHS
/*
* Cpu Name
*/

194
arch/arm/include/asm/arch-at91/at91sam9g45_matrix.h
View File

@@ -15,139 +15,81 @@
#ifndef AT91SAM9G45_MATRIX_H
#define AT91SAM9G45_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#ifndef __ASSEMBLY__
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
#define AT91_MATRIX_SLOT_CYCLE (0x1ff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
struct at91_matrix {
u32 mcfg[16];
u32 scfg[16];
u32 pras[16][2];
u32 mrcr; /* 0x100 Master Remap Control */
u32 filler[3];
u32 tcmr;
u32 filler2;
u32 ddrmpr;
u32 filler3[3];
u32 ebicsa;
u32 filler4[47];
u32 wpmr;
u32 wpsr;
};
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
#endif /* __ASSEMBLY__ */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_RCB11 (1 << 11)
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_ULBT_THIRTYTWO (5 << 0)
#define AT91_MATRIX_ULBT_SIXTYFOUR (6 << 0)
#define AT91_MATRIX_ULBT_128 (7 << 0)
#define AT91_MATRIX_TCMR (AT91_MATRIX + 0x110) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_TCM_NWS (0x1 << 11) /* Wait state TCM register */
#define AT91_MATRIX_TCM_NO_WS (0x0 << 11)
#define AT91_MATRIX_TCM_ONE_WS (0x1 << 11)
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR_SHIFT 18
#define AT91_MATRIX_VIDEO (AT91_MATRIX + 0x118) /* Video Mode Configuration Register */
#define AT91C_VDEC_SEL (0x1 << 0) /* Video Mode Selection */
#define AT91C_VDEC_SEL_OFF (0 << 0)
#define AT91C_VDEC_SEL_ON (1 << 0)
#define AT91_MATRIX_M0PR_SHIFT 0
#define AT91_MATRIX_M1PR_SHIFT 4
#define AT91_MATRIX_M2PR_SHIFT 8
#define AT91_MATRIX_M3PR_SHIFT 12
#define AT91_MATRIX_M4PR_SHIFT 16
#define AT91_MATRIX_M5PR_SHIFT 20
#define AT91_MATRIX_M6PR_SHIFT 24
#define AT91_MATRIX_M7PR_SHIFT 28
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x128) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR (1 << 17) /* EBI I/O slew rate selection */
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR (1 << 18) /* DDR2 dedicated port I/O slew rate selection */
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#define AT91_MATRIX_M8PR_SHIFT 0 /* register B */
#define AT91_MATRIX_M9PR_SHIFT 4 /* register B */
#define AT91_MATRIX_M10PR_SHIFT 8 /* register B */
#define AT91_MATRIX_M11PR_SHIFT 12 /* register B */
#define AT91_MATRIX_WPMR (AT91_MATRIX + 0x1E4) /* Write Protect Mode Register */
#define AT91_MATRIX_WPMR_WPEN (1 << 0) /* Write Protect ENable */
#define AT91_MATRIX_WPMR_WP_WPDIS (0 << 0)
#define AT91_MATRIX_WPMR_WP_WPEN (1 << 0)
#define AT91_MATRIX_WPMR_WPKEY (0xFFFFFF << 8) /* Write Protect KEY */
#define AT91_MATRIX_RCB0 (1 << 0)
#define AT91_MATRIX_RCB1 (1 << 1)
#define AT91_MATRIX_RCB2 (1 << 2)
#define AT91_MATRIX_RCB3 (1 << 3)
#define AT91_MATRIX_RCB4 (1 << 4)
#define AT91_MATRIX_RCB5 (1 << 5)
#define AT91_MATRIX_RCB6 (1 << 6)
#define AT91_MATRIX_RCB7 (1 << 7)
#define AT91_MATRIX_RCB8 (1 << 8)
#define AT91_MATRIX_RCB9 (1 << 9)
#define AT91_MATRIX_RCB10 (1 << 10)
#define AT91_MATRIX_WPSR (AT91_MATRIX + 0x1E8) /* Write Protect Status Register */
#define AT91_MATRIX_WPSR_WPVS (1 << 0) /* Write Protect Violation Status */
#define AT91_MATRIX_WPSR_NO_WPV (0 << 0)
#define AT91_MATRIX_WPSR_WPV (1 << 0)
#define AT91_MATRIX_WPSR_WPVSRC (0xFFFF << 8) /* Write Protect Violation Source */
#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
#define AT91_MATRIX_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
#define AT91_MATRIX_EBI_CS4A_SMC_CF0 (1 << 4)
#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
#define AT91_MATRIX_EBI_CS5A_SMC_CF1 (1 << 5)
#define AT91_MATRIX_EBI_DBPU_ON (0 << 8)
#define AT91_MATRIX_EBI_DBPU_OFF (1 << 8)
#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
#define AT91_MATRIX_EBI_EBI_IOSR_REDUCED (0 << 17)
#define AT91_MATRIX_EBI_EBI_IOSR_NORMAL (1 << 17)
#define AT91_MATRIX_EBI_DDR_IOSR_REDUCED (0 << 18)
#define AT91_MATRIX_EBI_DDR_IOSR_NORMAL (1 << 18)
#endif

12
arch/arm/include/asm/arch-davinci/hardware.h
View File

@@ -129,6 +129,7 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_TIMER1_BASE 0x01c21000
#define DAVINCI_WDOG_BASE 0x01c21000
#define DAVINCI_PLL_CNTRL0_BASE 0x01c11000
#define DAVINCI_PLL_CNTRL1_BASE 0x01e1a000
#define DAVINCI_PSC0_BASE 0x01c10000
#define DAVINCI_PSC1_BASE 0x01e27000
#define DAVINCI_SPI0_BASE 0x01c41000
@@ -152,8 +153,16 @@ typedef volatile unsigned int * dv_reg_p;
#define DAVINCI_DDR_EMIF_DATA_BASE 0xc0000000
#define DAVINCI_INTC_BASE 0xfffee000
#define DAVINCI_BOOTCFG_BASE 0x01c14000
#define DAVINCI_L3CBARAM_BASE 0x80000000
#define JTAG_ID_REG (DAVINCI_BOOTCFG_BASE + 0x18)
#define CHIP_REV_ID_REG (DAVINCI_BOOTCFG_BASE + 0x24)
#define HOST1CFG (DAVINCI_BOOTCFG_BASE + 0x44)
#define PSC0_MDCTL (DAVINCI_PSC0_BASE + 0xa00)
#define GPIO_BANK0_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x10)
#define GPIO_BANK0_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x14)
#define GPIO_BANK0_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x18)
#define GPIO_BANK0_REG_CLR_ADDR (DAVINCI_GPIO_BASE + 0x1c)
#define GPIO_BANK2_REG_DIR_ADDR (DAVINCI_GPIO_BASE + 0x38)
#define GPIO_BANK2_REG_OPDATA_ADDR (DAVINCI_GPIO_BASE + 0x3c)
#define GPIO_BANK2_REG_SET_ADDR (DAVINCI_GPIO_BASE + 0x40)
@@ -387,7 +396,8 @@ struct davinci_pllc_regs {
dv_reg emucnt1;
};
#define davinci_pllc_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc0_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL0_BASE)
#define davinci_pllc1_regs ((struct davinci_pllc_regs *)DAVINCI_PLL_CNTRL1_BASE)
#define DAVINCI_PLLC_DIV_MASK 0x1f
#define ASYNC3 get_async3_src()

45
arch/arm/include/asm/arch-mx25/gpio.h Normal file
View File

@@ -0,0 +1,45 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
/* Converts a GPIO port number and the internal bit position
* to the GPIO number
*/
#define MXC_GPIO_PORT_TO_NUM(port, bit) (((port - 1) << 5) + (bit & 0x1f))
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
#endif

12
arch/arm/include/asm/arch-mx25/imx-regs.h
View File

@@ -84,18 +84,6 @@ struct esdramc_regs {
u32 cdlyl; /* delay line cycle length debug */
};
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
u32 ctrl; /* control */

2
arch/arm/include/asm/arch-mx31/clock.h
View File

@@ -32,7 +32,7 @@ enum mxc_clock {
};
unsigned int mxc_get_clock(enum mxc_clock clk);
extern u32 imx_get_uartclk();
extern u32 imx_get_uartclk(void);
extern void mx31_gpio_mux(unsigned long mode);
extern void mx31_set_pad(enum iomux_pins pin, u32 config);

35
arch/arm/include/asm/arch-mx31/gpio.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX31_GPIO_H
#define __ASM_ARCH_MX31_GPIO_H
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
#endif

7
arch/arm/include/asm/arch-mx31/imx-regs.h
View File

@@ -57,13 +57,6 @@ struct clock_control_regs {
u32 pdr2;
};
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
struct cspi_regs {
u32 rxdata;
u32 txdata;

40
arch/arm/include/asm/arch-mx35/gpio.h Normal file
View File

@@ -0,0 +1,40 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr; /* data */
u32 gpio_dir; /* direction */
u32 psr; /* pad satus */
u32 icr1; /* interrupt config 1 */
u32 icr2; /* interrupt config 2 */
u32 imr; /* interrupt mask */
u32 isr; /* interrupt status */
u32 edge_sel; /* edge select */
};
#endif

35
arch/arm/include/asm/arch-mx5/gpio.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __ASM_ARCH_MX5_GPIO_H
#define __ASM_ARCH_MX5_GPIO_H
/* GPIO registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
#endif

12
arch/arm/include/asm/arch-mx5/imx-regs.h
View File

@@ -235,6 +235,11 @@
/* Assuming 24MHz input clock with doubler ON */
/* MFI PDF */
#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
#define DP_MFD_864 (180 - 1) /* PL Dither mode */
#define DP_MFN_864 180
#define DP_MFN_800_DIT 60 /* PL Dither mode */
#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
#define DP_MFD_850 (48 - 1)
#define DP_MFN_850 41
@@ -404,13 +409,6 @@ struct iomuxc {
};
#endif
/* GPIO Registers */
struct gpio_regs {
u32 gpio_dr;
u32 gpio_dir;
u32 gpio_psr;
};
/* System Reset Controller (SRC) */
struct src {
u32 scr;

1
arch/arm/include/asm/arch-omap3/clocks_omap3.h
View File

@@ -39,6 +39,7 @@
#define CORE_L4_DIV 2 /* 83MHz : L4 */
#define CORE_L3_DIV 2 /* 166MHz : L3 {DDR} */
#define GFX_DIV 2 /* 83MHz : CM_CLKSEL_GFX */
#define GFX_DIV_36X 5 /* 200MHz : CM_CLKSEL_GFX */
#define WKUP_RSM 2 /* 41.5MHz: CM_CLKSEL_WKUP */
/* PER DPLL */

174
arch/arm/include/asm/arch-omap3/dss.h Normal file
View File

@@ -0,0 +1,174 @@
/*
* (C) Copyright 2010
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*
* Referred to Linux Kernel DSS driver files for OMAP3 by
* Tomi Valkeinen from drivers/video/omap2/dss/
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation's version 2 and any
* later version the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef DSS_H
#define DSS_H
/*
* DSS Base Registers
*/
#define OMAP3_DSS_BASE 0x48050040
#define OMAP3_DISPC_BASE 0x48050440
#define OMAP3_VENC_BASE 0x48050C00
/* DSS Registers */
struct dss_regs {
u32 control; /* 0x40 */
u32 sdi_control; /* 0x44 */
u32 pll_control; /* 0x48 */
};
/* DISPC Registers */
struct dispc_regs {
u32 control; /* 0x40 */
u32 config; /* 0x44 */
u32 reserve_2; /* 0x48 */
u32 default_color0; /* 0x4C */
u32 default_color1; /* 0x50 */
u32 trans_color0; /* 0x54 */
u32 trans_color1; /* 0x58 */
u32 line_status; /* 0x5C */
u32 line_number; /* 0x60 */
u32 timing_h; /* 0x64 */
u32 timing_v; /* 0x68 */
u32 pol_freq; /* 0x6C */
u32 divisor; /* 0x70 */
u32 global_alpha; /* 0x74 */
u32 size_dig; /* 0x78 */
u32 size_lcd; /* 0x7C */
};
/* VENC Registers */
struct venc_regs {
u32 rev_id; /* 0x00 */
u32 status; /* 0x04 */
u32 f_control; /* 0x08 */
u32 reserve_1; /* 0x0C */
u32 vidout_ctrl; /* 0x10 */
u32 sync_ctrl; /* 0x14 */
u32 reserve_2; /* 0x18 */
u32 llen; /* 0x1C */
u32 flens; /* 0x20 */
u32 hfltr_ctrl; /* 0x24 */
u32 cc_carr_wss_carr; /* 0x28 */
u32 c_phase; /* 0x2C */
u32 gain_u; /* 0x30 */
u32 gain_v; /* 0x34 */
u32 gain_y; /* 0x38 */
u32 black_level; /* 0x3C */
u32 blank_level; /* 0x40 */
u32 x_color; /* 0x44 */
u32 m_control; /* 0x48 */
u32 bstamp_wss_data; /* 0x4C */
u32 s_carr; /* 0x50 */
u32 line21; /* 0x54 */
u32 ln_sel; /* 0x58 */
u32 l21__wc_ctl; /* 0x5C */
u32 htrigger_vtrigger; /* 0x60 */
u32 savid__eavid; /* 0x64 */
u32 flen__fal; /* 0x68 */
u32 lal__phase_reset; /* 0x6C */
u32 hs_int_start_stop_x; /* 0x70 */
u32 hs_ext_start_stop_x; /* 0x74 */
u32 vs_int_start_x; /* 0x78 */
u32 vs_int_stop_x__vs_int_start_y; /* 0x7C */
u32 vs_int_stop_y__vs_ext_start_x; /* 0x80 */
u32 vs_ext_stop_x__vs_ext_start_y; /* 0x84 */
u32 vs_ext_stop_y; /* 0x88 */
u32 reserve_3; /* 0x8C */
u32 avid_start_stop_x; /* 0x90 */
u32 avid_start_stop_y; /* 0x94 */
u32 reserve_4; /* 0x98 */
u32 reserve_5; /* 0x9C */
u32 fid_int_start_x__fid_int_start_y; /* 0xA0 */
u32 fid_int_offset_y__fid_ext_start_x; /* 0xA4 */
u32 fid_ext_start_y__fid_ext_offset_y; /* 0xA8 */
u32 reserve_6; /* 0xAC */
u32 tvdetgp_int_start_stop_x; /* 0xB0 */
u32 tvdetgp_int_start_stop_y; /* 0xB4 */
u32 gen_ctrl; /* 0xB8 */
u32 reserve_7; /* 0xBC */
u32 reserve_8; /* 0xC0 */
u32 output_control; /* 0xC4 */
u32 dac_b__dac_c; /* 0xC8 */
u32 height_width; /* 0xCC */
};
/* Few Register Offsets */
#define FRAME_MODE_SHIFT 1
#define TFTSTN_SHIFT 3
#define DATALINES_SHIFT 8
/* Enabling Display controller */
#define LCD_ENABLE 1
#define DIG_ENABLE (1 << 1)
#define GO_LCD (1 << 5)
#define GO_DIG (1 << 6)
#define GP_OUT0 (1 << 15)
#define GP_OUT1 (1 << 16)
#define DISPC_ENABLE (LCD_ENABLE | \
DIG_ENABLE | \
GO_LCD | \
GO_DIG | \
GP_OUT0| \
GP_OUT1)
/* Configure VENC DSS Params */
#define VENC_CLK_ENABLE (1 << 3)
#define DAC_DEMEN (1 << 4)
#define DAC_POWERDN (1 << 5)
#define VENC_OUT_SEL (1 << 6)
#define DIG_LPP_SHIFT 16
#define VENC_DSS_CONFIG (VENC_CLK_ENABLE | \
DAC_DEMEN | \
DAC_POWERDN | \
VENC_OUT_SEL)
/*
* Panel Configuration
*/
struct panel_config {
u32 timing_h;
u32 timing_v;
u32 pol_freq;
u32 divisor;
u32 lcd_size;
u32 panel_type;
u32 data_lines;
u32 load_mode;
u32 panel_color;
};
/*
* Generic DSS Functions
*/
void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
u32 height, u32 width);
void omap3_dss_panel_config(const struct panel_config *panel_cfg);
void omap3_dss_enable(void);
#endif /* DSS_H */

50
arch/arm/include/asm/arch-omap3/gpio.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _GPIO_OMAP3_H
#define _GPIO_OMAP3_H
#include <asm/omap_gpio.h>
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
#define OMAP34XX_GPIO4_BASE 0x49054000
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
#endif /* _GPIO_OMAP3_H */

8
arch/arm/include/asm/arch-omap3/omap3.h
View File

@@ -100,14 +100,6 @@ struct s32ktimer {
#endif /* __ASSEMBLY__ */
/* OMAP3 GPIO registers */
#define OMAP34XX_GPIO1_BASE 0x48310000
#define OMAP34XX_GPIO2_BASE 0x49050000
#define OMAP34XX_GPIO3_BASE 0x49052000
#define OMAP34XX_GPIO4_BASE 0x49054000
#define OMAP34XX_GPIO5_BASE 0x49056000
#define OMAP34XX_GPIO6_BASE 0x49058000
#ifndef __ASSEMBLY__
struct gpio {
unsigned char res1[0x34];

12
arch/arm/include/asm/arch-omap4/clocks.h
View File

@@ -679,12 +679,12 @@ struct dpll_regs {
struct dpll_params {
u32 m;
u32 n;
u8 m2;
u8 m3;
u8 m4;
u8 m5;
u8 m6;
u8 m7;
s8 m2;
s8 m3;
s8 m4;
s8 m5;
s8 m6;
s8 m7;
};
#endif /* _CLOCKS_OMAP4_H_ */

50
arch/arm/include/asm/arch-omap4/gpio.h Normal file
View File

@@ -0,0 +1,50 @@
/*
* Copyright (c) 2009 Wind River Systems, Inc.
* Tom Rix <Tom.Rix@windriver.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* This work is derived from the linux 2.6.27 kernel source
* To fetch, use the kernel repository
* git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git
* Use the v2.6.27 tag.
*
* Below is the original's header including its copyright
*
* linux/arch/arm/plat-omap/gpio.c
*
* Support functions for OMAP GPIO
*
* Copyright (C) 2003-2005 Nokia Corporation
* Written by Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _GPIO_OMAP4_H
#define _GPIO_OMAP4_H
#include <asm/omap_gpio.h>
#define OMAP44XX_GPIO1_BASE 0x4A310000
#define OMAP44XX_GPIO2_BASE 0x48055000
#define OMAP44XX_GPIO3_BASE 0x48057000
#define OMAP44XX_GPIO4_BASE 0x48059000
#define OMAP44XX_GPIO5_BASE 0x4805B000
#define OMAP44XX_GPIO6_BASE 0x4805D000
#endif /* _GPIO_OMAP4_H */

8
arch/arm/include/asm/arch-omap4/omap4.h
View File

@@ -153,12 +153,4 @@ struct s32ktimer {
#define DEV_DATA_PTR_OFFSET 0x18
#define BOOT_MODE_OFFSET 0x8
/* GPIO */
#define OMAP44XX_GPIO1_BASE 0x4A310000
#define OMAP44XX_GPIO2_BASE 0x48055000
#define OMAP44XX_GPIO3_BASE 0x48057000
#define OMAP44XX_GPIO4_BASE 0x48059000
#define OMAP44XX_GPIO5_BASE 0x4805B000
#define OMAP44XX_GPIO6_BASE 0x4805D000
#endif

29
arch/arm/include/asm/arch-s5pc1xx/gpio.h
View File

@@ -126,14 +126,27 @@ struct s5pc110_gpio {
};
/* functions */
void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
static inline unsigned int s5p_gpio_base(int nr)
{
return S5PC110_GPIO_BASE;
}
#define s5pc110_gpio_get_nr(bank, pin) \
((((((unsigned int)&(((struct s5pc110_gpio *)S5PC110_GPIO_BASE)->bank))\
- S5PC110_GPIO_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#endif
/* Pin configurations */

45
arch/arm/include/asm/arch-s5pc2xx/gpio.h
View File

@@ -80,14 +80,43 @@ struct s5pc210_gpio_part3 {
};
/* functions */
void gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg);
void s5p_gpio_direction_output(struct s5p_gpio_bank *bank, int gpio, int en);
void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en);
unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio);
void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode);
void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode);
/* GPIO pins per bank */
#define GPIO_PER_BANK 8
#define s5pc210_gpio_part1_get_nr(bank, pin) \
((((((unsigned int) &(((struct s5pc210_gpio_part1 *) \
S5PC210_GPIO_PART1_BASE)->bank)) \
- S5PC210_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin)
#define GPIO_PART1_MAX ((sizeof(struct s5pc210_gpio_part1) \
/ sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
#define s5pc210_gpio_part2_get_nr(bank, pin) \
(((((((unsigned int) &(((struct s5pc210_gpio_part2 *) \
S5PC210_GPIO_PART2_BASE)->bank)) \
- S5PC210_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + GPIO_PART1_MAX)
static inline unsigned int s5p_gpio_base(int nr)
{
if (nr < GPIO_PART1_MAX)
return S5PC210_GPIO_PART1_BASE;
else
return S5PC210_GPIO_PART2_BASE;
return 0;
}
#endif
/* Pin configurations */

127
arch/arm/include/asm/arch-tegra2/clk_rst.h
View File

@@ -24,15 +24,34 @@
#ifndef _CLK_RST_H_
#define _CLK_RST_H_
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
uint pll_out; /* output control */
uint reserved;
uint pll_misc; /* other misc things */
};
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll_simple {
uint pll_base; /* the control register */
uint pll_misc; /* other misc things */
};
/*
* Most PLLs use the clk_pll structure, but some have a simpler two-member
* structure for which we use clk_pll_simple. The reason for this non-
* othogonal setup is not stated.
*/
#define TEGRA_CLK_PLLS 6
#define TEGRA_CLK_SIMPLE_PLLS 3 /* Number of simple PLLs */
#define TEGRA_CLK_REGS 3 /* Number of clock enable registers */
/* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
struct clk_rst_ctlr {
uint crc_rst_src; /* _RST_SOURCE_0, 0x00 */
uint crc_rst_dev_l; /* _RST_DEVICES_L_0, 0x04 */
uint crc_rst_dev_h; /* _RST_DEVICES_H_0, 0x08 */
uint crc_rst_dev_u; /* _RST_DEVICES_U_0, 0x0C */
uint crc_clk_out_enb_l; /* _CLK_OUT_ENB_L_0, 0x10 */
uint crc_clk_out_enb_h; /* _CLK_OUT_ENB_H_0, 0x14 */
uint crc_clk_out_enb_u; /* _CLK_OUT_ENB_U_0, 0x18 */
uint crc_rst_src; /* _RST_SOURCE_0,0x00 */
uint crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */
uint crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */
uint crc_reserved0; /* reserved_0, 0x1C */
uint crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0,0x20 */
uint crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */
@@ -52,44 +71,11 @@ struct clk_rst_ctlr {
uint crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */
uint crc_reserved2[8]; /* reserved_2[8], 0x60-7C */
uint crc_pllc_base; /* _PLLC_BASE_0, 0x80 */
uint crc_pllc_out; /* _PLLC_OUT_0, 0x84 */
uint crc_reserved3; /* reserved_3, 0x88 */
uint crc_pllc_misc; /* _PLLC_MISC_0, 0x8C */
struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */
uint crc_pllm_base; /* _PLLM_BASE_0, 0x90 */
uint crc_pllm_out; /* _PLLM_OUT_0, 0x94 */
uint crc_reserved4; /* reserved_4, 0x98 */
uint crc_pllm_misc; /* _PLLM_MISC_0, 0x9C */
/* PLLs from 0xe0 to 0xf4 */
struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS];
uint crc_pllp_base; /* _PLLP_BASE_0, 0xA0 */
uint crc_pllp_outa; /* _PLLP_OUTA_0, 0xA4 */
uint crc_pllp_outb; /* _PLLP_OUTB_0, 0xA8 */
uint crc_pllp_misc; /* _PLLP_MISC_0, 0xAC */
uint crc_plla_base; /* _PLLA_BASE_0, 0xB0 */
uint crc_plla_out; /* _PLLA_OUT_0, 0xB4 */
uint crc_reserved5; /* reserved_5, 0xB8 */
uint crc_plla_misc; /* _PLLA_MISC_0, 0xBC */
uint crc_pllu_base; /* _PLLU_BASE_0, 0xC0 */
uint crc_reserved6; /* _reserved_6, 0xC4 */
uint crc_reserved7; /* _reserved_7, 0xC8 */
uint crc_pllu_misc; /* _PLLU_MISC_0, 0xCC */
uint crc_plld_base; /* _PLLD_BASE_0, 0xD0 */
uint crc_reserved8; /* _reserved_8, 0xD4 */
uint crc_reserved9; /* _reserved_9, 0xD8 */
uint crc_plld_misc; /* _PLLD_MISC_0, 0xDC */
uint crc_pllx_base; /* _PLLX_BASE_0, 0xE0 */
uint crc_pllx_misc; /* _PLLX_MISC_0, 0xE4 */
uint crc_plle_base; /* _PLLE_BASE_0, 0xE8 */
uint crc_plle_misc; /* _PLLE_MISC_0, 0xEC */
uint crc_plls_base; /* _PLLS_BASE_0, 0xF0 */
uint crc_plls_misc; /* _PLLS_MISC_0, 0xF4 */
uint crc_reserved10; /* _reserved_10, 0xF8 */
uint crc_reserved11; /* _reserved_11, 0xFC */
@@ -154,46 +140,37 @@ struct clk_rst_ctlr {
uint crc_cpu_cmplx_clr; /* _CPU_CMPLX_CLR_0, 0x344 */
};
#define PLL_BYPASS (1 << 31)
#define PLL_ENABLE (1 << 30)
#define PLL_BASE_OVRRIDE (1 << 28)
#define PLL_DIVP (1 << 20) /* post divider, b22:20 */
#define PLL_DIVM 0x0C /* input divider, b4:0 */
/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
#define CPU1_CLK_STP_SHIFT 9
#define SWR_UARTD_RST (1 << 1)
#define CLK_ENB_UARTD (1 << 1)
#define SWR_UARTA_RST (1 << 6)
#define CLK_ENB_UARTA (1 << 6)
#define CPU0_CLK_STP_SHIFT 8
#define CPU0_CLK_STP_MASK (1U << CPU0_CLK_STP_SHIFT)
#define SWR_CPU_RST (1 << 0)
#define CLK_ENB_CPU (1 << 0)
#define SWR_CSITE_RST (1 << 9)
#define CLK_ENB_CSITE (1 << 9)
/* CLK_RST_CONTROLLER_PLLx_BASE_0 */
#define PLL_BYPASS_SHIFT 31
#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT)
#define SET_CPURESET0 (1 << 0)
#define SET_DERESET0 (1 << 4)
#define SET_DBGRESET0 (1 << 12)
#define PLL_ENABLE_SHIFT 30
#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT)
#define SET_CPURESET1 (1 << 1)
#define SET_DERESET1 (1 << 5)
#define SET_DBGRESET1 (1 << 13)
#define PLL_BASE_OVRRIDE_MASK (1U << 28)
#define CLR_CPURESET0 (1 << 0)
#define CLR_DERESET0 (1 << 4)
#define CLR_DBGRESET0 (1 << 12)
#define PLL_DIVP_SHIFT 20
#define CLR_CPURESET1 (1 << 1)
#define CLR_DERESET1 (1 << 5)
#define CLR_DBGRESET1 (1 << 13)
#define PLL_DIVN_SHIFT 8
#define CPU0_CLK_STP (1 << 8)
#define CPU1_CLK_STP (1 << 9)
#define PLL_DIVM_SHIFT 0
#define CPCON (1 << 8)
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
#define SWR_SDMMC4_RST (1 << 15)
#define CLK_ENB_SDMMC4 (1 << 15)
#define SWR_SDMMC3_RST (1 << 5)
#define CLK_ENB_SDMMC3 (1 << 5)
#define PLL_LFCON_SHIFT 4
#define PLLU_VCO_FREQ_SHIFT 20
/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
#define OSC_FREQ_SHIFT 30
#define OSC_FREQ_MASK (3U << OSC_FREQ_SHIFT)
#endif /* CLK_RST_H */

263
arch/arm/include/asm/arch-tegra2/clock.h Normal file
View File

@@ -0,0 +1,263 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 clock control functions */
#ifndef _CLOCK_H
/* Set of oscillator frequencies supported in the internal API. */
enum clock_osc_freq {
/* All in MHz, so 13_0 is 13.0MHz */
CLOCK_OSC_FREQ_13_0,
CLOCK_OSC_FREQ_19_2,
CLOCK_OSC_FREQ_12_0,
CLOCK_OSC_FREQ_26_0,
CLOCK_OSC_FREQ_COUNT,
};
/* The PLLs supported by the hardware */
enum clock_pll_id {
CLOCK_PLL_ID_FIRST,
CLOCK_PLL_ID_CGENERAL = CLOCK_PLL_ID_FIRST,
CLOCK_PLL_ID_MEMORY,
CLOCK_PLL_ID_PERIPH,
CLOCK_PLL_ID_AUDIO,
CLOCK_PLL_ID_USB,
CLOCK_PLL_ID_DISPLAY,
/* now the simple ones */
CLOCK_PLL_ID_FIRST_SIMPLE,
CLOCK_PLL_ID_XCPU = CLOCK_PLL_ID_FIRST_SIMPLE,
CLOCK_PLL_ID_EPCI,
CLOCK_PLL_ID_SFROM32KHZ,
CLOCK_PLL_ID_COUNT,
};
/* The clocks supported by the hardware */
enum periph_id {
PERIPH_ID_FIRST,
/* Low word: 31:0 */
PERIPH_ID_CPU = PERIPH_ID_FIRST,
PERIPH_ID_RESERVED1,
PERIPH_ID_RESERVED2,
PERIPH_ID_AC97,
PERIPH_ID_RTC,
PERIPH_ID_TMR,
PERIPH_ID_UART1,
PERIPH_ID_UART2,
/* 8 */
PERIPH_ID_GPIO,
PERIPH_ID_SDMMC2,
PERIPH_ID_SPDIF,
PERIPH_ID_I2S1,
PERIPH_ID_I2C1,
PERIPH_ID_NDFLASH,
PERIPH_ID_SDMMC1,
PERIPH_ID_SDMMC4,
/* 16 */
PERIPH_ID_TWC,
PERIPH_ID_PWC,
PERIPH_ID_I2S2,
PERIPH_ID_EPP,
PERIPH_ID_VI,
PERIPH_ID_2D,
PERIPH_ID_USBD,
PERIPH_ID_ISP,
/* 24 */
PERIPH_ID_3D,
PERIPH_ID_IDE,
PERIPH_ID_DISP2,
PERIPH_ID_DISP1,
PERIPH_ID_HOST1X,
PERIPH_ID_VCP,
PERIPH_ID_RESERVED30,
PERIPH_ID_CACHE2,
/* Middle word: 63:32 */
PERIPH_ID_MEM,
PERIPH_ID_AHBDMA,
PERIPH_ID_APBDMA,
PERIPH_ID_RESERVED35,
PERIPH_ID_KBC,
PERIPH_ID_STAT_MON,
PERIPH_ID_PMC,
PERIPH_ID_FUSE,
/* 40 */
PERIPH_ID_KFUSE,
PERIPH_ID_SBC1,
PERIPH_ID_SNOR,
PERIPH_ID_SPI1,
PERIPH_ID_SBC2,
PERIPH_ID_XIO,
PERIPH_ID_SBC3,
PERIPH_ID_DVC_I2C,
/* 48 */
PERIPH_ID_DSI,
PERIPH_ID_TVO,
PERIPH_ID_MIPI,
PERIPH_ID_HDMI,
PERIPH_ID_CSI,
PERIPH_ID_TVDAC,
PERIPH_ID_I2C2,
PERIPH_ID_UART3,
/* 56 */
PERIPH_ID_RESERVED56,
PERIPH_ID_EMC,
PERIPH_ID_USB2,
PERIPH_ID_USB3,
PERIPH_ID_MPE,
PERIPH_ID_VDE,
PERIPH_ID_BSEA,
PERIPH_ID_BSEV,
/* Upper word 95:64 */
PERIPH_ID_SPEEDO,
PERIPH_ID_UART4,
PERIPH_ID_UART5,
PERIPH_ID_I2C3,
PERIPH_ID_SBC4,
PERIPH_ID_SDMMC3,
PERIPH_ID_PCIE,
PERIPH_ID_OWR,
/* 72 */
PERIPH_ID_AFI,
PERIPH_ID_CORESIGHT,
PERIPH_ID_RESERVED74,
PERIPH_ID_AVPUCQ,
PERIPH_ID_RESERVED76,
PERIPH_ID_RESERVED77,
PERIPH_ID_RESERVED78,
PERIPH_ID_RESERVED79,
/* 80 */
PERIPH_ID_RESERVED80,
PERIPH_ID_RESERVED81,
PERIPH_ID_RESERVED82,
PERIPH_ID_RESERVED83,
PERIPH_ID_IRAMA,
PERIPH_ID_IRAMB,
PERIPH_ID_IRAMC,
PERIPH_ID_IRAMD,
/* 88 */
PERIPH_ID_CRAM2,
PERIPH_ID_COUNT,
};
/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
#define PERIPH_REG(id) ((id) >> 5)
/* Mask value for a clock (within PERIPH_REG(id)) */
#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
/* return 1 if a PLL ID is in range */
#define clock_pll_id_isvalid(id) ((id) >= CLOCK_PLL_ID_FIRST && \
(id) < CLOCK_PLL_ID_COUNT)
/* return 1 if a peripheral ID is in range */
#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
(id) < PERIPH_ID_COUNT)
/* PLL stabilization delay in usec */
#define CLOCK_PLL_STABLE_DELAY_US 300
/* return the current oscillator clock frequency */
enum clock_osc_freq clock_get_osc_freq(void);
/*
* Start PLL using the provided configuration parameters.
*
* @param id clock id
* @param divm input divider
* @param divn feedback divider
* @param divp post divider 2^n
* @param cpcon charge pump setup control
* @param lfcon loop filter setup control
*
* @returns monotonic time in us that the PLL will be stable
*/
unsigned long clock_start_pll(enum clock_pll_id id, u32 divm, u32 divn,
u32 divp, u32 cpcon, u32 lfcon);
/*
* Enable a clock
*
* @param id clock id
*/
void clock_enable(enum periph_id clkid);
/*
* Set whether a clock is enabled or disabled.
*
* @param id clock id
* @param enable 1 to enable, 0 to disable
*/
void clock_set_enable(enum periph_id clkid, int enable);
/*
* Reset a peripheral. This puts it in reset, waits for a delay, then takes
* it out of reset and waits for th delay again.
*
* @param periph_id peripheral to reset
* @param us_delay time to delay in microseconds
*/
void reset_periph(enum periph_id periph_id, int us_delay);
/*
* Put a peripheral into or out of reset.
*
* @param periph_id peripheral to reset
* @param enable 1 to put into reset, 0 to take out of reset
*/
void reset_set_enable(enum periph_id periph_id, int enable);
/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
enum crc_reset_id {
/* Things we can hold in reset for each CPU */
crc_rst_cpu = 1,
crc_rst_de = 1 << 2, /* What is de? */
crc_rst_watchdog = 1 << 3,
crc_rst_debug = 1 << 4,
};
/*
* Put parts of the CPU complex into or out of reset.\
*
* @param cpu cpu number (0 or 1 on Tegra2)
* @param which which parts of the complex to affect (OR of crc_reset_id)
* @param reset 1 to assert reset, 0 to de-assert
*/
void reset_cmplx_set_enable(int cpu, int which, int reset);
#endif

161
arch/arm/include/asm/arch-tegra2/pinmux.h
View File

@@ -24,6 +24,142 @@
#ifndef _PINMUX_H_
#define _PINMUX_H_
/* Pins which we can set to tristate or normal */
enum pmux_pin {
/* APB_MISC_PP_TRISTATE_REG_A_0 */
PIN_ATA,
PIN_ATB,
PIN_ATC,
PIN_ATD,
PIN_CDEV1,
PIN_CDEV2,
PIN_CSUS,
PIN_DAP1,
PIN_DAP2,
PIN_DAP3,
PIN_DAP4,
PIN_DTA,
PIN_DTB,
PIN_DTC,
PIN_DTD,
PIN_DTE,
PIN_GPU,
PIN_GPV,
PIN_I2CP,
PIN_IRTX,
PIN_IRRX,
PIN_KBCB,
PIN_KBCA,
PIN_PMC,
PIN_PTA,
PIN_RM,
PIN_KBCE,
PIN_KBCF,
PIN_GMA,
PIN_GMC,
PIN_SDMMC1,
PIN_OWC,
/* 32: APB_MISC_PP_TRISTATE_REG_B_0 */
PIN_GME,
PIN_SDC,
PIN_SDD,
PIN_RESERVED0,
PIN_SLXA,
PIN_SLXC,
PIN_SLXD,
PIN_SLXK,
PIN_SPDI,
PIN_SPDO,
PIN_SPIA,
PIN_SPIB,
PIN_SPIC,
PIN_SPID,
PIN_SPIE,
PIN_SPIF,
PIN_SPIG,
PIN_SPIH,
PIN_UAA,
PIN_UAB,
PIN_UAC,
PIN_UAD,
PIN_UCA,
PIN_UCB,
PIN_RESERVED1,
PIN_ATE,
PIN_KBCC,
PIN_RESERVED2,
PIN_RESERVED3,
PIN_GMB,
PIN_GMD,
PIN_DDC,
/* 64: APB_MISC_PP_TRISTATE_REG_C_0 */
PIN_LD0,
PIN_LD1,
PIN_LD2,
PIN_LD3,
PIN_LD4,
PIN_LD5,
PIN_LD6,
PIN_LD7,
PIN_LD8,
PIN_LD9,
PIN_LD10,
PIN_LD11,
PIN_LD12,
PIN_LD13,
PIN_LD14,
PIN_LD15,
PIN_LD16,
PIN_LD17,
PIN_LHP0,
PIN_LHP1,
PIN_LHP2,
PIN_LVP0,
PIN_LVP1,
PIN_HDINT,
PIN_LM0,
PIN_LM1,
PIN_LVS,
PIN_LSC0,
PIN_LSC1,
PIN_LSCK,
PIN_LDC,
PIN_LCSN,
/* 96: APB_MISC_PP_TRISTATE_REG_D_0 */
PIN_LSPI,
PIN_LSDA,
PIN_LSDI,
PIN_LPW0,
PIN_LPW1,
PIN_LPW2,
PIN_LDI,
PIN_LHS,
PIN_LPP,
PIN_RESERVED4,
PIN_KBCD,
PIN_GPU7,
PIN_DTF,
PIN_UDA,
PIN_CRTP,
PIN_SDB,
};
#define TEGRA_TRISTATE_REGS 4
/* APB MISC Pin Mux and Tristate (APB_MISC_PP_) registers */
struct pmux_tri_ctlr {
uint pmt_reserved0; /* ABP_MISC_PP_ reserved offset 00 */
@@ -31,10 +167,7 @@ struct pmux_tri_ctlr {
uint pmt_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 08 */
uint pmt_reserved2; /* ABP_MISC_PP_ reserved offset 0C */
uint pmt_reserved3; /* ABP_MISC_PP_ reserved offset 10 */
uint pmt_tri_a; /* _TRI_STATE_REG_A_0, offset 14 */
uint pmt_tri_b; /* _TRI_STATE_REG_B_0, offset 18 */
uint pmt_tri_c; /* _TRI_STATE_REG_C_0, offset 1C */
uint pmt_tri_d; /* _TRI_STATE_REG_D_0, offset 20 */
uint pmt_tri[TEGRA_TRISTATE_REGS]; /* _TRI_STATE_REG_A/B/C/D_0 14-20 */
uint pmt_cfg_ctl; /* _CONFIG_CTL_0, offset 24 */
uint pmt_reserved[22]; /* ABP_MISC_PP_ reserved offs 28-7C */
@@ -48,14 +181,16 @@ struct pmux_tri_ctlr {
uint pmt_ctl_g; /* _PIN_MUX_CTL_G_0, offset 98 */
};
#define Z_GMC (1 << 29)
#define Z_IRRX (1 << 20)
#define Z_IRTX (1 << 19)
#define Z_GMA (1 << 28)
#define Z_GME (1 << 0)
#define Z_ATB (1 << 1)
#define Z_SDB (1 << 15)
#define Z_SDC (1 << 1)
#define Z_SDD (1 << 2)
/* Converts a pin number to a tristate register: 0=A, 1=B, 2=C, 3=D */
#define TRISTATE_REG(id) ((id) >> 5)
/* Mask value for a tristate (within TRISTATE_REG(id)) */
#define TRISTATE_MASK(id) (1 << ((id) & 0x1f))
/* Set a pin to tristate */
void pinmux_tristate_enable(enum pmux_pin pin);
/* Set a pin to normal (non tristate) */
void pinmux_tristate_disable(enum pmux_pin pin);
#endif /* PINMUX_H */

30
arch/arm/include/asm/arch-tegra2/timer.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Tegra2 timer functions */
#ifndef _TEGRA2_TIMER_H
#define _TEGRA2_TIMER_H
/* returns the current monotonic timer value in microseconds */
unsigned long timer_get_us(void);
#endif

19
arch/arm/lib/board.c
View File

@@ -275,10 +275,6 @@ void board_init_f(ulong bootflag)
gd->mon_len = _bss_end_ofs;
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
if ((*init_fnc_ptr)() != 0) {
hang ();
@@ -376,6 +372,11 @@ void board_init_f(ulong bootflag)
gd->bd = bd;
debug("Reserving %zu Bytes for Board Info at: %08lx\n",
sizeof (bd_t), addr_sp);
#ifdef CONFIG_MACH_TYPE
gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
#endif
addr_sp -= sizeof (gd_t);
id = (gd_t *) addr_sp;
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
@@ -451,11 +452,9 @@ void board_init_r(gd_t *id, ulong dest_addr)
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
monitor_flash_len = _end_ofs;
/*
* Enable D$:
* I$, if needed, must be already enabled in start.S
*/
dcache_enable();
/* Enable caches */
enable_caches();
debug("monitor flash len: %08lX\n", monitor_flash_len);
board_init(); /* Setup chipselects */
@@ -626,7 +625,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
pram += (LOGBUFF_LEN + LOGBUFF_OVERHEAD) / 1024;
#endif
#endif
sprintf((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
sprintf((char *)memsz, "%ldk", (gd->ram_size / 1024) - pram);
setenv("mem", (char *)memsz);
}
#endif

15
arch/arm/lib/cache-pl310.c
View File

@@ -26,6 +26,7 @@
#include <asm/armv7.h>
#include <asm/pl310.h>
#include <config.h>
#include <common.h>
struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
@@ -89,21 +90,23 @@ void v7_outer_cache_inval_range(u32 start, u32 stop)
u32 pa, line_size = 32;
/*
* If start address is not aligned to cache-line flush the first
* line to prevent affecting somebody else's buffer
* If start address is not aligned to cache-line do not
* invalidate the first cache-line
*/
if (start & (line_size - 1)) {
v7_outer_cache_flush_range(start, start + 1);
printf("ERROR: %s - start address is not aligned - 0x%08x\n",
__func__, start);
/* move to next cache line */
start = (start + line_size - 1) & ~(line_size - 1);
}
/*
* If stop address is not aligned to cache-line flush the last
* line to prevent affecting somebody else's buffer
* If stop address is not aligned to cache-line do not
* invalidate the last cache-line
*/
if (stop & (line_size - 1)) {
v7_outer_cache_flush_range(stop, stop + 1);
printf("ERROR: %s - stop address is not aligned - 0x%08x\n",
__func__, stop);
/* align to the beginning of this cache line */
stop &= ~(line_size - 1);
}

12
arch/arm/lib/cache.c
View File

@@ -53,3 +53,15 @@ void __flush_dcache_all(void)
}
void flush_dcache_all(void)
__attribute__((weak, alias("__flush_dcache_all")));
/*
* Default implementation of enable_caches()
* Real implementation should be in platform code
*/
void __enable_caches(void)
{
puts("WARNING: Caches not enabled\n");
}
void enable_caches(void)
__attribute__((weak, alias("__enable_caches")));

3
arch/arm/lib/memcpy.S
View File

@@ -60,6 +60,9 @@
.globl memcpy
memcpy:
cmp r0, r1
moveq pc, lr
enter r4, lr
subs r2, r2, #4