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sun6i: Poke magic sram controller register to avoid cache issues

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Without this the cache will only work in write-through mode, and as soon as
it is put in write-back mode things break.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
This commit is contained in:
Hans de Goede 2014-11-02 16:55:09 +01:00
parent 9a07eb0ba0
commit 6dbfda81c0
1 changed files with 5 additions and 0 deletions
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5
arch/arm/cpu/armv7/sunxi/board.c
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@ -114,6 +114,11 @@ void reset_cpu(ulong addr)
/* do some early init */
void s_init(void)
{
#if defined CONFIG_SPL_BUILD && defined CONFIG_MACH_SUN6I
/* Magic (undocmented) value taken from boot0, without this DRAM
* access gets messed up (seems cache related) */
setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#endif
#if !defined CONFIG_SPL_BUILD && (defined CONFIG_MACH_SUN7I || \
defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I)
/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */