armv8: ls1088a: Add NXP LS1088A SoC support

LS1088A is compliant with the Layerscape Chassis Generation 3 with
eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4
SDRAM memory controller with ECC, Data path acceleration architecture
2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs),
QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc.

Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com>
Signed-off-by: Raghav Dogra <raghav.dogra@nxp.com>
Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com>
[YS: Revised commit message]
Reviewed-by: York Sun <york.sun@nxp.com>

arch/arm/include/asm/arch-fsl-layerscape/config.h

@@ -116,6 +116,67 @@
 #define CONFIG_SYS_FSL_ERRATUM_A008751
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
+
+#elif defined(CONFIG_ARCH_LS1088A)
+#define CONFIG_SYS_FSL_NUM_CC_PLLS		3
+#define CONFIG_SYS_FSL_CLUSTER_CLOCKS		{ 1, 1 }
+#define CONFIG_GICV3
+#define CONFIG_FSL_TZPC_BP147
+#define CONFIG_FSL_TZASC_400
+#define CONFIG_SYS_PAGE_SIZE		0x10000
+
+#define	SRDS_MAX_LANES	4
+
+/* TZ Protection Controller Definitions */
+#define TZPC_BASE				0x02200000
+#define TZPCR0SIZE_BASE				(TZPC_BASE)
+#define TZPCDECPROT_0_STAT_BASE			(TZPC_BASE + 0x800)
+#define TZPCDECPROT_0_SET_BASE			(TZPC_BASE + 0x804)
+#define TZPCDECPROT_0_CLR_BASE			(TZPC_BASE + 0x808)
+#define TZPCDECPROT_1_STAT_BASE			(TZPC_BASE + 0x80C)
+#define TZPCDECPROT_1_SET_BASE			(TZPC_BASE + 0x810)
+#define TZPCDECPROT_1_CLR_BASE			(TZPC_BASE + 0x814)
+#define TZPCDECPROT_2_STAT_BASE			(TZPC_BASE + 0x818)
+#define TZPCDECPROT_2_SET_BASE			(TZPC_BASE + 0x81C)
+#define TZPCDECPROT_2_CLR_BASE			(TZPC_BASE + 0x820)
+
+/* Generic Interrupt Controller Definitions */
+#define GICD_BASE			0x06000000
+#define GICR_BASE			0x06100000
+
+/* SMMU Defintions */
+#define SMMU_BASE			0x05000000 /* GR0 Base */
+
+/* DDR */
+#define CONFIG_SYS_DDR_BLOCK1_SIZE	((phys_size_t)2 << 30)
+#define CONFIG_MAX_MEM_MAPPED		CONFIG_SYS_DDR_BLOCK1_SIZE
+
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_CCSR_SCFG_LE
+#define CONFIG_SYS_FSL_ESDHC_LE
+#define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_FSL_PEX_LUT_LE
+
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* SFP */
+#define CONFIG_SYS_FSL_SFP_VER_3_4
+#define CONFIG_SYS_FSL_SFP_LE
+#define CONFIG_SYS_FSL_SRK_LE
+
+/* Security Monitor */
+#define CONFIG_SYS_FSL_SEC_MON_LE
+
+/* Secure Boot */
+#define CONFIG_ESBC_HDR_LS
+
+/* DCFG - GUR */
+#define CONFIG_SYS_FSL_CCSR_GUR_LE
+#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
+#define CONFIG_SYS_FSL_OCRAM_BASE	0x18000000 /* initial RAM */
+#define SYS_FSL_OCRAM_SPACE_SIZE	0x00200000 /* 2M space */
+#define CONFIG_SYS_FSL_OCRAM_SIZE	0x00020000 /* Real size 128K */
+
 #elif defined(CONFIG_FSL_LSCH2)
 #define CONFIG_SYS_FSL_OCRAM_BASE		0x10000000 /* initial RAM */
 #define SYS_FSL_OCRAM_SPACE_SIZE		0x00200000 /* 2M space */
@@ -218,7 +279,6 @@
 #define GICC_BASE		0x01420000
 
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
-
 #else
 #error SoC not defined
 #endif

arch/arm/include/asm/arch-fsl-layerscape/cpu.h

@@ -24,6 +24,10 @@ static struct cpu_type cpu_type_list[] = {
 	CPU_TYPE_ENTRY(LS1026A, LS1026A, 2),
 	CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
 	CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
+	CPU_TYPE_ENTRY(LS1088A, LS1088A, 8),
+	CPU_TYPE_ENTRY(LS1084A, LS1084A, 8),
+	CPU_TYPE_ENTRY(LS1048A, LS1048A, 4),
+	CPU_TYPE_ENTRY(LS1044A, LS1044A, 4),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF

arch/arm/include/asm/arch-fsl-layerscape/fsl_serdes.h

@@ -9,7 +9,7 @@
 
 #include <config.h>
 
-#ifdef CONFIG_ARCH_LS2080A
+#ifdef CONFIG_FSL_LSCH3
 enum srds_prtcl {
 	/*
 	 * Nobody will check whether the device 'NONE' has been configured,
@@ -158,6 +158,7 @@ void fsl_serdes_init(void);
 int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
 enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
 int is_serdes_prtcl_valid(int serdes, u32 prtcl);
+int serdes_get_number(int serdes, int cfg);
 
 #ifdef CONFIG_FSL_LSCH2
 const char *serdes_clock_to_string(u32 clock);

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

@@ -246,6 +246,17 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT
 #define FSL_CHASSIS3_SRDS1_REGSR	29
 #define FSL_CHASSIS3_SRDS2_REGSR	29
+#elif defined(CONFIG_ARCH_LS1088A)
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK	0xFFFF0000
+#define	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT	16
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK	0x0000FFFF
+#define	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT	0
+#define FSL_CHASSIS3_SRDS1_PRTCL_MASK	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS1_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR29_SRDS1_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS2_PRTCL_MASK	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_MASK
+#define FSL_CHASSIS3_SRDS2_PRTCL_SHIFT	FSL_CHASSIS3_RCWSR30_SRDS2_PRTCL_SHIFT
+#define FSL_CHASSIS3_SRDS1_REGSR	29
+#define FSL_CHASSIS3_SRDS2_REGSR	30
 #endif
 #define RCW_SB_EN_REG_INDEX	9
 #define RCW_SB_EN_MASK		0x00000400

arch/arm/include/asm/arch-fsl-layerscape/soc.h

@@ -57,6 +57,10 @@ struct cpu_type {
 #define SVR_LS1023A		0x879208
 #define SVR_LS1046A		0x870700
 #define SVR_LS1026A		0x870708
+#define SVR_LS1048A		0x870320
+#define SVR_LS1084A		0x870302
+#define SVR_LS1088A		0x870300
+#define SVR_LS1044A		0x870322
 #define SVR_LS2045A		0x870120
 #define SVR_LS2080A		0x870110
 #define SVR_LS2085A		0x870100

arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h

@@ -66,12 +66,26 @@
 #define FSL_USB2_STREAM_ID		2
 #define FSL_SDMMC_STREAM_ID		3
 #define FSL_SATA1_STREAM_ID		4
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_SATA2_STREAM_ID		5
+#endif
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_DMA_STREAM_ID		6
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_DMA_STREAM_ID		5
+#endif
 
 /* PCI - programmed in PEXn_LUT */
 #define FSL_PEX_STREAM_ID_START		7
+
+#if defined(CONFIG_ARCH_LS2080A)
 #define FSL_PEX_STREAM_ID_END		22
+#elif defined(CONFIG_ARCH_LS1088A)
+#define FSL_PEX_STREAM_ID_END		18
+#endif
+
 
 /* DPAA2 - set in MC DPC and alloced by MC */
 #define FSL_DPAA2_STREAM_ID_START	23