pico-imx6ul: Add Ethernet support
Pico-imx6ul has a KSZ8081 Ethernet PHY. Add support for it. Signed-off-by: Diego Dorta <diego.dorta@nxp.com> Acked-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
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@ -16,6 +16,8 @@
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#include <asm/imx-common/iomux-v3.h>
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#include <asm/io.h>
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#include <common.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include <linux/sizes.h>
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#include <usb.h>
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@ -34,6 +36,87 @@ DECLARE_GLOBAL_DATA_PTR;
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PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
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PAD_CTL_SPEED_HIGH | \
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PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
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#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
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#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
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static iomux_v3_cfg_t const fec_pads[] = {
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MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
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MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
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MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static void setup_iomux_fec(void)
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{
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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int board_eth_init(bd_t *bis)
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{
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setup_iomux_fec();
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gpio_direction_output(RMII_PHY_RESET, 0);
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/*
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* According to KSZ8081MNX-RNB manual:
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* For warm reset, the reset (RST#) pin should be asserted low for a
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* minimum of 500μs. The strap-in pin values are read and updated
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* at the de-assertion of reset.
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*/
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udelay(500);
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gpio_direction_output(RMII_PHY_RESET, 1);
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/*
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* According to KSZ8081MNX-RNB manual:
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* After the de-assertion of reset, wait a minimum of 100μs before
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* starting programming on the MIIM (MDC/MDIO) interface.
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*/
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udelay(100);
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return fecmxc_initialize(bis);
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}
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static int setup_fec(void)
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{
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struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
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int ret;
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clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
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IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
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ret = enable_fec_anatop_clock(1, ENET_50MHZ);
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if (ret)
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return ret;
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enable_enet_clk(1);
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return 0;
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}
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int board_phy_config(struct phy_device *phydev)
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{
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = imx_ddr_size();
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@ -106,6 +189,7 @@ int board_init(void)
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/* Address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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setup_fec();
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setup_usb();
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return 0;
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@ -17,6 +17,16 @@
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#define CONFIG_DISPLAY_CPUINFO
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#define CONFIG_DISPLAY_BOARDINFO
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/* Network support */
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#define CONFIG_FEC_MXC
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#define CONFIG_MII
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#define IMX_FEC_BASE ENET2_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1
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#define CONFIG_FEC_XCV_TYPE RMII
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#define CONFIG_PHYLIB
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#define CONFIG_PHY_MICREL
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (16 * SZ_1M)
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