tegra20: add USB ULPI init code
This adds the required code to set up a ULPI USB port. It is mostly a port of the Linux ULPI setup code with some tweaks added for more correctness, discovered along the way of debugging this. To use this both CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT have to be set in the board configuration file. Signed-off-by: Lucas Stach <dev@lynxeye.de> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
This commit is contained in:
Lucas Stach
Tom Rini
parent
141288b3a3
commit
6d365ea0ac
3
README
3
README
@ -1268,6 +1268,9 @@ The following options need to be configured:
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viewport is supported.
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To enable the ULPI layer support, define CONFIG_USB_ULPI and
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CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
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If your ULPI phy needs a different reference clock than the
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standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
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the appropriate value in Hz.
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- MMC Support:
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The MMC controller on the Intel PXA is supported. To
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@ -32,9 +32,17 @@
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/uart.h>
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#include <asm/arch/usb.h>
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#include <usb/ulpi.h>
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#include <libfdt.h>
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#include <fdtdec.h>
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#ifdef CONFIG_USB_ULPI
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#ifndef CONFIG_USB_ULPI_VIEWPORT
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#error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
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define CONFIG_USB_ULPI_VIEWPORT"
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#endif
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#endif
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enum {
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USB_PORTS_MAX = 4, /* Maximum ports we allow */
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};
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@ -68,11 +76,13 @@ enum dr_mode {
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struct fdt_usb {
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struct usb_ctlr *reg; /* address of registers in physical memory */
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unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
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unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
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unsigned enabled:1; /* 1 to enable, 0 to disable */
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unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
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enum dr_mode dr_mode; /* dual role mode */
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enum periph_id periph_id;/* peripheral id */
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struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
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struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
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};
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static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
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@ -187,8 +197,8 @@ void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
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*/
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}
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/* set up the USB controller with the parameters provided */
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static int init_usb_controller(struct fdt_usb *config,
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/* set up the UTMI USB controller with the parameters provided */
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static int init_utmi_usb_controller(struct fdt_usb *config,
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struct usb_ctlr *usbctlr, const u32 timing[])
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{
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u32 val;
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@ -297,18 +307,116 @@ static int init_usb_controller(struct fdt_usb *config,
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if (!loop_count)
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return -1;
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return 0;
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}
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/* Disable ICUSB FS/LS transceiver */
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clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
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/* Select UTMI parallel interface */
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clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
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PTS_UTMI << PTS_SHIFT);
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clrbits_le32(&usbctlr->port_sc1, STS);
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static void power_up_port(struct usb_ctlr *usbctlr)
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{
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/* Deassert power down state */
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clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
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UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
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clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
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UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
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return 0;
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}
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#ifdef CONFIG_USB_ULPI
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/* if board file does not set a ULPI reference frequency we default to 24MHz */
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#ifndef CONFIG_ULPI_REF_CLK
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#define CONFIG_ULPI_REF_CLK 24000000
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#endif
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/* set up the ULPI USB controller with the parameters provided */
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static int init_ulpi_usb_controller(struct fdt_usb *config,
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struct usb_ctlr *usbctlr)
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{
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u32 val;
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int loop_count;
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struct ulpi_viewport ulpi_vp;
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/* set up ULPI reference clock on pllp_out4 */
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clock_enable(PERIPH_ID_DEV2_OUT);
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clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
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/* reset ULPI phy */
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if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
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fdtdec_setup_gpio(&config->phy_reset_gpio);
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gpio_direction_output(config->phy_reset_gpio.gpio, 0);
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mdelay(5);
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gpio_set_value(config->phy_reset_gpio.gpio, 1);
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}
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/* Reset the usb controller */
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clock_enable(config->periph_id);
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usbf_reset_controller(config, usbctlr);
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/* enable pinmux bypass */
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setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
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ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
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/* Select ULPI parallel interface */
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clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
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/* enable ULPI transceiver */
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setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
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/* configure ULPI transceiver timings */
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val = 0;
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writel(val, &usbctlr->ulpi_timing_ctrl_1);
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val |= ULPI_DATA_TRIMMER_SEL(4);
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val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
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val |= ULPI_DIR_TRIMMER_SEL(4);
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writel(val, &usbctlr->ulpi_timing_ctrl_1);
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udelay(10);
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val |= ULPI_DATA_TRIMMER_LOAD;
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val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
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val |= ULPI_DIR_TRIMMER_LOAD;
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writel(val, &usbctlr->ulpi_timing_ctrl_1);
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/* set up phy for host operation with external vbus supply */
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ulpi_vp.port_num = 0;
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ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
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if (ulpi_init(&ulpi_vp)) {
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printf("Tegra ULPI viewport init failed\n");
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return -1;
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}
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ulpi_set_vbus(&ulpi_vp, 1, 1);
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ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
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/* enable wakeup events */
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setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
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/* Enable and wait for the phy clock to become valid in 100 ms */
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setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
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for (loop_count = 100000; loop_count != 0; loop_count--) {
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if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
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break;
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udelay(1);
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}
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if (!loop_count)
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return -1;
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clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
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return 0;
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}
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#else
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static int init_ulpi_usb_controller(struct fdt_usb *config,
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struct usb_ctlr *usbctlr)
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{
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printf("No code to set up ULPI controller, please enable"
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"CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
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return -1;
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}
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#endif
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static void config_clock(const u32 timing[])
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{
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clock_start_pll(CLOCK_ID_USB,
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@ -327,24 +435,21 @@ static int add_port(struct fdt_usb *config, const u32 timing[])
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struct usb_ctlr *usbctlr = config->reg;
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if (port_count == USB_PORTS_MAX) {
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debug("tegrausb: Cannot register more than %d ports\n",
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printf("tegrausb: Cannot register more than %d ports\n",
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USB_PORTS_MAX);
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return -1;
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}
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if (init_usb_controller(config, usbctlr, timing)) {
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debug("tegrausb: Cannot init port\n");
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if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
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printf("tegrausb: Cannot init port\n");
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return -1;
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}
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if (config->utmi) {
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/* Disable ICUSB FS/LS transceiver */
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clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
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/* Select UTMI parallel interface */
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clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
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PTS_UTMI << PTS_SHIFT);
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clrbits_le32(&usbctlr->port_sc1, STS);
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power_up_port(usbctlr);
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if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
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printf("tegrausb: Cannot init port\n");
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return -1;
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}
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port[port_count++] = *config;
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return 0;
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@ -406,6 +511,7 @@ int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
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phy = fdt_getprop(blob, node, "phy_type", NULL);
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config->utmi = phy && 0 == strcmp("utmi", phy);
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config->ulpi = phy && 0 == strcmp("ulpi", phy);
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config->enabled = fdtdec_get_is_enabled(blob, node);
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config->has_legacy_mode = fdtdec_get_bool(blob, node,
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"nvidia,has-legacy-mode");
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@ -415,10 +521,13 @@ int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
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return -FDT_ERR_NOTFOUND;
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}
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fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
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debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
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"dr_mode=%d\n", config->enabled, config->has_legacy_mode,
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config->utmi, config->periph_id, config->vbus_gpio.gpio,
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config->dr_mode);
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fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
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&config->phy_reset_gpio);
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debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
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"vbus=%d, phy_reset=%d, dr_mode=%d\n",
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config->enabled, config->has_legacy_mode, config->utmi,
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config->ulpi, config->periph_id, config->vbus_gpio.gpio,
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config->phy_reset_gpio.gpio, config->dr_mode);
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return 0;
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}
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@ -100,10 +100,12 @@ struct usb_ctlr {
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/* 0x410 */
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uint usb1_legacy_ctrl;
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uint reserved12[3];
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uint reserved12[4];
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/* 0x420 */
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uint reserved13[56];
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/* 0x424 */
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uint ulpi_timing_ctrl_0;
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uint ulpi_timing_ctrl_1;
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uint reserved13[53];
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/* 0x500 */
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uint reserved14[64 * 3];
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@ -144,10 +146,24 @@ struct usb_ctlr {
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#define VBUS_SENSE_CTL_AB_SESS_VLD 2
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#define VBUS_SENSE_CTL_A_SESS_VLD 3
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/* USB2_IF_ULPI_TIMING_CTRL_0 */
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#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
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#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
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/* USB2_IF_ULPI_TIMING_CTRL_1 */
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#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
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#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
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#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
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#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
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#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
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#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
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/* USBx_IF_USB_SUSP_CTRL_0 */
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#define ULPI_PHY_ENB (1 << 13)
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#define UTMIP_PHY_ENB (1 << 12)
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#define UTMIP_RESET (1 << 11)
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#define USB_PHY_CLK_VALID (1 << 7)
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#define USB_SUSP_CLR (1 << 5)
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/* USBx_UTMIP_MISC_CFG1 */
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#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
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@ -203,12 +219,15 @@ struct usb_ctlr {
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/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
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#define PTS_SHIFT 30
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#define PTS_MASK (3U << PTS_SHIFT)
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#define PTS_UTMI 0
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#define PTS_UTMI 0
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#define PTS_RESERVED 1
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#define PTS_ULP 2
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#define PTS_ULPI 2
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#define PTS_ICUSB_SER 3
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#define STS (1 << 29)
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#define WKOC (1 << 22)
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#define WKDS (1 << 21)
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#define WKCN (1 << 20)
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/* USBx_UTMIP_XCVR_CFG0_0 */
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#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
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