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rename CFG_ macros to CONFIG_SYS

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Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
2008-10-16 15:01:15 +02:00
committed by Wolfgang Denk
parent 71edc27181
commit 6d0f6bcf33
2039 changed files with 53568 additions and 53568 deletions
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8
cpu/arm926ejs/at91/spi.c
View File

@@ -48,7 +48,7 @@ void AT91F_SpiInit(void)
((AT91_MASTER_CLOCK / AT91_SPI_CLK) << 8),
AT91_BASE_SPI + AT91_SPI_CSR(0));
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS1
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
/* Configure CS1 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -57,7 +57,7 @@ void AT91F_SpiInit(void)
AT91_BASE_SPI + AT91_SPI_CSR(1));
#endif
#ifdef CFG_DATAFLASH_LOGIC_ADDR_CS3
#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
/* Configure CS3 */
writel(AT91_SPI_NCPHA |
(AT91_SPI_DLYBS & DATAFLASH_TCSS) |
@@ -144,11 +144,11 @@ unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
((timeout = get_timer_masked()) < CFG_SPI_WRITE_TOUT));
((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
pDesc->state = IDLE;
if (timeout >= CFG_SPI_WRITE_TOUT) {
if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
printf("Error Timeout\n\r");
return DATAFLASH_ERROR;
}

2
cpu/arm926ejs/at91/timer.c
View File

@@ -130,7 +130,7 @@ ulong get_tbclk(void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

4
cpu/arm926ejs/at91/usb.c
View File

@@ -23,7 +23,7 @@
#include <common.h>
#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
@@ -59,4 +59,4 @@ int usb_cpu_init_fail(void)
return usb_cpu_stop();
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_CPU_INIT) */
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

2
cpu/arm926ejs/cpu.c
View File

@@ -95,7 +95,7 @@ int cpu_init (void)
* setup up stacks if necessary
*/
#ifdef CONFIG_USE_IRQ
IRQ_STACK_START = _armboot_start - CFG_MALLOC_LEN - CFG_GBL_DATA_SIZE - 4;
IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4;
FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ;
#endif
return 0;

2
cpu/arm926ejs/davinci/i2c.c
View File

@@ -104,7 +104,7 @@ void i2c_init(int speed, int slaveadd)
}
psc = 2;
div = (CFG_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10; /* SCLL + SCLH */
REG(I2C_PSC) = psc; /* 27MHz / (2 + 1) = 9MHz */
REG(I2C_SCLL) = (div * 50) / 100; /* 50% Duty */
REG(I2C_SCLH) = div - REG(I2C_SCLL);

48
cpu/arm926ejs/davinci/nand.c
View File

@@ -44,14 +44,14 @@
#include <common.h>
#include <asm/io.h>
#ifdef CFG_USE_NAND
#ifdef CONFIG_SYS_USE_NAND
#if !defined(CONFIG_NAND_LEGACY)
#include <nand.h>
#include <asm/arch/nand_defs.h>
#include <asm/arch/emif_defs.h>
extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
@@ -87,11 +87,11 @@ static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
#endif
}
#ifdef CFG_NAND_HW_ECC
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_NAND_HW_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
/* Linux-compatible ECC uses MTD defaults. */
/* These layouts are not compatible with Linux or RBL/UBL. */
#ifdef CFG_NAND_LARGEPAGE
#ifdef CONFIG_SYS_NAND_LARGEPAGE
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 12,
.eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58},
@@ -103,7 +103,7 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
{.offset = 60, .length = 4}
}
};
#elif defined(CFG_NAND_SMALLPAGE)
#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
static struct nand_ecclayout davinci_nand_ecclayout = {
.eccbytes = 3,
.eccpos = {0, 1, 2},
@@ -113,9 +113,9 @@ static struct nand_ecclayout davinci_nand_ecclayout = {
}
};
#else
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static void nand_davinci_enable_hwecc(struct mtd_info *mtd, int mode)
{
@@ -154,7 +154,7 @@ static u_int32_t nand_davinci_readecc(struct mtd_info *mtd, u_int32_t region)
static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
{
u_int32_t tmp;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
/*
* This is not how you should read ECCs on large page Davinci devices.
* The region parameter gets you ECCs for flash chips on different chip
@@ -191,11 +191,11 @@ static int nand_davinci_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u
*ecc_code++ = tmp;
*ecc_code++ = tmp >> 8;
*ecc_code++ = tmp >> 16;
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
static void nand_davinci_gen_true_ecc(u_int8_t *ecc_buf)
{
u_int32_t tmp = ecc_buf[0] | (ecc_buf[1] << 16) | ((ecc_buf[2] & 0xf0) << 20) | ((ecc_buf[2] & 0x0f) << 8);
@@ -312,12 +312,12 @@ static int nand_davinci_compare_ecc(u_int8_t *ecc_nand, u_int8_t *ecc_calc, u_in
return(-1);
}
}
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *read_ecc, u_char *calc_ecc)
{
struct nand_chip *this = mtd->priv;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
int block_count = 0, i, rc;
block_count = (this->ecc.size/512);
@@ -366,10 +366,10 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, u_char *
return -1;
}
}
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
return(0);
}
#endif /* CFG_NAND_HW_ECC */
#endif /* CONFIG_SYS_NAND_HW_ECC */
static int nand_davinci_dev_ready(struct mtd_info *mtd)
{
@@ -431,32 +431,32 @@ int board_nand_init(struct nand_chip *nand)
nand->IO_ADDR_W = (void __iomem *)NAND_CE0DATA;
nand->chip_delay = 0;
nand->select_chip = nand_davinci_select_chip;
#ifdef CFG_NAND_USE_FLASH_BBT
#ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
nand->options = NAND_USE_FLASH_BBT;
#endif
#ifdef CFG_NAND_HW_ECC
#ifdef CONFIG_SYS_NAND_HW_ECC
nand->ecc.mode = NAND_ECC_HW;
#ifdef CFG_DAVINCI_BROKEN_ECC
#ifdef CONFIG_SYS_DAVINCI_BROKEN_ECC
nand->ecc.layout = &davinci_nand_ecclayout;
#ifdef CFG_NAND_LARGEPAGE
#ifdef CONFIG_SYS_NAND_LARGEPAGE
nand->ecc.size = 2048;
nand->ecc.bytes = 12;
#elif defined(CFG_NAND_SMALLPAGE)
#elif defined(CONFIG_SYS_NAND_SMALLPAGE)
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#else
#error "Either CFG_NAND_LARGEPAGE or CFG_NAND_SMALLPAGE must be defined!"
#error "Either CONFIG_SYS_NAND_LARGEPAGE or CONFIG_SYS_NAND_SMALLPAGE must be defined!"
#endif
#else
nand->ecc.size = 512;
nand->ecc.bytes = 3;
#endif /* CFG_DAVINCI_BROKEN_ECC */
#endif /* CONFIG_SYS_DAVINCI_BROKEN_ECC */
nand->ecc.calculate = nand_davinci_calculate_ecc;
nand->ecc.correct = nand_davinci_correct_data;
nand->ecc.hwctl = nand_davinci_enable_hwecc;
#else
nand->ecc.mode = NAND_ECC_SOFT;
#endif /* CFG_NAND_HW_ECC */
#endif /* CONFIG_SYS_NAND_HW_ECC */
/* Set address of hardware control function */
nand->cmd_ctrl = nand_davinci_hwcontrol;
@@ -472,4 +472,4 @@ int board_nand_init(struct nand_chip *nand)
#else
#error "U-Boot legacy NAND support not available for DaVinci chips"
#endif
#endif /* CFG_USE_NAND */
#endif /* CONFIG_SYS_USE_NAND */

8
cpu/arm926ejs/davinci/timer.c
View File

@@ -54,9 +54,9 @@ typedef volatile struct {
u_int32_t wdtcr;
} davinci_timer;
davinci_timer *timer = (davinci_timer *)CFG_TIMERBASE;
davinci_timer *timer = (davinci_timer *)CONFIG_SYS_TIMERBASE;
#define TIMER_LOAD_VAL (CFG_HZ_CLOCK / CFG_HZ)
#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ)
#define TIM_CLK_DIV 16
static ulong timestamp;
@@ -117,7 +117,7 @@ void udelay(unsigned long usec)
ulong endtime;
signed long diff;
tmo = CFG_HZ_CLOCK / 1000;
tmo = CONFIG_SYS_HZ_CLOCK / 1000;
tmo *= usec;
tmo /= (1000 * TIM_CLK_DIV);
@@ -144,5 +144,5 @@ unsigned long long get_ticks(void)
*/
ulong get_tbclk(void)
{
return CFG_HZ;
return CONFIG_SYS_HZ;
}

18
cpu/arm926ejs/omap/timer.c
View File

@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+8))
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+8))
static ulong timestamp;
static ulong lastdec;
@@ -51,9 +51,9 @@ int timer_init (void)
int32_t val;
/* Start the decrementer ticking down from 0xffffffff */
*((int32_t *) (CFG_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CFG_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CFG_TIMERBASE + CNTL_TIMER)) = val;
*((int32_t *) (CONFIG_SYS_TIMERBASE + LOAD_TIM)) = TIMER_LOAD_VAL;
val = MPUTIM_ST | MPUTIM_AR | MPUTIM_CLOCK_ENABLE | (CONFIG_SYS_PVT << MPUTIM_PTV_BIT);
*((int32_t *) (CONFIG_SYS_TIMERBASE + CNTL_TIMER)) = val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -87,10 +87,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -140,10 +140,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -172,6 +172,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}

12
cpu/arm926ejs/start.S
View File

@@ -165,8 +165,8 @@ copy_loop:
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
sub r0, r0, #CFG_MALLOC_LEN /* malloc area */
sub r0, r0, #CFG_GBL_DATA_SIZE /* bdinfo */
sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
@@ -276,8 +276,8 @@ cpu_init_crit:
stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r2, r2, #(CFG_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
@ get values for "aborted" pc and cpsr (into parm regs)
ldmia r2, {r2 - r3}
add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack
@@ -310,8 +310,8 @@ cpu_init_crit:
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE+CFG_MALLOC_LEN)
sub r13, r13, #(CFG_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
str lr, [r13] @ save caller lr in position 0 of saved stack
mrs lr, spsr @ get the spsr

20
cpu/arm926ejs/versatile/timer.c
View File

@@ -41,7 +41,7 @@
#define TIMER_LOAD_VAL 0xffffffff
/* macro to read the 32 bit timer */
#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
static ulong timestamp;
static ulong lastdec;
@@ -62,9 +62,9 @@ int timer_init (void)
ulong tmr_ctrl_val;
/* 1st disable the Timer */
tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~TIMER_ENABLE;
*(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/*
* The Timer Control Register has one Undefined/Shouldn't Use Bit
@@ -78,11 +78,11 @@ int timer_init (void)
* Tmr Siz : 16 Bit Counter
* Tmr in Wrapping Mode
*/
tmr_ctrl_val = *(volatile ulong *)(CFG_TIMERBASE + 8);
tmr_ctrl_val = *(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8);
tmr_ctrl_val &= ~(TIMER_MODE_MSK | TIMER_INT_EN | TIMER_PRS_MSK | TIMER_SIZE_MSK | TIMER_ONE_SHT );
tmr_ctrl_val |= (TIMER_ENABLE | TIMER_PRS_8S);
*(volatile ulong *)(CFG_TIMERBASE + 8) = tmr_ctrl_val;
*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = tmr_ctrl_val;
/* init the timestamp and lastdec value */
reset_timer_masked();
@@ -116,10 +116,10 @@ void udelay (unsigned long usec)
if(usec >= 1000){ /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
}else{ /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -169,10 +169,10 @@ void udelay_masked (unsigned long usec)
if (usec >= 1000) { /* if "big" number, spread normalization to seconds */
tmo = usec / 1000; /* start to normalize for usec to ticks per sec */
tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */
tmo *= CONFIG_SYS_HZ; /* find number of "ticks" to wait to achieve target */
tmo /= 1000; /* finish normalize. */
} else { /* else small number, don't kill it prior to HZ multiply */
tmo = usec * CFG_HZ;
tmo = usec * CONFIG_SYS_HZ;
tmo /= (1000*1000);
}
@@ -201,6 +201,6 @@ ulong get_tbclk (void)
{
ulong tbclk;
tbclk = CFG_HZ;
tbclk = CONFIG_SYS_HZ;
return tbclk;
}