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Merge tag 'v2021.07-rc5' into next

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Prepare v2021.07-rc5

# gpg: Signature made Mon 28 Jun 2021 03:39:36 PM EDT
# gpg:                using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C
# gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate]

# Conflicts:
#	configs/am64x_evm_r5_defconfig
This commit is contained in:
Tom Rini
2021-06-28 16:22:13 -04:00
parent 67edf2553f 3ef4572110
commit 6d0453d889
1245 changed files with 10274 additions and 2859 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/net/Kconfig
View File

@@ -673,6 +673,14 @@ config SNI_AVE
This driver implements support for the Socionext AVE Ethernet
controller, as found on the Socionext UniPhier family.
config SNI_NETSEC
bool "Socionext NETSEC Ethernet support"
depends on DM_ETH && SYNQUACER_SPI
select PHYLIB
help
This driver implements support for the Socionext SynQuacer NETSEC
ethernet controller, as found on the Socionext SynQuacer family.
source "drivers/net/mscc_eswitch/Kconfig"
config ETHER_ON_FEC1

1
drivers/net/Makefile
View File

@@ -89,6 +89,7 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_FSL_PFE) += pfe_eth/
obj-y += qe/
obj-$(CONFIG_SNI_AVE) += sni_ave.o
obj-$(CONFIG_SNI_NETSEC) += sni_netsec.o
obj-y += ti/
obj-$(CONFIG_MEDIATEK_ETH) += mtk_eth.o
obj-y += mscc_eswitch/

19
drivers/net/dwc_eth_qos.c
View File

@@ -172,8 +172,6 @@ struct eqos_mtl_regs {
#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
#define EQOS_MTL_RXQ0_OPERATION_MODE_FEP BIT(4)
#define EQOS_MTL_RXQ0_OPERATION_MODE_FUP BIT(3)
#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
@@ -321,6 +319,7 @@ struct eqos_priv {
void *rx_pkt;
bool started;
bool reg_access_ok;
bool clk_ck_enabled;
};
/*
@@ -591,12 +590,13 @@ static int eqos_start_clks_stm32(struct udevice *dev)
goto err_disable_clk_rx;
}
if (clk_valid(&eqos->clk_ck)) {
if (clk_valid(&eqos->clk_ck) && !eqos->clk_ck_enabled) {
ret = clk_enable(&eqos->clk_ck);
if (ret < 0) {
pr_err("clk_enable(clk_ck) failed: %d", ret);
goto err_disable_clk_tx;
}
eqos->clk_ck_enabled = true;
}
#endif
@@ -648,8 +648,6 @@ static void eqos_stop_clks_stm32(struct udevice *dev)
clk_disable(&eqos->clk_tx);
clk_disable(&eqos->clk_rx);
clk_disable(&eqos->clk_master_bus);
if (clk_valid(&eqos->clk_ck))
clk_disable(&eqos->clk_ck);
#endif
debug("%s: OK\n", __func__);
@@ -1222,7 +1220,6 @@ static int eqos_start(struct udevice *dev)
}
/* Configure MTL */
writel(0x60, &eqos->mtl_regs->txq0_quantum_weight - 0x100);
/* Enable Store and Forward mode for TX */
/* Program Tx operating mode */
@@ -1236,9 +1233,7 @@ static int eqos_start(struct udevice *dev)
/* Enable Store and Forward mode for RX, since no jumbo frame */
setbits_le32(&eqos->mtl_regs->rxq0_operation_mode,
EQOS_MTL_RXQ0_OPERATION_MODE_RSF |
EQOS_MTL_RXQ0_OPERATION_MODE_FEP |
EQOS_MTL_RXQ0_OPERATION_MODE_FUP);
EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
/* Transmit/Receive queue fifo size; use all RAM for 1 queue */
val = readl(&eqos->mac_regs->hw_feature1);
@@ -1314,12 +1309,6 @@ static int eqos_start(struct udevice *dev)
eqos->config->config_mac <<
EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
clrsetbits_le32(&eqos->mac_regs->rxq_ctrl0,
EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
0x2 <<
EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
/* Multicast and Broadcast Queue Enable */
setbits_le32(&eqos->mac_regs->unused_0a4,
0x00100000);

4
drivers/net/e1000.c
View File

@@ -5673,6 +5673,10 @@ static int e1000_write_hwaddr(struct eth_device *dev)
DEBUGOUT("%s: mac=%pM\n", __func__, mac);
if ((hw->eeprom.type == e1000_eeprom_invm) &&
!(E1000_READ_REG(hw, EECD) & E1000_EECD_FLASH_DETECTED_I210))
return -ENOSYS;
memset(current_mac, 0, 6);
/* Read from EEPROM, not from registers, to make sure

1
drivers/net/e1000.h
View File

@@ -1245,6 +1245,7 @@ struct e1000_hw {
#define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */
#define E1000_EECD_FLUPD_I210 0x00800000 /* Update FLASH */
#define E1000_EECD_FLUDONE_I210 0x04000000 /* Update FLASH done*/
#define E1000_EECD_FLASH_DETECTED_I210 0x00080000 /* FLASH detected */
#define E1000_FLUDONE_ATTEMPTS 20000
#define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */
#define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */

4
drivers/net/fm/eth.c
View File

@@ -288,8 +288,10 @@ static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
/* alloc Rx buffer from main memory */
rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
if (!rx_buf_pool)
if (!rx_buf_pool) {
free(rx_bd_ring_base);
return -ENOMEM;
}
memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);

24
drivers/net/octeontx/smi.c
View File

@@ -314,10 +314,12 @@ read_error:
int octeontx_smi_probe(struct udevice *dev)
{
int ret, subnode, cnt = 0, node = dev_ofnode(dev).of_offset;
struct mii_dev *bus;
struct octeontx_smi_priv *priv;
pci_dev_t bdf = dm_pci_get_bdf(dev);
struct octeontx_smi_priv *priv;
struct mii_dev *bus;
int ret, cnt = 0;
ofnode subnode;
u64 baseaddr;
debug("SMI PCI device: %x\n", bdf);
if (!dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, PCI_REGION_MEM)) {
@@ -325,14 +327,12 @@ int octeontx_smi_probe(struct udevice *dev)
return -1;
}
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"cavium,thunder-8890-mdio-nexus");
fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
"cavium,thunder-8890-mdio");
if (ret)
dev_for_each_subnode(subnode, dev) {
if (!ofnode_device_is_compatible(subnode,
"cavium,thunder-8890-mdio"))
continue;
if (ofnode_read_u64(subnode, "reg", &baseaddr))
continue;
bus = mdio_alloc();
priv = malloc(sizeof(*priv));
if (!bus || !priv) {
@@ -347,9 +347,7 @@ int octeontx_smi_probe(struct udevice *dev)
bus->priv = priv;
priv->mode = CLAUSE22;
priv->baseaddr = (void __iomem *)fdtdec_get_addr(gd->fdt_blob,
subnode,
"reg");
priv->baseaddr = (void __iomem *)baseaddr;
debug("mdio base addr %p\n", priv->baseaddr);
/* use given name or generate its own unique name */

2
drivers/net/pfe_eth/pfe_cmd.c
View File

@@ -418,7 +418,7 @@ static void send_dummy_pkt_to_hif(void)
writel(buf, TMU_PHY_INQ_PKTINFO);
}
static void pfe_command_stop(int argc, char *const argv[])
void pfe_command_stop(int argc, char *const argv[])
{
int pfe_pe_id, hif_stop_loop = 10;
u32 rx_status;

60
drivers/net/pfe_eth/pfe_firmware.c
View File

@@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2015-2016 Freescale Semiconductor, Inc.
* Copyright 2017 NXP
* Copyright 2017,2021 NXP
*/
/*
@@ -262,7 +262,8 @@ int pfe_firmware_init(void)
uintptr_t pfe_img_addr = 0;
#endif
int ret = 0;
int fw_count;
int fw_count, max_fw_count;
const char *p;
ret = pfe_spi_flash_init();
if (ret)
@@ -293,6 +294,61 @@ int pfe_firmware_init(void)
}
#endif
p = env_get("load_util");
if (!p) {
max_fw_count = 2;
} else {
max_fw_count = simple_strtoul(p, NULL, 10);
if (max_fw_count)
max_fw_count = 3;
else
max_fw_count = 2;
}
for (fw_count = 0; fw_count < max_fw_count; fw_count++) {
switch (fw_count) {
case 0:
pfe_firmware_name = "class_slowpath";
break;
case 1:
pfe_firmware_name = "tmu_slowpath";
break;
case 2:
pfe_firmware_name = "util_slowpath";
break;
}
if (pfe_get_fw(&raw_image_addr, &raw_image_size,
pfe_firmware_name)) {
printf("%s firmware couldn't be found in FIT image\n",
pfe_firmware_name);
break;
}
pfe_firmware = malloc(raw_image_size);
if (!pfe_firmware)
return -ENOMEM;
memcpy((void *)pfe_firmware, (void *)raw_image_addr,
raw_image_size);
switch (fw_count) {
case 0:
env_set_addr("class_elf_firmware", pfe_firmware);
env_set_addr("class_elf_size", (void *)raw_image_size);
break;
case 1:
env_set_addr("tmu_elf_firmware", pfe_firmware);
env_set_addr("tmu_elf_size", (void *)raw_image_size);
break;
case 2:
env_set_addr("util_elf_firmware", pfe_firmware);
env_set_addr("util_elf_size", (void *)raw_image_size);
break;
}
}
raw_image_addr = NULL;
pfe_firmware = NULL;
raw_image_size = 0;
for (fw_count = 0; fw_count < 2; fw_count++) {
if (fw_count == 0)
pfe_firmware_name = "class";

1134
drivers/net/sni_netsec.c Normal file
View File

File diff suppressed because it is too large Load Diff

8
drivers/net/sun8i_emac.c
View File

@@ -211,7 +211,9 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
* The EMAC clock is either 200 or 300 MHz, so we need a divider
* of 128 to get the MDIO frequency below the required 2.5 MHz.
*/
mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
if (!priv->use_internal_phy)
mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
MDIO_CMD_MII_CLK_CSR_SHIFT;
mii_cmd |= MDIO_CMD_MII_BUSY;
@@ -242,7 +244,9 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
* The EMAC clock is either 200 or 300 MHz, so we need a divider
* of 128 to get the MDIO frequency below the required 2.5 MHz.
*/
mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 << MDIO_CMD_MII_CLK_CSR_SHIFT;
if (!priv->use_internal_phy)
mii_cmd |= MDIO_CMD_MII_CLK_CSR_DIV_128 <<
MDIO_CMD_MII_CLK_CSR_SHIFT;
mii_cmd |= MDIO_CMD_MII_WRITE;
mii_cmd |= MDIO_CMD_MII_BUSY;

7
drivers/net/tsec.c
View File

@@ -828,6 +828,7 @@ int tsec_probe(struct udevice *dev)
const char *phy_mode;
ofnode parent, child;
fdt_addr_t reg;
u32 max_speed;
int ret;
data = (struct tsec_data *)dev_get_driver_data(dev);
@@ -893,8 +894,12 @@ int tsec_probe(struct udevice *dev)
}
priv->interface = pdata->phy_interface;
/* Check for speed limit, default is 1000Mbps */
max_speed = dev_read_u32_default(dev, "max-speed", 1000);
/* Initialize flags */
priv->flags = TSEC_GIGABIT;
if (max_speed == 1000)
priv->flags = TSEC_GIGABIT;
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;