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FSL PCI: Configure PCIe reference ratio

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Most FSL PCIe controllers expects 333 MHz PCI reference clock.
This clock is derived from the CCB but in many cases the ref.
clock is not 333 MHz and a divisor needs to be configured.

This adds PEX_CCB_DIV #define which can be defined for each
type of CPU/platform.

Signed-off-by: Joakim Tjernlund <joakim.tjernlund@infinera.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Joakim Tjernlund 2017-09-12 19:56:41 +02:00 committed by York Sun
parent b2486b40dc
commit 6ce83fb3d6
1 changed files with 6 additions and 0 deletions
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6
drivers/pci/fsl_pci_init.c
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@ -321,6 +321,12 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
pci_setup_indirect(hose, cfg_addr, cfg_data);
#ifdef PEX_CCB_DIV
/* Configure the PCIE controller core clock ratio */
pci_hose_write_config_dword(hose, dev, 0x440,
((gd->bus_clk / 1000000) *
(16 / PEX_CCB_DIV)) / 333);
#endif
block_rev = in_be32(&pci->block_rev1);
if (PEX_IP_BLK_REV_2_2 <= block_rev) {
pi = &pci->pit[2]; /* 0xDC0 */