ARM: dts: stm32: add SCMI version of STM32 boards (DK1/DK2/ED1/EV1)
Add a "secure" version of STM32 boards based on SCMI when RCC_TZCR.TZEN=1. Only boards provided by STMicroelectronics are concerned: -STM32MP157A-DK1 -STM32MP157C-DK2 -STM32MP157C-ED1 -STM32MP157C-EV1 The resources secured by RCC_TZCR.TZEN=1 are managed by OP-TEE and the associated SCMI services, reset and clock. These device trees are only supported with stm32mp15_defconfig, with OP-TEE, SCMI and without SPL support. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
parent
7f4de655c0
commit
6cccc8d396
@ -1171,13 +1171,17 @@ dtb-$(CONFIG_STM32MP13x) += \
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dtb-$(CONFIG_STM32MP15x) += \
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stm32mp157a-dk1.dtb \
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stm32mp157a-dk1-scmi.dtb \
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stm32mp157a-icore-stm32mp1-ctouch2.dtb \
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stm32mp157a-icore-stm32mp1-edimm2.2.dtb \
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stm32mp157a-microgea-stm32mp1-microdev2.0.dtb \
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stm32mp157a-microgea-stm32mp1-microdev2.0-of7.dtb \
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stm32mp157c-dk2.dtb \
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stm32mp157c-dk2-scmi.dtb \
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stm32mp157c-ed1.dtb \
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stm32mp157c-ed1-scmi.dtb \
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stm32mp157c-ev1.dtb \
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stm32mp157c-ev1-scmi.dtb \
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stm32mp157c-odyssey.dtb \
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stm32mp15xx-dhcom-drc02.dtb \
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stm32mp15xx-dhcom-pdk2.dtb \
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167
arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
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167
arch/arm/dts/stm32mp15-scmi-u-boot.dtsi
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@ -0,0 +1,167 @@
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// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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*/
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/ {
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aliases {
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gpio0 = &gpioa;
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gpio1 = &gpiob;
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gpio2 = &gpioc;
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gpio3 = &gpiod;
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gpio4 = &gpioe;
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gpio5 = &gpiof;
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gpio6 = &gpiog;
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gpio7 = &gpioh;
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gpio8 = &gpioi;
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gpio9 = &gpioj;
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gpio10 = &gpiok;
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gpio25 = &gpioz;
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pinctrl0 = &pinctrl;
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pinctrl1 = &pinctrl_z;
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};
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binman: binman {
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multiple-images;
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};
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soc {
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u-boot,dm-pre-reloc;
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ddr: ddr@5a003000 {
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u-boot,dm-pre-reloc;
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compatible = "st,stm32mp1-ddr";
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reg = <0x5a003000 0x550
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0x5a004000 0x234>;
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status = "okay";
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};
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};
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/* need PSCI for sysreset during board_f */
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psci {
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u-boot,dm-pre-proper;
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};
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};
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&bsec {
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u-boot,dm-pre-reloc;
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};
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&gpioa {
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u-boot,dm-pre-reloc;
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};
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&gpiob {
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u-boot,dm-pre-reloc;
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};
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&gpioc {
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u-boot,dm-pre-reloc;
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};
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&gpiod {
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u-boot,dm-pre-reloc;
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};
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&gpioe {
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u-boot,dm-pre-reloc;
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};
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&gpiof {
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u-boot,dm-pre-reloc;
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};
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&gpiog {
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u-boot,dm-pre-reloc;
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};
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&gpioh {
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u-boot,dm-pre-reloc;
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};
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&gpioi {
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u-boot,dm-pre-reloc;
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};
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&gpioj {
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u-boot,dm-pre-reloc;
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};
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&gpiok {
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u-boot,dm-pre-reloc;
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};
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&gpioz {
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u-boot,dm-pre-reloc;
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};
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&optee {
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u-boot,dm-pre-proper;
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};
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&iwdg2 {
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u-boot,dm-pre-reloc;
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};
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/* pre-reloc probe = reserve video frame buffer in video_reserve() */
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<dc {
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u-boot,dm-pre-proper;
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};
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/* temp = waiting kernel update */
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&m4_rproc {
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resets = <&scmi_reset RST_SCMI_MCU>,
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<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
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reset-names = "mcu_rst", "hold_boot";
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&pinctrl_z {
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u-boot,dm-pre-reloc;
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};
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&rcc {
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u-boot,dm-pre-reloc;
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};
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&scmi {
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u-boot,dm-pre-proper;
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};
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&usart1 {
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resets = <&rcc USART1_R>;
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};
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&usart2 {
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resets = <&rcc USART2_R>;
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};
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&usart3 {
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resets = <&rcc USART3_R>;
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};
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&uart4 {
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resets = <&rcc UART4_R>;
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};
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&uart5 {
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resets = <&rcc UART5_R>;
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};
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&usart6 {
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resets = <&rcc USART6_R>;
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};
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&uart7 {
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resets = <&rcc UART7_R>;
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};
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&uart8{
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resets = <&rcc UART8_R>;
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};
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57
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
Normal file
57
arch/arm/dts/stm32mp157a-dk1-scmi-u-boot.dtsi
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@ -0,0 +1,57 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2022
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-scmi-u-boot.dtsi"
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#include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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usb0 = &usbotg_hs;
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};
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config {
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "u-boot-env";
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st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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led {
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red {
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label = "error";
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gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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default-state = "off";
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status = "okay";
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};
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};
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};
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&adc {
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status = "okay";
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&uart4_pins_a {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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/* pull-up on rx to avoid floating level */
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bias-pull-up;
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};
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};
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&usbotg_hs {
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u-boot,force-b-session-valid;
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};
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6
arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
Normal file
6
arch/arm/dts/stm32mp157c-dk2-scmi-u-boot.dtsi
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@ -0,0 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2022
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*/
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#include "stm32mp157a-dk1-scmi-u-boot.dtsi"
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47
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
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47
arch/arm/dts/stm32mp157c-ed1-scmi-u-boot.dtsi
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@ -0,0 +1,47 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2022
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*/
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#include <dt-bindings/clock/stm32mp1-clksrc.h>
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#include "stm32mp15-scmi-u-boot.dtsi"
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#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi"
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/ {
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aliases {
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i2c3 = &i2c4;
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};
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config {
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u-boot,boot-led = "heartbeat";
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u-boot,error-led = "error";
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u-boot,mmc-env-partition = "u-boot-env";
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st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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};
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led {
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red {
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label = "error";
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gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
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default-state = "off";
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status = "okay";
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};
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};
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};
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&uart4 {
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u-boot,dm-pre-reloc;
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};
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&uart4_pins_a {
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u-boot,dm-pre-reloc;
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pins1 {
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u-boot,dm-pre-reloc;
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};
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pins2 {
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u-boot,dm-pre-reloc;
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/* pull-up on rx to avoid floating level */
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bias-pull-up;
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};
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};
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17
arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
Normal file
17
arch/arm/dts/stm32mp157c-ev1-scmi-u-boot.dtsi
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@ -0,0 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause
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/*
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* Copyright : STMicroelectronics 2022
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*/
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#include "stm32mp157c-ed1-scmi-u-boot.dtsi"
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/ {
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aliases {
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gpio26 = &stmfx_pinctrl;
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i2c1 = &i2c2;
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i2c4 = &i2c5;
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pinctrl2 = &stmfx_pinctrl;
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spi0 = &qspi;
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usb0 = &usbotg_hs;
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};
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};
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@ -77,6 +77,16 @@ Currently the following boards are supported:
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+ stm32mp157c-ev1.dts
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+ stm32mp15xx-dhcor-avenger96.dts
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The SCMI variant of each board is supported by a specific "scmi" device tree:
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+ stm32mp157a-dk1-scmi.dts
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+ stm32mp157c-dk2-scmi.dts
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+ stm32mp157c-ed1-scmi.dts
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+ stm32mp157c-ev1-scmi.dts
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SCMI variant is used only with stm32mp15_defconfig, when the resources are
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secured with RCC_TZCR.TZEN=1 in OP-TEE. The access to these reset and clock
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resources are provided by OP-TEE and the associated SCMI services.
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STM32MP13x
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``````````
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@ -136,6 +146,9 @@ TF-A_ (BL2) initialize the DDR and loads the next stage binaries from a FIP file
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the secure monitor to access to secure resources.
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+ HW_CONFIG: The hardware configuration file = the U-Boot device tree
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The scmi variant of each device tree is only support with OP-TEE as secure
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monitor, with stm32mp15_defconfig.
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The **Basic** boot chain with SPL (for STM32MP15x)
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``````````````````````````````````````````````````
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@ -248,6 +261,12 @@ Build Procedure
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a) trusted boot with FIP on STM32MP15x ev1::
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# export KBUILD_OUTPUT=stm32mp15
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# make stm32mp15_defconfig
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# make DEVICE_TREE=stm32mp157c-ev1-scmi all
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or without SCMI support
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# export KBUILD_OUTPUT=stm32mp15
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# make stm32mp15_defconfig
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# make DEVICE_TREE=stm32mp157c-ev1 all
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