leandrof/u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

Browse Source 
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.

Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Tom Rini 2022-10-28 20:27:13 -04:00
parent 5155207ae1
commit 6cc04547cb
237 changed files with 861 additions and 862 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
README
View File

@ -298,7 +298,7 @@ The following options need to be configured:
Enables a workaround for erratum A004510. If set,
then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional)
@ -314,7 +314,7 @@ The following options need to be configured:
See Freescale App Note 4493 for more information about
this erratum.
CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600
according to the A004510 workaround.
@ -330,7 +330,7 @@ The following options need to be configured:
Freescale DDR driver in use. This type of DDR controller is
found in mpc83xx, mpc85xx as well as some ARM core SoCs.
CONFIG_SYS_FSL_DDR_ADDR
CFG_SYS_FSL_DDR_ADDR
Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV
@ -339,7 +339,7 @@ The following options need to be configured:
CONFIG_SYS_FSL_LBC_CLK_DIV
Defines divider of platform clock(clock input to eLBC controller).
CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
CFG_SYS_FSL_DDR_SDRAM_BASE_PHY
Physical address from the view of DDR controllers. It is the
same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But
it could be different for ARM SoCs.

4
arch/arm/cpu/armv7/ls102xa/clock.c
View File

@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */

10
arch/arm/cpu/armv7/ls102xa/cpu.c
View File

@ -228,7 +228,7 @@ void enable_caches(void)
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr);
}
@ -237,7 +237,7 @@ uint get_svr(void)
int print_cpuinfo(void)
{
char buf1[32], buf2[32];
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr);
@ -316,7 +316,7 @@ int arch_cpu_init(void)
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
@ -355,7 +355,7 @@ int arch_cpu_init(void)
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr);
}
@ -363,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr)
/* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);

4
arch/arm/cpu/armv7/ls102xa/fdt.c
View File

@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
int off;
int val;
const char *sysclk_path;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
else {
ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif

8
arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
View File

@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
@ -103,14 +103,14 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR +
CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT);

20
arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
View File

@ -31,7 +31,7 @@ static void __secure ls1_save_ddr_head(void)
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
static void __secure ls1_deepsleep_irq_cfg(void)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
@ -120,8 +120,8 @@ static void __secure ls1_start_fsm(void)
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
static void __secure ls1_deep_sleep(u32 entry_point)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point)
#else
static void __secure ls1_sleep(void)
{
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;

16
arch/arm/cpu/armv7/ls102xa/psci.S
View File

@ -129,8 +129,8 @@ psci_cpu_on:
mov r1, r4
@ Get DCFG base address
movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
@ -141,8 +141,8 @@ psci_cpu_on:
@ Reset target CPU
@ Get SCFG base address
movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
@ -216,8 +216,8 @@ psci_affinity_info:
mov r1, r4
@ Get RCPM base address
movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@ -236,8 +236,8 @@ out_affinity_info:
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2

8
arch/arm/cpu/armv7/ls102xa/soc.c
View File

@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
unsigned int get_soc_major_rev(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major;
svr = in_be32(&gur->svr);
@ -113,7 +113,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@ -129,7 +129,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
@ -161,7 +161,7 @@ void erratum_a010315(void)
int arch_soc_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;

48
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
View File

@ -96,11 +96,11 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
@ -159,7 +159,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@ -168,7 +168,7 @@ static struct mm_region early_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@ -204,7 +204,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@ -213,12 +213,12 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
{ CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
{ CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -333,7 +333,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
{ CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@ -342,7 +342,7 @@ static struct mm_region final_map[] = {
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
{ CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
void cpu_name(char *name)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
svr = gur_in32(&gur->svr);
@ -430,7 +430,7 @@ void cpu_name(char *name)
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
* The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@ -443,7 +443,7 @@ static inline void early_mmu_setup(void)
/* global data is already setup, no allocation yet */
if (el == 3)
gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void)
#ifdef CONFIG_ARCH_LS2080A
unsigned int i;
u32 svr, ver;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
@ -775,7 +775,7 @@ enum boot_src get_boot_src(void)
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#endif
if (current_el() == 2) {
@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
u32 initiator_type(u32 cluster, int init_id)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = 0;
@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
u32 cpu_pos_mask(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0;
u32 cluster, type, mask = 0;
@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
u32 cpu_mask(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
@ -930,7 +930,7 @@ int cpu_numcores(void)
int fsl_qoriq_core_to_cluster(unsigned int core)
{
struct ccsr_gur __iomem *gur =
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core)
u32 fsl_qoriq_core_to_type(unsigned int core)
{
struct ccsr_gur __iomem *gur =
(void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
(void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type;
@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core)
#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
@ -988,7 +988,7 @@ uint get_svr(void)
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@ -1179,9 +1179,9 @@ int arch_early_init_r(void)
int timer_init(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
#endif
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
@ -1230,7 +1230,7 @@ int timer_init(void)
}
#if !CONFIG_IS_ENABLED(SYSRESET)
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
{

10
arch/arm/cpu/armv8/fsl-layerscape/fdt.c
View File

@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob)
{
int offset, err;
u64 reg[8];
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int val;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int align_64k = 0;
val = gur_in32(&gur->svr);
@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
static void fdt_fixup_msi(void *blob)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int rev;
rev = gur_in32(&gur->svr);
@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
fdt_fixup_kaslr(blob);
#endif
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif

14
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
View File

@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]);
int i;
@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
int get_serdes_protocol(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock)
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
int setup_serdes_volt(u32 svdd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes *serdes1_base;
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes *serdes2_base;
@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd)
if (svdd_cur == svdd_tar)
return 0;
serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_base = (void *)serdes1_base + 0x10000;
#endif
@ -406,14 +406,14 @@ void fsl_serdes_init(void)
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_SERDES_ADDR,
CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_SERDES_ADDR,
CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);

4
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
View File

@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
@ -29,7 +29,7 @@ void get_sys_info(struct sys_info *sys_info)
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */

20
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
View File

@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = 0;
int i;
@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
int setup_serdes_volt(u32 svdd)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes __iomem *serdes1_base =
(void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
(void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes __iomem *serdes2_base =
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
struct ccsr_serdes __iomem *serdes3_base =
(void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
(void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif
u32 cfg_tmp;
@ -585,7 +585,7 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
CFG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@ -593,7 +593,7 @@ void fsl_serdes_init(void)
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@ -601,7 +601,7 @@ void fsl_serdes_init(void)
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
serdes_init(NXP_SRDS_3,
CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@ -611,7 +611,7 @@ void fsl_serdes_init(void)
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16];
int cfgr = 0;
u32 cfg;

10
arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
View File

@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
(void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
(void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
(void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
};
struct ccsr_clk_ctrl __iomem *clk_ctrl =
(void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
(void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[16] = {
[0] = 0, /* CC1 PPL / 1 */
@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info)
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = get_board_sys_clk();
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;

2
arch/arm/cpu/armv8/fsl-layerscape/icid.c
View File

@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size)
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],

4
arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
View File

@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
ENTRY(fsl_clear_ocram)
/* Clear OCRAM */
ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
ldr x0, =CFG_SYS_FSL_OCRAM_BASE
ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
mov x2, #0
clear_loop:
str x2, [x0]

2
arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
View File

@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
bool soc_has_mac1(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr);

10
arch/arm/cpu/armv8/fsl-layerscape/mp.c
View File

@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch)
#ifdef CONFIG_FSL_LSCH3
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 mpidr = 0;
mpidr = ((cluster << 8) | core);
@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
int fsl_layerscape_wake_seconday_cores(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 svr, ver, cluster, type;
int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;

4
arch/arm/cpu/armv8/fsl-layerscape/ppa.c
View File

@ -253,7 +253,7 @@ int ppa_init(void)
#endif
#ifdef CONFIG_FSL_LSCH3
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
@ -261,7 +261,7 @@ int ppa_init(void)
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];

36
arch/arm/cpu/armv8/fsl-layerscape/soc.c
View File

@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
bool soc_has_dp_ddr(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */
@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
bool soc_has_aiop(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
@ -249,13 +249,13 @@ static void erratum_a008336(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
@ -271,8 +271,8 @@ static void erratum_a008514(void)
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
#endif
#endif
@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void)
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void)
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
@ -473,7 +473,7 @@ static void erratum_a008850_early(void)
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
if (current_el() < 3)
@ -493,7 +493,7 @@ void erratum_a008850_post(void)
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* Skip if running at lower exception level */
@ -526,21 +526,21 @@ void erratum_a010315(void)
static void erratum_a010539(void)
{
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 porsr1;
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
}
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd)
#ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en)
{
struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1);
@ -629,7 +629,7 @@ int setup_chip_volt(void)
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecccr2;
out_be32(&scfg->pfeasbcr,
@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void)
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
enum boot_src src;
#endif

28
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -24,7 +24,7 @@
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
@ -32,9 +32,9 @@
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@ -95,7 +95,7 @@
#define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@ -126,9 +126,9 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* LX2160A/LX2162A Soc Support */
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@ -139,13 +139,13 @@
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@ -161,7 +161,7 @@
/* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
@ -180,9 +180,9 @@
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@ -200,9 +200,9 @@
/* DCFG - GUR */
#elif defined(CONFIG_FSL_LSCH2)
#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544

6
arch/arm/include/asm/arch-fsl-layerscape/cpu.h
View File

@ -10,7 +10,7 @@
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
@ -19,7 +19,7 @@
#endif
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
@ -73,7 +73,7 @@
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000

26
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
View File

@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SDHC_ICID(streamid) \
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
CONFIG_SYS_FSL_ESDHC_ADDR)
CFG_SYS_FSL_ESDHC_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob);
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_ADDR, \
CONFIG_SYS_FSL_QMAN_ADDR, false)
CFG_SYS_FSL_QMAN_ADDR, \
CFG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_ADDR, \
CONFIG_SYS_FSL_BMAN_ADDR, false)
CFG_SYS_FSL_BMAN_ADDR, \
CFG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob);
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
CFG_SYS_FSL_SEC_ADDR, \
CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[];
extern int fman_icid_tbl_sz;
@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz;
SET_ICID_ENTRY( \
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, \
CFG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
extern int icid_tbl_sz;

48
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
View File

@ -14,18 +14,18 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
@ -65,7 +65,7 @@
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
@ -165,24 +165,24 @@ struct sys_info {
unsigned long freq_qman;
};
#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
#define CONFIG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
#define CFG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull
#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull
#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x720000ull
#define FSL_SEC_JR2_OFFSET 0x730000ull
#define FSL_SEC_JR3_OFFSET 0x740000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)

60
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
View File

@ -9,19 +9,19 @@
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#else
#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#endif
#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#ifndef CONFIG_NXP_LSCH3_2
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#else
@ -29,8 +29,8 @@
#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
#endif
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
@ -38,20 +38,20 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
0x18A0)
#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
@ -108,16 +108,16 @@
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x07020000ull
#define FSL_SEC_JR2_OFFSET 0x07030000ull
#define FSL_SEC_JR3_OFFSET 0x07040000ull
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)

2
arch/arm/include/asm/arch-imx8/imx-regs.h
View File

@ -47,6 +47,6 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
#endif /* __ASM_ARCH_IMX8_REGS_H__ */

12
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -87,12 +87,12 @@
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
#define CONFIG_SYS_FSL_SEC_OFFSET (0)
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_OFFSET (0)
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
CFG_SYS_FSL_JR0_OFFSET)
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>

24
arch/arm/include/asm/arch-ls102xa/config.h
View File

@ -17,25 +17,25 @@
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000

18
arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
View File

@ -29,30 +29,30 @@
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, 0)
CFG_SYS_FSL_SEC_OFFSET, 0)
struct liodn_id_table {
const char *compat;

12
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -238,12 +238,12 @@
#endif
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_OFFSET 0
#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
CFG_SYS_FSL_JR0_OFFSET)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)

12
arch/arm/include/asm/arch-mx7/imx-regs.h
View File

@ -215,12 +215,12 @@
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_OFFSET 0
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
CFG_SYS_FSL_JR0_OFFSET)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>

12
arch/arm/include/asm/arch-mx7ulp/imx-regs.h
View File

@ -228,12 +228,12 @@
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
#define CONFIG_SYS_FSL_SEC_OFFSET 0
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_SEC_OFFSET 0
#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_OFFSET 0x1000
#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
CFG_SYS_FSL_JR0_OFFSET)
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))

2
arch/arm/mach-imx/cmd_dek.c
View File

@ -40,7 +40,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
hab_caam_clock_enable(1);
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();

2
arch/arm/mach-imx/cmd_mfgprot.c
View File

@ -41,7 +41,7 @@ static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const arg
/* Enable HAB clock */
hab_caam_clock_enable(1);
u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)

4
arch/arm/mach-imx/mx7/clock.c
View File

@ -30,9 +30,9 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

4
arch/arm/mach-imx/mx7ulp/clock.c
View File

@ -18,9 +18,9 @@ DECLARE_GLOBAL_DATA_PTR;
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#endif
#endif

12
arch/arm/mach-imx/speed.c
View File

@ -21,21 +21,21 @@ int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);

2
arch/powerpc/cpu/mpc85xx/cmd_errata.c
View File

@ -84,7 +84,7 @@ static void check_erratum_a4849(uint32_t svr)
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {

12
arch/powerpc/cpu/mpc85xx/cpu.c
View File

@ -98,7 +98,7 @@ int checkcpu (void)
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
(void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
(void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
@ -540,16 +540,16 @@ static void dump_spd_ddr_reg(void)
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)

14
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -160,7 +160,7 @@ void disable_cpc_sram(void)
{
int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@ -217,7 +217,7 @@ void enable_cpc(void)
char cpc_subarg[16];
bool have_hwconfig = false;
int cpc_args = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@ -271,7 +271,7 @@ void enable_cpc(void)
static void invalidate_cpc(void)
{
int i;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
@ -300,7 +300,7 @@ static void invalidate_cpc(void)
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
(void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
(void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
@ -476,7 +476,7 @@ int enable_cluster_l2(void)
do {
int j, cluster_valid = 0;
l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@ -518,7 +518,7 @@ int l2cache_init(void)
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
#endif
puts ("L2: ");
@ -664,7 +664,7 @@ int cpu_init_r(void)
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)

10
arch/powerpc/cpu/mpc85xx/fdt.c
View File

@ -164,7 +164,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
static inline void ft_fixup_l3cache(void *blob, int off)
{
u32 line_size, num_ways, size, num_sets;
cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@ -299,7 +299,7 @@ static inline void ft_fixup_l2cache(void *blob)
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
#else
struct ccsr_cluster_l2 *l2cache =
(struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
(struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
#endif
u32 size, line_size, num_ways, num_sets;
@ -466,11 +466,11 @@ static void ft_fixup_dpaa_clks(void *blob)
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif
#endif
@ -611,7 +611,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd)
else {
ccsr_sec_t __iomem *sec;
sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif

24
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
View File

@ -21,10 +21,10 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
#ifdef CFG_SYS_FSL_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
#ifdef CFG_SYS_FSL_SRDS_4
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
@ -104,13 +104,13 @@ int is_serdes_configured(enum srds_prtcl device)
ret |= serdes2_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
#ifdef CFG_SYS_FSL_SRDS_3
if (!serdes3_prtcl_map[NONE])
fsl_serdes_init();
ret |= serdes3_prtcl_map[device];
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
#ifdef CFG_SYS_FSL_SRDS_4
if (!serdes4_prtcl_map[NONE])
fsl_serdes_init();
@ -139,13 +139,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
#ifdef CFG_SYS_FSL_SRDS_3
case FSL_SRDS_3:
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
break;
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
#ifdef CFG_SYS_FSL_SRDS_4
case FSL_SRDS_4:
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@ -351,28 +351,28 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
CFG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_3
#ifdef CFG_SYS_FSL_SRDS_3
serdes_init(FSL_SRDS_3,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_4
#ifdef CFG_SYS_FSL_SRDS_4
serdes_init(FSL_SRDS_4,
CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);

10
arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
View File

@ -109,7 +109,7 @@ int serdes_get_bank_by_lane(int lane)
int serdes_lane_enabled(int lane)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int word = lanes[lane].lpd / 32;
@ -257,7 +257,7 @@ void serdes_reset_rx(enum srds_prtcl device)
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
return;
regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device);
@ -466,7 +466,7 @@ static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg)
static void wait_for_rstdone(unsigned int bank)
{
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned long long end_tick;
u32 rstctl;
@ -527,7 +527,7 @@ void fsl_serdes_init(void)
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return;
srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@ -601,7 +601,7 @@ void fsl_serdes_init(void)
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
break;
default:
srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);

14
arch/powerpc/cpu/mpc85xx/liodn.c
View File

@ -76,7 +76,7 @@ static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size)
static void setup_sec_liodn_base(void)
{
ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
@ -101,12 +101,12 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
switch(dev) {
case FSL_HW_PORTAL_FMAN1:
fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
#endif
default:
@ -130,7 +130,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
static void setup_pme_liodn_base(void)
{
#ifdef CONFIG_SYS_DPAA_PME
ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_PME].id[1];
@ -141,7 +141,7 @@ static void setup_pme_liodn_base(void)
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
static void setup_raide_liodn_base(void)
{
struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@ -155,7 +155,7 @@ static void setup_raide_liodn_base(void)
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
@ -168,7 +168,7 @@ static void set_rman_liodn(struct liodn_id_table *tbl, int size)
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);

4
arch/powerpc/cpu/mpc85xx/mp.c
View File

@ -265,8 +265,8 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize)
struct law_entry e;
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);

4
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -26,14 +26,14 @@ void get_sys_info(sys_info_t *sys_info)
{
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;

2
arch/powerpc/cpu/mpc85xx/start.S
View File

@ -966,7 +966,7 @@ delete_ccsr_l2_tlb:
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else

2
arch/powerpc/cpu/mpc8xxx/law.c
View File

@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)

8
arch/powerpc/cpu/mpc8xxx/srio.c
View File

@ -79,9 +79,9 @@ static int srio_erratum_a004034(u8 port)
int idx, first, last;
u32 i;
unsigned long long end_tick;
struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
>> (12 - port * 4)) & 0x3;
init_lane = (in_be32((void *)&srio_regs->lp_serial
@ -291,7 +291,7 @@ void srio_init(void)
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@ -343,7 +343,7 @@ void srio_boot_master(int port)
void srio_boot_master_release_slave(int port)
{
struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");

81
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -17,10 +17,10 @@
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
@ -59,30 +59,30 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020)
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_NUM_FMAN 2
@ -91,11 +91,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_NUM_FMAN 2
@ -104,7 +104,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
@ -118,7 +118,7 @@
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
@ -131,17 +131,17 @@
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRDS_3
#define CONFIG_SYS_FSL_SRDS_4
#define CFG_SYS_FSL_SRDS_3
#define CFG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
@ -154,21 +154,21 @@
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@ -184,8 +184,7 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
#define CONFIG_SYS_FSL_NUM_CC_PLL 2
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@ -202,15 +201,15 @@
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
@ -224,7 +223,7 @@
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif

56
arch/powerpc/include/asm/fsl_liodn.h
View File

@ -33,7 +33,7 @@ struct srio_liodn_id_table {
{ .id = { id_a }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ (port - 1) * 0x200 \
+ CONFIG_SYS_FSL_SRIO_ADDR, \
+ CFG_SYS_FSL_SRIO_ADDR, \
}
struct liodn_id_table {
@ -130,29 +130,29 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
offsetof(struct ccsr_qman, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
CONFIG_SYS_FSL_QMAN_OFFSET)
CFG_SYS_FSL_QMAN_OFFSET, \
CFG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,bman", liodn, \
offsetof(struct ccsr_bman, liodnr) + \
CONFIG_SYS_FSL_BMAN_OFFSET, \
CONFIG_SYS_FSL_BMAN_OFFSET)
CFG_SYS_FSL_BMAN_OFFSET, \
CFG_SYS_FSL_BMAN_OFFSET)
#define SET_PME_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
CONFIG_SYS_FSL_CORENET_PME_OFFSET)
CFG_SYS_FSL_CORENET_PME_OFFSET, \
CFG_SYS_FSL_CORENET_PME_OFFSET)
#define SET_PMAN_LIODN(num, liodn) \
SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
offsetof(struct ccsr_pman, ppa1) + \
CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
CFG_SYS_FSL_FM##fmNum##_OFFSET + \
offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
#ifdef CONFIG_SYS_FMAN_V3
@ -160,31 +160,31 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
#else
/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
#endif
/*
* handle both old and new versioned SEC properties:
@ -193,44 +193,44 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, \
CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
CFG_SYS_FSL_SEC_OFFSET, \
CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
CONFIG_SYS_FSL_SEC_OFFSET, 0)
CFG_SYS_FSL_SEC_OFFSET, 0)
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
liodnA, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
offsetof(struct ccsr_rman, mmitdr) + \
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];

2
arch/powerpc/include/asm/immap_83xx.h
View File

@ -862,7 +862,7 @@ struct ccsr_gpio {
};
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
#define CONFIG_SYS_FSL_DDR_ADDR \
#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CFG_SYS_MPC83xx_DMA_ADDR \

210
arch/powerpc/include/asm/immap_85xx.h
View File

@ -963,7 +963,7 @@ struct rio_lp_serial {
u32 prtoccsr; /* Port Response Time-out CCSR */
u8 res1[20];
u32 pgccsr; /* Port General CSR */
struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Logical error reporting registers */
@ -993,7 +993,7 @@ struct rio_phys_err_port {
/* Physical error reporting registers */
struct rio_phys_err {
struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Implementation Space: General Port-Common */
@ -1033,7 +1033,7 @@ struct rio_impl_port_spec {
/* Implementation Space: register */
struct rio_implement {
struct rio_impl_common com;
struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Revision Control Register */
@ -1061,13 +1061,13 @@ struct rio_atmu_riw {
/* ATMU window registers */
struct rio_atmu_win {
struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
u8 res0[64];
struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
};
struct rio_atmu {
struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
#ifdef CONFIG_SYS_FSL_RMU
@ -1154,7 +1154,7 @@ struct ccsr_rio {
struct rio_atmu atmu;
#ifdef CONFIG_SYS_FSL_RMU
u8 res5[8192];
struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
u8 res6[512];
struct rio_dbell dbell;
u8 res7[100];
@ -1162,7 +1162,7 @@ struct ccsr_rio {
#endif
#ifdef CONFIG_SYS_FSL_SRIO_LIODN
u8 res5[8192];
struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
#endif
};
#endif
@ -2431,17 +2431,17 @@ struct ccsr_pman {
#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#ifdef CONFIG_SYS_PMAN
#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
/* In SFPv3, OSPR register is now at offset 0x200.
* * So directly mapping sfp register map to this address */
@ -2450,13 +2450,13 @@ struct ccsr_pman {
#else
#define CONFIG_SYS_SFP_OFFSET 0xE8000
#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
#define CFG_SYS_FSL_CPC_OFFSET 0x10000
#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000
#define CFG_SYS_FSL_PAMU_OFFSET 0x20000
#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
@ -2468,7 +2468,7 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
!defined(CONFIG_ARCH_B4420)
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
@ -2487,33 +2487,33 @@ struct ccsr_pman {
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
#define CFG_SYS_FSL_SEC_OFFSET 0x300000
#define CFG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
#define CFG_SYS_FSL_FM1_OFFSET 0x400000
#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
#define CFG_SYS_FSL_FM2_OFFSET 0x500000
#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
@ -2551,57 +2551,57 @@ struct ccsr_pman {
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
#define CFG_SYS_FSL_SEC_OFFSET 0x80000
#define CFG_SYS_FSL_JR0_OFFSET 0x81000
#else
#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
#define CFG_SYS_FSL_SEC_OFFSET 0x30000
#define CFG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
#define CFG_SYS_FSL_FM1_OFFSET 0x100000
#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
#define CONFIG_SYS_FSL_SCFG_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
#define CONFIG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
#define CONFIG_SYS_FSL_BMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
#define CFG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
#define CFG_SYS_FSL_SCFG_ADDR \
(CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
#define CFG_SYS_FSL_QMAN_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
#define CFG_SYS_FSL_BMAN_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
#define CFG_SYS_FSL_CORENET_PME_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
#define CFG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CFG_SYS_FSL_CORENET_CCM_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
#define CFG_SYS_FSL_CORENET_CLK_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CFG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
#define CONFIG_SYS_FSL_DDR_ADDR \
#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
#define CONFIG_SYS_FSL_DDR2_ADDR \
#define CFG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
#define CONFIG_SYS_FSL_DDR3_ADDR \
#define CFG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
@ -2631,14 +2631,14 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
#define CFG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CFG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
#define CFG_SYS_MPC85xx_USB2_ADDR \
@ -2647,20 +2647,20 @@ struct ccsr_pman {
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
#define CONFIG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CONFIG_SYS_FSL_FM2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
#define CONFIG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
#define CFG_SYS_FSL_SEC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
#define CFG_SYS_FSL_JR0_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define CFG_SYS_FSL_FM1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
#define CFG_SYS_FSL_FM2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
#define CFG_SYS_FSL_SRIO_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PAMU_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
(CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
@ -2739,8 +2739,8 @@ struct ccsr_cluster_l2 {
u32 l2erraddr; /* 0xe54 L2 cache error address */
u32 l2errctl; /* 0xe58 L2 cache error control */
};
#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#define CFG_SYS_FSL_CLUSTER_1_L2 \
(CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000

2
board/advantech/imx8mp_rsb3720a1/spl.c
View File

@ -129,7 +129,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(1);

4
board/advantech/imx8qm_rom7720_a1/spl.c
View File

@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@ -108,7 +108,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc1 USDHC2
* mmc2 USDHC3
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);

2
board/bosch/acc/acc.c
View File

@ -562,7 +562,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC2
* mmc1 USDHC4
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
SETUP_IOMUX_PADS(usdhc2_pads);

2
board/compulab/cl-som-imx7/cl-som-imx7.c
View File

@ -90,7 +90,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc2 USDHC3 (eMMC)
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
cl_som_imx7_usdhc1_pads_set();

2
board/compulab/cm_fx6/cm_fx6.c
View File

@ -622,7 +622,7 @@ int board_init(void)
int i;
cm_fx6_set_usdhc_iomux();
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++)
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++)
enable_usdhc_clk(1, i);
}
#endif

4
board/congatec/cgtqmx8/cgtqmx8.c
View File

@ -114,7 +114,7 @@ int board_early_init_f(void)
#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
{USDHC2_BASE_ADDR, 0, 4},
{USDHC3_BASE_ADDR, 0, 4},
@ -173,7 +173,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc1 (external SD card) USDHC2
* mmc2 (onboard µSD) USDHC3
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
/* onboard eMMC */

8
board/freescale/common/arm_sleep.c
View File

@ -35,7 +35,7 @@ void __weak board_sleep_prepare(void)
bool is_warm_boot(void)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@ -57,7 +57,7 @@ static void dp_ddr_restore(void)
{
u64 *src, *dst;
int i;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
/* get the address of ddr date from SPARECR3 */
src = (u64 *)in_le32(&scfg->sparecr[2]);
@ -71,7 +71,7 @@ static void dp_ddr_restore(void)
void ls1_psci_resume_fixup(void)
{
u32 tmp;
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef QIXIS_BASE
void *qixis_base = (void *)QIXIS_BASE;
@ -114,7 +114,7 @@ int fsl_dp_resume(void)
{
u32 start_addr;
void (*kernel_resume)(void);
struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
if (!is_warm_boot())
return 0;

2
board/freescale/common/fsl_chain_of_trust.c
View File

@ -30,7 +30,7 @@
#if defined(CONFIG_MPC85xx)
#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR
#else
#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR
#define CONFIG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR
#endif
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE

4
board/freescale/common/fsl_validate.c
View File

@ -114,7 +114,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
*/
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
if (memcmp((u8 *)(uintptr_t)csf_hdr_addr,
@ -130,7 +130,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr)
#if defined(CONFIG_ESBC_HDR_LS)
static int get_ie_info_addr(uintptr_t *ie_addr)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* For LS-CH3, the address of IE Table is
* stated in Scratch13 and scratch14 of DCFG.
* Bootrom validates this table while validating uboot.

2
board/freescale/common/ls102xa_stream_id.c
View File

@ -9,7 +9,7 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num)
{
void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
u32 icid;

2
board/freescale/common/ns_access.c
View File

@ -180,7 +180,7 @@ static struct csu_ns_dev ns_dev[] = {
void set_devices_ns_access(unsigned long index, u16 val)
{
u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR;
u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR;
u32 *reg;
uint32_t tmp;

2
board/freescale/common/vid.c
View File

@ -539,7 +539,7 @@ int adjust_vdd(ulong vdd_override)
{
int re_enable = disable_interrupts();
#if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3)
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#else
ccsr_gur_t __iomem *gur =
(void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);

2
board/freescale/imx8mq_evk/spl.c
View File

@ -121,7 +121,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);

2
board/freescale/ls1012aqds/eth.c
View File

@ -133,7 +133,7 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
static const char *mdio_name;
struct pfe_mdio_info mac_mdio_info;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u8 data8;
struct pfe_eth_dev *priv = dev_get_priv(dev);

2
board/freescale/ls1012aqds/ls1012aqds.c
View File

@ -213,7 +213,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob)
struct pfe_prop_val prop_val;
void *l_blob = blob;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;

2
board/freescale/ls1012ardb/eth.c
View File

@ -80,7 +80,7 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;

6
board/freescale/ls1021aiot/ls1021aiot.c
View File

@ -38,7 +38,7 @@ int checkboard(void)
puts("Board: LS1021AIOT\n");
#ifndef CONFIG_QSPI_BOOT
struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cpldrev;
cpldrev = in_be32(&dcfg->gpporcr1);
@ -51,7 +51,7 @@ int checkboard(void)
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@ -111,7 +111,7 @@ int dram_init(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */

8
board/freescale/ls1021aqds/ls1021aqds.c
View File

@ -160,7 +160,7 @@ int dram_init(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */
@ -185,7 +185,7 @@ int board_early_init_f(void)
void board_init_f(ulong dummy)
{
#ifdef CONFIG_NAND_BOOT
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 porsr1, pinctl;
/*
@ -234,7 +234,7 @@ void board_init_f(ulong dummy)
void config_etseccm_source(int etsec_gtx_125_mux)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
switch (etsec_gtx_125_mux) {
case GE0_CLK125:
@ -308,7 +308,7 @@ int config_board_mux(int ctrl_type)
int config_serdes_mux(void)
{
struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
u32 cfg;
cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;

4
board/freescale/ls1021atsn/ls1021atsn.c
View File

@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR;
static void ddrmc_init(void)
{
#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@ -130,7 +130,7 @@ int board_eth_init(struct bd_info *bis)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/*

6
board/freescale/ls1021atwr/ls1021atwr.c
View File

@ -143,7 +143,7 @@ int checkboard(void)
void ddrmc_init(void)
{
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
@ -288,7 +288,7 @@ static void convert_serdes_mux(int type, int need_reset)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT;
@ -383,7 +383,7 @@ conflict:
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET
/* clear BD & FR bits for BE BD's and frame data */

4
board/freescale/ls1043aqds/eth.c
View File

@ -261,7 +261,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
void fdt_fixup_board_enet(void *fdt)
{
int i;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &
@ -302,7 +302,7 @@ int board_eth_init(struct bd_info *bis)
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct memac_mdio_info tgec_mdio_info;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) &

10
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -430,9 +430,9 @@ void board_retimer_init(void)
int board_early_init_f(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@ -475,7 +475,7 @@ int board_early_init_f(void)
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@ -529,7 +529,7 @@ int board_init(void)
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
board_retimer_init();
#ifdef CONFIG_SYS_FSL_SERDES
#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@ -596,6 +596,6 @@ u16 flash_read16(void *addr)
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif

2
board/freescale/ls1043ardb/eth.c
View File

@ -21,7 +21,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;

4
board/freescale/ls1043ardb/ls1043ardb.c
View File

@ -188,7 +188,7 @@ int checkboard(void)
int board_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
erratum_a010315();
@ -230,7 +230,7 @@ int board_init(void)
int config_board_mux(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
if (hwconfig("qe-hdlc")) {

4
board/freescale/ls1046afrwy/eth.c
View File

@ -20,7 +20,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info dtsec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@ -70,7 +70,7 @@ int fdt_update_ethernet_dt(void *blob)
int i, prop;
int offset, nodeoff;
const char *path;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;

2
board/freescale/ls1046afrwy/ls1046afrwy.c
View File

@ -146,7 +146,7 @@ int board_setup_core_volt(u32 vdd)
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/*
* USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT

2
board/freescale/ls1046aqds/eth.c
View File

@ -268,7 +268,7 @@ int board_eth_init(struct bd_info *bis)
{
int i, idx, lane, slot, interface;
struct memac_mdio_info dtsec_mdio_info;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
u8 brdcfg12;

10
board/freescale/ls1046aqds/ls1046aqds.c
View File

@ -300,9 +300,9 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int board_early_init_f(void)
{
u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
#endif
#ifdef CONFIG_LPUART
@ -347,7 +347,7 @@ int board_early_init_f(void)
bool is_warm_boot(void)
{
#define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
return 1;
@ -395,7 +395,7 @@ int board_init(void)
{
select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
#ifdef CONFIG_SYS_FSL_SERDES
#ifdef CFG_SYS_FSL_SERDES
config_serdes_mux();
#endif
@ -479,6 +479,6 @@ u16 flash_read16(void *addr)
#if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif

4
board/freescale/ls1046ardb/eth.c
View File

@ -22,7 +22,7 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_info tgec_mdio_info;
struct mii_dev *dev;
u32 srds_s1;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
@ -84,7 +84,7 @@ int fdt_update_ethernet_dt(void *blob)
int i, prop;
int offset, nodeoff;
const char *path;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;

4
board/freescale/ls1046ardb/ls1046ardb.c
View File

@ -80,7 +80,7 @@ int checkboard(void)
int board_init(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_NXP_ESBC
/*
@ -146,7 +146,7 @@ int power_init_board(void)
void config_board_mux(void)
{
#ifdef CONFIG_HAS_FSL_XHCI_USB
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 usb_pwrfault;
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */

14
board/freescale/ls1088a/eth_ls1088aqds.c
View File

@ -471,7 +471,7 @@ static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval)
*/
static void initialize_dpmac_to_slot(void)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@ -524,7 +524,7 @@ static void initialize_dpmac_to_slot(void)
void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
{
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@ -576,7 +576,7 @@ void ls1088a_handle_phy_interface_sgmii(int dpmac_id)
void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
{
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@ -615,7 +615,7 @@ void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
void ls1088a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) &
@ -639,7 +639,7 @@ void ls1088a_handle_phy_interface_xsgmii(int i)
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
u32 serdes1_prtcl, cfg;
struct mii_dev *bus;
@ -682,7 +682,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@ -807,7 +807,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char expected_dts[100];
char srds_s1_str[2];
u32 srds_s1, cfg;

6
board/freescale/ls1088a/eth_ls1088ardb.c
View File

@ -25,7 +25,7 @@ int board_eth_init(struct bd_info *bis)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct memac_mdio_controller *reg;
u32 srds_s1, cfg;
@ -35,14 +35,14 @@ int board_eth_init(struct bd_info *bis)
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;

2
board/freescale/ls1088a/ls1088a.c
View File

@ -1031,7 +1031,7 @@ int is_flash_available(void)
#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
void *env_sf_get_env_addr(void)
{
return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);
}
#endif
#endif

16
board/freescale/ls2080aqds/eth.c
View File

@ -502,7 +502,7 @@ static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval)
*/
static void initialize_dpmac_to_slot(void)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@ -656,7 +656,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id)
{
int lane, slot;
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@ -799,7 +799,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
{
int lane = 0, slot;
struct mii_dev *bus;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@ -864,7 +864,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
void ls2080a_handle_phy_interface_xsgmii(int i)
{
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@ -898,7 +898,7 @@ int board_eth_init(struct bd_info *bis)
{
#ifndef CONFIG_DM_ETH
#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK)
>> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
@ -920,7 +920,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio0_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO1;
CFG_SYS_FSL_WRIOP1_MDIO1;
memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */
@ -930,7 +930,7 @@ int board_eth_init(struct bd_info *bis)
sizeof(struct memac_mdio_info));
memac_mdio1_info->regs =
(struct memac_mdio_controller *)
CONFIG_SYS_FSL_WRIOP1_MDIO2;
CFG_SYS_FSL_WRIOP1_MDIO2;
memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */
@ -1053,7 +1053,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;

6
board/freescale/ls2080ardb/eth_ls2080rdb.c
View File

@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis)
int i, interface;
struct memac_mdio_info mdio_info;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
struct memac_mdio_controller *reg;
@ -37,14 +37,14 @@ int board_eth_init(struct bd_info *bis)
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;

4
board/freescale/ls2080ardb/ls2080ardb.c
View File

@ -242,7 +242,7 @@ int config_board_mux(int ctrl_type)
ulong *cs4340_get_fw_addr(void)
{
#ifdef CONFIG_TFABOOT
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
#endif
ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR;
@ -318,7 +318,7 @@ int misc_init_r(void)
char *env_hwconfig;
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
u32 val;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);

12
board/freescale/lx2160a/eth_lx2160aqds.c
View File

@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis)
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2, srds_s3;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@ -476,14 +476,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@ -670,9 +670,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@ -929,7 +929,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2];
u32 srds_s1, srds_s2, srds_s3;

6
board/freescale/lx2160a/eth_lx2160ardb.c
View File

@ -48,21 +48,21 @@ int board_eth_init(struct bd_info *bis)
struct memac_mdio_controller *reg;
int i, interface;
struct mii_dev *dev;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1;
srds_s1 = in_le32(&gur->rcwsr[28]) &
FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */
fm_memac_mdio_init(bis, &mdio_info);
reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = reg;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;

12
board/freescale/lx2160a/eth_lx2162aqds.c
View File

@ -480,7 +480,7 @@ int board_eth_init(struct bd_info *bis)
size_t len;
struct mii_dev *bus;
const struct phy_config *phy_config;
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 srds_s1, srds_s2;
srds_s1 = in_le32(&gur->rcwsr[28]) &
@ -493,14 +493,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d", srds_s1, srds_s2);
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/
fm_memac_mdio_init(bis, &mdio_info);
regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2;
mdio_info.regs = regs;
mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@ -679,9 +679,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1)
reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
reg = CFG_SYS_FSL_WRIOP1_MDIO1;
else
reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
if (offset < 0) {
@ -946,7 +946,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;

4
board/freescale/lx2160a/lx2160a.c
View File

@ -180,7 +180,7 @@ void esdhc_dspi_status_fixup(void *blob)
const char dspi1_path[] = "/soc/spi@2110000";
const char dspi2_path[] = "/soc/spi@2120000";
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;
@ -385,7 +385,7 @@ static void esdhc_adapter_card_ident(void)
int config_board_mux(void)
{
u8 reg11, reg5, reg13;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 sdhc1_base_pmux;
u32 sdhc2_base_pmux;
u32 iic5_pmux;

2
board/freescale/mx53loco/mx53loco.c
View File

@ -124,7 +124,7 @@ static int power_init(void)
return ret;
}
if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
if (!i2c_probe(CFG_SYS_FSL_PMIC_I2C_ADDR)) {
ret = pmic_init(I2C_0);
if (ret)
return ret;

2
board/freescale/p2041rdb/p2041rdb.c
View File

@ -167,7 +167,7 @@ unsigned long get_board_sys_clk(void)
int misc_init_r(void)
{
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 actual[NUM_SRDS_BANKS];
unsigned int i;
u8 sw;

2
board/freescale/t208xqds/eth_t208xqds.c
View File

@ -192,7 +192,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_TARGET_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
(void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &

2
board/google/imx8mq_phanbell/spl.c
View File

@ -97,7 +97,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);

2
board/keymile/kmcent2/kmcent2.c
View File

@ -220,7 +220,7 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
int misc_init_r(void)
{
serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;

4
board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c
View File

@ -50,8 +50,8 @@ int dram_init(void)
int board_early_init_f(void)
{
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */

2
board/kontron/pitx_imx8m/spl.c
View File

@ -132,7 +132,7 @@ int board_mmc_init(struct bd_info *bis)
* mmc0 USDHC1
* mmc1 USDHC2
*/
for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
switch (i) {
case 0:
init_clk_usdhc(0);

Some files were not shown because too many files have changed in this diff Show More