ppc: Remove T1023RBD boards and T1024RDB_SECURE_BOOT

These boards have not been converted to CONFIG_DM_PCI by the deadline
and is also missing conversion to CONFIG_DM.  Remove them.  As this is
the only ARCH_T1023 platform left, remove that support as well.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
2021-05-14 21:34:22 -04:00
parent 98898601b4
commit 6c3d99335c
14 changed files with 6 additions and 421 deletions

View File

@@ -113,16 +113,6 @@ config TARGET_QEMU_PPCE500
select ARCH_QEMU_E500
select PHYS_64BIT
config TARGET_T1023RDB
bool "Support T1023RDB"
select ARCH_T1023
select BOARD_LATE_INIT if CHAIN_OF_TRUST
select SUPPORT_SPL
select PHYS_64BIT
select FSL_DDR_INTERACTIVE
imply CMD_EEPROM
imply PANIC_HANG
config TARGET_T1024RDB
bool "Support T1024RDB"
select ARCH_T1024
@@ -692,27 +682,6 @@ config ARCH_P5040
config ARCH_QEMU_E500
bool
config ARCH_T1023
bool
select E500MC
select FSL_LAW
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_FSL_HAS_SEC
select SYS_FSL_QORIQ_CHASSIS2
select SYS_FSL_SEC_BE
select SYS_FSL_SEC_COMPAT_5
select FSL_IFC
imply CMD_EEPROM
imply CMD_NAND
imply CMD_REGINFO
config ARCH_T1024
bool
select E500MC
@@ -916,7 +885,6 @@ config MAX_CPUS
ARCH_P1024 || \
ARCH_P1025 || \
ARCH_P2020 || \
ARCH_T1023 || \
ARCH_T1024
default 1
help
@@ -952,7 +920,6 @@ config SYS_CCSRBAR_DEFAULT
ARCH_P3041 || \
ARCH_P4080 || \
ARCH_P5040 || \
ARCH_T1023 || \
ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042 || \
@@ -1144,8 +1111,7 @@ config SYS_FSL_NUM_LAWS
ARCH_T2080 || \
ARCH_T4160 || \
ARCH_T4240
default 16 if ARCH_T1023 || \
ARCH_T1024 || \
default 16 if ARCH_T1024 || \
ARCH_T1040 || \
ARCH_T1042
default 12 if ARCH_BSC9131 || \
@@ -1224,7 +1190,6 @@ config SYS_FSL_IFC_CLK_DIV
default 2 if ARCH_B4420 || \
ARCH_B4860 || \
ARCH_T1024 || \
ARCH_T1023 || \
ARCH_T1040 || \
ARCH_T1042 || \
ARCH_T4160 || \

View File

@@ -47,7 +47,6 @@ obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
obj-$(CONFIG_ARCH_T1040) += t1040_ids.o
obj-$(CONFIG_ARCH_T1042) += t1040_ids.o
obj-$(CONFIG_ARCH_T1023) += t1024_ids.o
obj-$(CONFIG_ARCH_T1024) += t1024_ids.o
obj-$(CONFIG_ARCH_T2080) += t2080_ids.o
@@ -83,7 +82,6 @@ obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
obj-$(CONFIG_ARCH_T1040) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1042) += t1040_serdes.o
obj-$(CONFIG_ARCH_T1023) += t1024_serdes.o
obj-$(CONFIG_ARCH_T1024) += t1024_serdes.o
obj-$(CONFIG_ARCH_T2080) += t2080_serdes.o

View File

@@ -201,7 +201,7 @@ void get_sys_info(sys_info_t *sys_info)
defined(CONFIG_ARCH_T2080)
#define FM1_CLK_SEL 0xe0000000
#define FM1_CLK_SHIFT 29
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#elif defined(CONFIG_ARCH_T1024)
#define FM1_CLK_SEL 0x00000007
#define FM1_CLK_SHIFT 0
#else
@@ -211,7 +211,7 @@ void get_sys_info(sys_info_t *sys_info)
#define FM1_CLK_SHIFT 26
#endif
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#if defined(CONFIG_ARCH_T1024)
rcw_tmp = in_be32(&gur->rcwsr[15]) - 4;
#else
rcw_tmp = in_be32(&gur->rcwsr[7]);

View File

@@ -313,7 +313,7 @@
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#elif defined(CONFIG_ARCH_T1024)
#define CONFIG_E5500
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1

View File

@@ -28,7 +28,6 @@
defined(CONFIG_TARGET_T1042RDB) || \
defined(CONFIG_TARGET_T1042D4RDB) || \
defined(CONFIG_TARGET_T1042RDB_PI) || \
defined(CONFIG_ARCH_T1023) || \
defined(CONFIG_ARCH_T1024)
#ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CPC_REINIT_F

View File

@@ -1792,7 +1792,7 @@ typedef struct ccsr_gur {
#define PXCKEN_MASK 0x80000000
#define PXCK_MASK 0x00FF0000
#define PXCK_BITS_START 16
#elif defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#elif defined(CONFIG_ARCH_T1024)
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL 0xff800000
#define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT 23
#define FSL_CORENET_RCWSR6_BOOT_LOC 0x0f800000
@@ -2500,7 +2500,7 @@ typedef struct ccsr_gur {
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
#define MAX_SERDES 4
#if defined(CONFIG_ARCH_T1024) || defined(CONFIG_ARCH_T1023)
#if defined(CONFIG_ARCH_T1024)
#define SRDS_MAX_LANES 4
#else
#define SRDS_MAX_LANES 8