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bsh: imx8mn-smm-s2/pro: Add iMX8MN BSH SMM S2 boards

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Introduce BSH SystemMaster (SMM) S2 board family, which consists of:
iMX8MN SMM S2 and iMX8MN SMM S2 PRO boards.

Add support for iMX8MN BSH SMM S2 board:

- 256 MiB DDR3 RAM
- 512MiB Nand
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet

Add support for iMX8MN BSH SMM S2 PRO board:

- 512 MiB DDR3 RAM
- 8 GiB eMMC
- USBOTG1 peripheral - fastboot.
- 100Mbit Ethernet

Signed-off-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
This commit is contained in:
Ariel D'Alessandro 2022-04-12 10:31:38 -03:00 committed by Stefano Babic
parent a2f5c9366a
commit 6c317fedc7
24 changed files with 3308 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/dts/Makefile
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@ -913,6 +913,8 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-venice-gw7902.dtb \
imx8mm-verdin.dtb \
phycore-imx8mm.dtb \
imx8mn-bsh-smm-s2.dtb \
imx8mn-bsh-smm-s2pro.dtb \
imx8mn-ddr4-evk.dtb \
imx8mq-cm.dtb \
imx8mn-evk.dtb \

423
arch/arm/dts/imx8mn-bsh-smm-s2-common.dtsi Normal file
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@ -0,0 +1,423 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn.dtsi"
/ {
chosen {
stdout-path = &uart4;
};
fec_supply: fec_supply_en {
compatible = "regulator-fixed";
regulator-name = "tja1101_en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
vin-supply = <&buck4_reg>;
enable-active-high;
};
usdhc2_pwrseq: usdhc2_pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_pwrseq>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
};
&A53_0 {
cpu-supply = <&buck2_reg>;
};
&A53_1 {
cpu-supply = <&buck2_reg>;
};
&A53_2 {
cpu-supply = <&buck2_reg>;
};
&A53_3 {
cpu-supply = <&buck2_reg>;
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_espi2>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
phy-supply = <&fec_supply>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
phy-reset-duration = <20>;
fsl,magic-packet;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
bd71847: pmic@4b {
compatible = "rohm,bd71847";
reg = <0x4b>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
rohm,reset-snvs-powered;
#clock-cells = <0>;
clocks = <&osc_32k 0>;
clock-output-names = "clk-32k-out";
regulators {
buck1_reg: BUCK1 {
/* PMIC_BUCK1 - VDD_SOC */
regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck2_reg: BUCK2 {
/* PMIC_BUCK2 - VDD_ARM */
regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <1250>;
};
buck3_reg: BUCK3 {
/* PMIC_BUCK5 - VDD_DRAM_VPU_GPU */
regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
regulator-always-on;
};
buck4_reg: BUCK4 {
/* PMIC_BUCK6 - VDD_3V3 */
regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
buck5_reg: BUCK5 {
/* PMIC_BUCK7 - VDD_1V8 */
regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
regulator-always-on;
};
buck6_reg: BUCK6 {
/* PMIC_BUCK8 - NVCC_DRAM */
regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1_reg: LDO1 {
/* PMIC_LDO1 - NVCC_SNVS_1V8 */
regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <1900000>;
regulator-boot-on;
regulator-always-on;
};
ldo2_reg: LDO2 {
/* PMIC_LDO2 - VDD_SNVS_0V8 */
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
};
ldo3_reg: LDO3 {
/* PMIC_LDO3 - VDDA_1V8 */
regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4_reg: LDO4 {
/* PMIC_LDO4 - VDD_MIPI_0V9 */
regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
ldo6_reg: LDO6 {
/* PMIC_LDO6 - VDD_MIPI_1V2 */
regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
};
&i2c4 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
assigned-clocks = <&clk IMX8MN_CLK_UART3>;
assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
uart-has-rtscts;
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_bluetooth>;
shutdown-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
max-speed = <3000000>;
};
};
/* Console */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
&usbotg1 {
dr_mode = "peripheral";
disable-over-current;
status = "okay";
};
&usdhc2 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
mmc-pwrseq = <&usdhc2_pwrseq>;
bus-width = <4>;
non-removable;
status = "okay";
brcmf: bcrmf@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wlan>;
interrupt-parent = <&gpio1>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "host-wake";
};
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_espi2: espi2grp {
fsl,pins = <
MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x082
MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x082
MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x082
MX8MN_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x040
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400000c2
MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400000c2
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400000c2
MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400000c2
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400000c2
MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400000c2
>;
};
pinctrl_pmic: pmicirq {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x040
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x040
MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x040
>;
};
pinctrl_usdhc2_pwrseq: usdhc2pwrseqgrp {
fsl,pins = <
MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x040 /* WL_REG_ON */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x090
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d0
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d0
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d0
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d0
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x094
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d4
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d4
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d4
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d4
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x096
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x0d6
MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x0d6
MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x0d6
MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x0d6
MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x0d6
>;
};
pinctrl_wlan: wlangrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x0d6 /* GPIO_0 - WIFI_GPIO_0 */
MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x0d6 /* GPIO_1 - WIFI_GPIO_1 */
MX8MN_IOMUXC_GPIO1_IO04_GPIO1_IO4 0x0d6 /* BT_GPIO_5 - WIFI_GPIO_5 */
MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x0d6 /* I2S_CLK - WIFI_GPIO_6 */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x040
MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x040
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x040
MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x040
MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x040
MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x040
>;
};
pinctrl_bluetooth: bluetoothgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x044 /* BT_REG_ON */
MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x046 /* BT_DEV_WAKE */
MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x090 /* BT_HOST_WAKE */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x046
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x002
MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x002
MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x090
MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x090
MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x090
MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x016
MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x016
MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x016
MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x016
MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x090
MX8MN_IOMUXC_ENET_TXC_ENET1_TX_ER 0x016
MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x150 /* RMII_INT - ENET_INT */
MX8MN_IOMUXC_SD2_WP_GPIO2_IO20 0x150 /* RMII_EN - ENET_EN */
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x016 /* RMII_WAKE - GPIO_ENET_WAKE */
MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x016 /* RMII_RESET - GPIO_ENET_RST */
>;
};
};

225
arch/arm/dts/imx8mn-bsh-smm-s2-u-boot-common.dtsi Normal file
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@ -0,0 +1,225 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/ {
binman: binman {
multiple-images;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
u-boot,dm-spl;
};
};
&{/soc@0} {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
u-boot,dm-spl;
};
&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
u-boot,dm-spl;
};
&aips1 {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&aips3 {
u-boot,dm-spl;
};
&aips4 {
u-boot,dm-spl;
};
&clk {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
/delete-property/ assigned-clocks;
/delete-property/ assigned-clock-parents;
/delete-property/ assigned-clock-rates;
};
&gpio1 {
u-boot,dm-spl;
};
&gpio2 {
u-boot,dm-spl;
};
&gpio4 {
u-boot,dm-spl;
};
&i2c1 {
u-boot,dm-spl;
};
&iomuxc {
u-boot,dm-spl;
};
&osc_24m {
u-boot,dm-pre-reloc;
u-boot,dm-spl;
};
&pinctrl_i2c1 {
u-boot,dm-spl;
};
&pinctrl_pmic {
u-boot,dm-spl;
};
&pinctrl_uart4 {
u-boot,dm-spl;
};
&pinctrl_wdog {
u-boot,dm-spl;
};
&uart4 {
u-boot,dm-spl;
};
&wdog1 {
u-boot,dm-spl;
};
&binman {
u-boot-spl-ddr {
align = <4>;
align-size = <4>;
filename = "u-boot-spl-ddr.bin";
pad-byte = <0xff>;
u-boot-spl {
align-end = <4>;
filename = "u-boot-spl.bin";
};
1d-imem {
filename = "ddr3_imem_1d.bin";
size = <0x8000>;
type = "blob-ext";
};
1d_dmem {
filename = "ddr3_dmem_1d.bin";
size = <0x4000>;
type = "blob-ext";
};
};
spl {
filename = "spl.bin";
mkimage {
args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x912000";
blob {
filename = "u-boot-spl-ddr.bin";
};
};
};
itb {
filename = "u-boot.itb";
fit {
description = "Configuration to load ATF before U-Boot";
fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
fit,fdt-list = "of-list";
#address-cells = <1>;
images {
uboot {
arch = "arm64";
compression = "none";
description = "U-Boot (64-bit)";
load = <CONFIG_SYS_TEXT_BASE>;
type = "standalone";
uboot_blob {
filename = "u-boot-nodtb.bin";
type = "blob-ext";
};
};
atf {
arch = "arm64";
compression = "none";
description = "ARM Trusted Firmware";
entry = <0x960000>;
load = <0x960000>;
type = "firmware";
atf_blob {
filename = "bl31.bin";
type = "atf-bl31";
};
};
binman_fip: fip {
arch = "arm64";
compression = "none";
description = "Trusted Firmware FIP";
load = <0x40310000>;
type = "firmware";
};
@fdt-SEQ {
compression = "none";
description = "NAME";
type = "flat_dt";
uboot_fdt_blob {
filename = "u-boot.dtb";
type = "blob-ext";
};
};
};
configurations {
default = "@config-DEFAULT-SEQ";
binman_configuration: @config-SEQ {
description = "NAME";
fdt = "fdt-SEQ";
firmware = "uboot";
loadables = "atf";
};
};
};
};
imx-boot {
filename = "flash.bin";
pad-byte = <0x00>;
spl {
filename = "spl.bin";
offset = <0x0>;
type = "blob-ext";
};
binman_uboot: uboot {
filename = "u-boot.itb";
offset = <0x58000>;
type = "blob-ext";
};
};
};

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arch/arm/dts/imx8mn-bsh-smm-s2-u-boot.dtsi Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_gpmi_nand {
u-boot,dm-spl;
};
&gpmi {
u-boot,dm-spl;
};

48
arch/arm/dts/imx8mn-bsh-smm-s2.dts Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
/ {
model = "BSH SMM S2";
compatible = "bsh,imx8mn-bsh-smm-s2", "fsl,imx8mn";
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x10000000>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
nand-on-flash-bbt;
status = "okay";
};
&iomuxc {
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX8MN_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096
MX8MN_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096
MX8MN_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096
MX8MN_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096
MX8MN_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096
MX8MN_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096
MX8MN_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096
MX8MN_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096
MX8MN_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096
MX8MN_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096
MX8MN_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096
MX8MN_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096
MX8MN_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056
MX8MN_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096
MX8MN_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096
>;
};
};

15
arch/arm/dts/imx8mn-bsh-smm-s2pro-u-boot.dtsi Normal file
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@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
#include "imx8mn-bsh-smm-s2-u-boot-common.dtsi"
&pinctrl_usdhc1 {
u-boot,dm-spl;
};
&usdhc1 {
u-boot,dm-spl;
};

80
arch/arm/dts/imx8mn-bsh-smm-s2pro.dts Normal file
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@ -0,0 +1,80 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
* Copyright 2021 BSH Hausgeraete GmbH
*/
/dts-v1/;
#include "imx8mn-bsh-smm-s2-common.dtsi"
/ {
model = "BSH SMM S2 PRO";
compatible = "bsh,imx8mn-bsh-smm-s2pro", "fsl,imx8mn";
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0x0 0x20000000>;
};
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&iomuxc {
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000090
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d0
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d0
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d0
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d0
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d0
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d0
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d0
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d0
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d0
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x090
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000094
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d4
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d4
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d4
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d4
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d4
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d4
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d4
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d4
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d4
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x094
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x40000096
MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x0d6
MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0d6
MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0d6
MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0d6
MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x0d6
MX8MN_IOMUXC_SD1_DATA4_USDHC1_DATA4 0x0d6
MX8MN_IOMUXC_SD1_DATA5_USDHC1_DATA5 0x0d6
MX8MN_IOMUXC_SD1_DATA6_USDHC1_DATA6 0x0d6
MX8MN_IOMUXC_SD1_DATA7_USDHC1_DATA7 0x0d6
MX8MN_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x096
>;
};
};

15
arch/arm/mach-imx/imx8m/Kconfig
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@ -91,6 +91,20 @@ config TARGET_KONTRON_MX8MM
select SUPPORT_SPL
select IMX8M_LPDDR4
config TARGET_IMX8MN_BSH_SMM_S2
bool "imx8mn-bsh-smm-s2"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_BSH_SMM_S2PRO
bool "imx8mn-bsh-smm-s2pro"
select BINMAN
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR3L
config TARGET_IMX8MN_EVK
bool "imx8mn LPDDR4 EVK board"
select BINMAN
@ -221,6 +235,7 @@ endchoice
source "board/advantech/imx8mp_rsb3720a1/Kconfig"
source "board/beacon/imx8mm/Kconfig"
source "board/beacon/imx8mn/Kconfig"
source "board/bsh/imx8mn_smm_s2/Kconfig"
source "board/compulab/imx8mm-cl-iot-gate/Kconfig"
source "board/engicam/imx8mm/Kconfig"
source "board/freescale/imx8mq_evk/Kconfig"

49
board/bsh/imx8mn_smm_s2/Kconfig Normal file
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@ -0,0 +1,49 @@
config BSH_SMM_S2_DDR3L_256
bool "BSH SMM S2 DDR3L 256 MiB RAM support"
config BSH_SMM_S2_DDR3L_512
bool "BSH SMM S2 DDR3L 512 MiB RAM support"
if TARGET_IMX8MN_BSH_SMM_S2
config SYS_BOARD
default "imx8mn_smm_s2"
config SYS_VENDOR
default "bsh"
config IMX_CONFIG
default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg"
config SYS_CONFIG_NAME
default "imx8mn_bsh_smm_s2"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BSH_SMM_S2_DDR3L_256
source "board/freescale/common/Kconfig"
endif
if TARGET_IMX8MN_BSH_SMM_S2PRO
config SYS_BOARD
default "imx8mn_smm_s2"
config SYS_VENDOR
default "bsh"
config IMX_CONFIG
default "board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg"
config SYS_CONFIG_NAME
default "imx8mn_bsh_smm_s2pro"
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select BSH_SMM_S2_DDR3L_512
source "board/freescale/common/Kconfig"
endif

8
board/bsh/imx8mn_smm_s2/MAINTAINERS Normal file
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@ -0,0 +1,8 @@
ARM i.MX8MN BSH SMM S2 BOARDS
M: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
M: Michael Trimarchi <michael@amarulasolutions.com>
S: Maintained
F: arch/arm/dts/imx8mn-bsh-smm-s2*
F: board/bsh/imx8mn_smm_s2/
F: configs/imx8mn_bsh_smm_s2*
F: include/configs/imx8mn_bsh_smm_s2*

13
board/bsh/imx8mn_smm_s2/Makefile Normal file
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@ -0,0 +1,13 @@
#
# Copyright 2021 Collabora Ltd.
#
# SPDX-License-Identifier: GPL-2.0+
#
obj-y += imx8mn_smm_s2.o
ifdef CONFIG_SPL_BUILD
obj-y += spl.o
obj-$(CONFIG_BSH_SMM_S2_DDR3L_256) += ddr3l_timing_256m.o
obj-$(CONFIG_BSH_SMM_S2_DDR3L_512) += ddr3l_timing_512m.o
endif

941
board/bsh/imx8mn_smm_s2/ddr3l_timing_256m.c Normal file
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@ -0,0 +1,941 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*
* Generated code from MX8M_DDR_tool
*
* Align with uboot version:
* imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
* For imx_v2019.04_5.4.x and above version:
* please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
{ 0x3d400064, 0x610040 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
{ 0x3d4000e0, 0x180000 },
{ 0x3d4000e4, 0x90000 },
{ 0x3d4000f0, 0x0 },
{ 0x3d4000f4, 0xee5 },
{ 0x3d400100, 0xc101b0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
{ 0x3d400110, 0x6020306 },
{ 0x3d400114, 0x4040302 },
{ 0x3d400120, 0x909 },
{ 0x3d400180, 0x40800020 },
{ 0x3d400184, 0xc350 },
{ 0x3d400190, 0x3868203 },
{ 0x3d400194, 0x20303 },
{ 0x3d4001b4, 0x603 },
{ 0x3d400198, 0x7000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001a0, 0x400018 },
{ 0x3d4001a4, 0x5003c },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001c4, 0x0 },
{ 0x3d400200, 0x1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0xf0f0707 },
{ 0x3d400240, 0x600060c },
{ 0x3d400244, 0x1323 },
{ 0x3d400400, 0x100 },
{ 0x3d400250, 0x7ab50b07 },
{ 0x3d400254, 0x22 },
{ 0x3d40025c, 0x7b00665e },
{ 0x3d400264, 0xb0000040 },
{ 0x3d40026c, 0x50000a0c },
{ 0x3d400300, 0x17 },
{ 0x3d40036c, 0x10000 },
{ 0x3d400404, 0x3051 },
{ 0x3d400408, 0x61d2 },
{ 0x3d400494, 0xe00 },
{ 0x3d400498, 0x7ff },
{ 0x3d40049c, 0xe00 },
{ 0x3d4004a0, 0x7ff },
{ 0x3d402064, 0x28001b },
{ 0x3d4020dc, 0x12200004 },
{ 0x3d4020e0, 0x0 },
{ 0x3d402100, 0x7090b07 },
{ 0x3d402104, 0x20209 },
{ 0x3d402108, 0x3030407 },
{ 0x3d40210c, 0x2006 },
{ 0x3d402110, 0x3020203 },
{ 0x3d402114, 0x3030202 },
{ 0x3d402120, 0x909 },
{ 0x3d402180, 0x40800020 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x20303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d402240, 0x6000604 },
{ 0x3d4020f4, 0xee5 },
{ 0x3d400028, 0x1 },
};
/* PHY Initialize Configuration */
struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x1005f, 0x3ff },
{ 0x1015f, 0x3ff },
{ 0x1105f, 0x3ff },
{ 0x1115f, 0x3ff },
{ 0x11005f, 0x3ff },
{ 0x11015f, 0x3ff },
{ 0x11105f, 0x3ff },
{ 0x11115f, 0x3ff },
{ 0x55, 0x3ff },
{ 0x1055, 0x3ff },
{ 0x2055, 0x3ff },
{ 0x3055, 0x3ff },
{ 0x4055, 0xff },
{ 0x5055, 0xff },
{ 0x6055, 0x3ff },
{ 0x7055, 0x3ff },
{ 0x8055, 0x3ff },
{ 0x9055, 0x3ff },
{ 0x200c5, 0xb },
{ 0x1200c5, 0x7 },
{ 0x2002e, 0x1 },
{ 0x12002e, 0x1 },
{ 0x20024, 0x0 },
{ 0x2003a, 0x0 },
{ 0x120024, 0x0 },
{ 0x2003a, 0x0 },
{ 0x20056, 0xa },
{ 0x120056, 0xa },
{ 0x1004d, 0x208 },
{ 0x1014d, 0x208 },
{ 0x1104d, 0x208 },
{ 0x1114d, 0x208 },
{ 0x11004d, 0x208 },
{ 0x11014d, 0x208 },
{ 0x11104d, 0x208 },
{ 0x11114d, 0x208 },
{ 0x10049, 0xe38 },
{ 0x10149, 0xe38 },
{ 0x11049, 0xe38 },
{ 0x11149, 0xe38 },
{ 0x110049, 0xe38 },
{ 0x110149, 0xe38 },
{ 0x111049, 0xe38 },
{ 0x111149, 0xe38 },
{ 0x43, 0x63 },
{ 0x1043, 0x63 },
{ 0x2043, 0x63 },
{ 0x3043, 0x63 },
{ 0x4043, 0x63 },
{ 0x5043, 0x63 },
{ 0x6043, 0x63 },
{ 0x7043, 0x63 },
{ 0x8043, 0x63 },
{ 0x9043, 0x63 },
{ 0x20018, 0x1 },
{ 0x20075, 0x0 },
{ 0x20050, 0x0 },
{ 0x20008, 0x190 },
{ 0x120008, 0xa7 },
{ 0x20088, 0x9 },
{ 0x200b2, 0x32c },
{ 0x10043, 0x581 },
{ 0x10143, 0x581 },
{ 0x11043, 0x581 },
{ 0x11143, 0x581 },
{ 0x1200b2, 0x32c },
{ 0x110043, 0x581 },
{ 0x110143, 0x581 },
{ 0x111043, 0x581 },
{ 0x111143, 0x581 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x20019, 0x5 },
{ 0x120019, 0x5 },
{ 0x200f0, 0x5555 },
{ 0x200f1, 0x5555 },
{ 0x200f2, 0x5555 },
{ 0x200f3, 0x5555 },
{ 0x200f4, 0x5555 },
{ 0x200f5, 0x5555 },
{ 0x200f6, 0x5555 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x1004a, 0x500 },
{ 0x1104a, 0x500 },
{ 0x2002c, 0x0 },
};
/* ddr phy trained csr */
struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x0200b2, 0x0},
{0x1200b2, 0x0},
{0x2200b2, 0x0},
{0x0200cb, 0x0},
{0x010043, 0x0},
{0x110043, 0x0},
{0x210043, 0x0},
{0x010143, 0x0},
{0x110143, 0x0},
{0x210143, 0x0},
{0x011043, 0x0},
{0x111043, 0x0},
{0x211043, 0x0},
{0x011143, 0x0},
{0x111143, 0x0},
{0x211143, 0x0},
{0x000080, 0x0},
{0x100080, 0x0},
{0x200080, 0x0},
{0x001080, 0x0},
{0x101080, 0x0},
{0x201080, 0x0},
{0x002080, 0x0},
{0x102080, 0x0},
{0x202080, 0x0},
{0x003080, 0x0},
{0x103080, 0x0},
{0x203080, 0x0},
{0x004080, 0x0},
{0x104080, 0x0},
{0x204080, 0x0},
{0x005080, 0x0},
{0x105080, 0x0},
{0x205080, 0x0},
{0x006080, 0x0},
{0x106080, 0x0},
{0x206080, 0x0},
{0x007080, 0x0},
{0x107080, 0x0},
{0x207080, 0x0},
{0x008080, 0x0},
{0x108080, 0x0},
{0x208080, 0x0},
{0x009080, 0x0},
{0x109080, 0x0},
{0x209080, 0x0},
{0x010080, 0x0},
{0x110080, 0x0},
{0x210080, 0x0},
{0x010180, 0x0},
{0x110180, 0x0},
{0x210180, 0x0},
{0x010081, 0x0},
{0x110081, 0x0},
{0x210081, 0x0},
{0x010181, 0x0},
{0x110181, 0x0},
{0x210181, 0x0},
{0x010082, 0x0},
{0x110082, 0x0},
{0x210082, 0x0},
{0x010182, 0x0},
{0x110182, 0x0},
{0x210182, 0x0},
{0x010083, 0x0},
{0x110083, 0x0},
{0x210083, 0x0},
{0x010183, 0x0},
{0x110183, 0x0},
{0x210183, 0x0},
{0x011080, 0x0},
{0x111080, 0x0},
{0x211080, 0x0},
{0x011180, 0x0},
{0x111180, 0x0},
{0x211180, 0x0},
{0x011081, 0x0},
{0x111081, 0x0},
{0x211081, 0x0},
{0x011181, 0x0},
{0x111181, 0x0},
{0x211181, 0x0},
{0x011082, 0x0},
{0x111082, 0x0},
{0x211082, 0x0},
{0x011182, 0x0},
{0x111182, 0x0},
{0x211182, 0x0},
{0x011083, 0x0},
{0x111083, 0x0},
{0x211083, 0x0},
{0x011183, 0x0},
{0x111183, 0x0},
{0x211183, 0x0},
{0x0100d0, 0x0},
{0x1100d0, 0x0},
{0x2100d0, 0x0},
{0x0101d0, 0x0},
{0x1101d0, 0x0},
{0x2101d0, 0x0},
{0x0100d1, 0x0},
{0x1100d1, 0x0},
{0x2100d1, 0x0},
{0x0101d1, 0x0},
{0x1101d1, 0x0},
{0x2101d1, 0x0},
{0x0100d2, 0x0},
{0x1100d2, 0x0},
{0x2100d2, 0x0},
{0x0101d2, 0x0},
{0x1101d2, 0x0},
{0x2101d2, 0x0},
{0x0100d3, 0x0},
{0x1100d3, 0x0},
{0x2100d3, 0x0},
{0x0101d3, 0x0},
{0x1101d3, 0x0},
{0x2101d3, 0x0},
{0x0110d0, 0x0},
{0x1110d0, 0x0},
{0x2110d0, 0x0},
{0x0111d0, 0x0},
{0x1111d0, 0x0},
{0x2111d0, 0x0},
{0x0110d1, 0x0},
{0x1110d1, 0x0},
{0x2110d1, 0x0},
{0x0111d1, 0x0},
{0x1111d1, 0x0},
{0x2111d1, 0x0},
{0x0110d2, 0x0},
{0x1110d2, 0x0},
{0x2110d2, 0x0},
{0x0111d2, 0x0},
{0x1111d2, 0x0},
{0x2111d2, 0x0},
{0x0110d3, 0x0},
{0x1110d3, 0x0},
{0x2110d3, 0x0},
{0x0111d3, 0x0},
{0x1111d3, 0x0},
{0x2111d3, 0x0},
{0x010068, 0x0},
{0x010168, 0x0},
{0x010268, 0x0},
{0x010368, 0x0},
{0x010468, 0x0},
{0x010568, 0x0},
{0x010668, 0x0},
{0x010768, 0x0},
{0x010868, 0x0},
{0x010069, 0x0},
{0x010169, 0x0},
{0x010269, 0x0},
{0x010369, 0x0},
{0x010469, 0x0},
{0x010569, 0x0},
{0x010669, 0x0},
{0x010769, 0x0},
{0x010869, 0x0},
{0x01006a, 0x0},
{0x01016a, 0x0},
{0x01026a, 0x0},
{0x01036a, 0x0},
{0x01046a, 0x0},
{0x01056a, 0x0},
{0x01066a, 0x0},
{0x01076a, 0x0},
{0x01086a, 0x0},
{0x01006b, 0x0},
{0x01016b, 0x0},
{0x01026b, 0x0},
{0x01036b, 0x0},
{0x01046b, 0x0},
{0x01056b, 0x0},
{0x01066b, 0x0},
{0x01076b, 0x0},
{0x01086b, 0x0},
{0x011068, 0x0},
{0x011168, 0x0},
{0x011268, 0x0},
{0x011368, 0x0},
{0x011468, 0x0},
{0x011568, 0x0},
{0x011668, 0x0},
{0x011768, 0x0},
{0x011868, 0x0},
{0x011069, 0x0},
{0x011169, 0x0},
{0x011269, 0x0},
{0x011369, 0x0},
{0x011469, 0x0},
{0x011569, 0x0},
{0x011669, 0x0},
{0x011769, 0x0},
{0x011869, 0x0},
{0x01106a, 0x0},
{0x01116a, 0x0},
{0x01126a, 0x0},
{0x01136a, 0x0},
{0x01146a, 0x0},
{0x01156a, 0x0},
{0x01166a, 0x0},
{0x01176a, 0x0},
{0x01186a, 0x0},
{0x01106b, 0x0},
{0x01116b, 0x0},
{0x01126b, 0x0},
{0x01136b, 0x0},
{0x01146b, 0x0},
{0x01156b, 0x0},
{0x01166b, 0x0},
{0x01176b, 0x0},
{0x01186b, 0x0},
{0x01008c, 0x0},
{0x11008c, 0x0},
{0x21008c, 0x0},
{0x01018c, 0x0},
{0x11018c, 0x0},
{0x21018c, 0x0},
{0x01008d, 0x0},
{0x11008d, 0x0},
{0x21008d, 0x0},
{0x01018d, 0x0},
{0x11018d, 0x0},
{0x21018d, 0x0},
{0x01008e, 0x0},
{0x11008e, 0x0},
{0x21008e, 0x0},
{0x01018e, 0x0},
{0x11018e, 0x0},
{0x21018e, 0x0},
{0x01008f, 0x0},
{0x11008f, 0x0},
{0x21008f, 0x0},
{0x01018f, 0x0},
{0x11018f, 0x0},
{0x21018f, 0x0},
{0x01108c, 0x0},
{0x11108c, 0x0},
{0x21108c, 0x0},
{0x01118c, 0x0},
{0x11118c, 0x0},
{0x21118c, 0x0},
{0x01108d, 0x0},
{0x11108d, 0x0},
{0x21108d, 0x0},
{0x01118d, 0x0},
{0x11118d, 0x0},
{0x21118d, 0x0},
{0x01108e, 0x0},
{0x11108e, 0x0},
{0x21108e, 0x0},
{0x01118e, 0x0},
{0x11118e, 0x0},
{0x21118e, 0x0},
{0x01108f, 0x0},
{0x11108f, 0x0},
{0x21108f, 0x0},
{0x01118f, 0x0},
{0x11118f, 0x0},
{0x21118f, 0x0},
{0x0100c0, 0x0},
{0x1100c0, 0x0},
{0x2100c0, 0x0},
{0x0101c0, 0x0},
{0x1101c0, 0x0},
{0x2101c0, 0x0},
{0x0102c0, 0x0},
{0x1102c0, 0x0},
{0x2102c0, 0x0},
{0x0103c0, 0x0},
{0x1103c0, 0x0},
{0x2103c0, 0x0},
{0x0104c0, 0x0},
{0x1104c0, 0x0},
{0x2104c0, 0x0},
{0x0105c0, 0x0},
{0x1105c0, 0x0},
{0x2105c0, 0x0},
{0x0106c0, 0x0},
{0x1106c0, 0x0},
{0x2106c0, 0x0},
{0x0107c0, 0x0},
{0x1107c0, 0x0},
{0x2107c0, 0x0},
{0x0108c0, 0x0},
{0x1108c0, 0x0},
{0x2108c0, 0x0},
{0x0100c1, 0x0},
{0x1100c1, 0x0},
{0x2100c1, 0x0},
{0x0101c1, 0x0},
{0x1101c1, 0x0},
{0x2101c1, 0x0},
{0x0102c1, 0x0},
{0x1102c1, 0x0},
{0x2102c1, 0x0},
{0x0103c1, 0x0},
{0x1103c1, 0x0},
{0x2103c1, 0x0},
{0x0104c1, 0x0},
{0x1104c1, 0x0},
{0x2104c1, 0x0},
{0x0105c1, 0x0},
{0x1105c1, 0x0},
{0x2105c1, 0x0},
{0x0106c1, 0x0},
{0x1106c1, 0x0},
{0x2106c1, 0x0},
{0x0107c1, 0x0},
{0x1107c1, 0x0},
{0x2107c1, 0x0},
{0x0108c1, 0x0},
{0x1108c1, 0x0},
{0x2108c1, 0x0},
{0x0100c2, 0x0},
{0x1100c2, 0x0},
{0x2100c2, 0x0},
{0x0101c2, 0x0},
{0x1101c2, 0x0},
{0x2101c2, 0x0},
{0x0102c2, 0x0},
{0x1102c2, 0x0},
{0x2102c2, 0x0},
{0x0103c2, 0x0},
{0x1103c2, 0x0},
{0x2103c2, 0x0},
{0x0104c2, 0x0},
{0x1104c2, 0x0},
{0x2104c2, 0x0},
{0x0105c2, 0x0},
{0x1105c2, 0x0},
{0x2105c2, 0x0},
{0x0106c2, 0x0},
{0x1106c2, 0x0},
{0x2106c2, 0x0},
{0x0107c2, 0x0},
{0x1107c2, 0x0},
{0x2107c2, 0x0},
{0x0108c2, 0x0},
{0x1108c2, 0x0},
{0x2108c2, 0x0},
{0x0100c3, 0x0},
{0x1100c3, 0x0},
{0x2100c3, 0x0},
{0x0101c3, 0x0},
{0x1101c3, 0x0},
{0x2101c3, 0x0},
{0x0102c3, 0x0},
{0x1102c3, 0x0},
{0x2102c3, 0x0},
{0x0103c3, 0x0},
{0x1103c3, 0x0},
{0x2103c3, 0x0},
{0x0104c3, 0x0},
{0x1104c3, 0x0},
{0x2104c3, 0x0},
{0x0105c3, 0x0},
{0x1105c3, 0x0},
{0x2105c3, 0x0},
{0x0106c3, 0x0},
{0x1106c3, 0x0},
{0x2106c3, 0x0},
{0x0107c3, 0x0},
{0x1107c3, 0x0},
{0x2107c3, 0x0},
{0x0108c3, 0x0},
{0x1108c3, 0x0},
{0x2108c3, 0x0},
{0x0110c0, 0x0},
{0x1110c0, 0x0},
{0x2110c0, 0x0},
{0x0111c0, 0x0},
{0x1111c0, 0x0},
{0x2111c0, 0x0},
{0x0112c0, 0x0},
{0x1112c0, 0x0},
{0x2112c0, 0x0},
{0x0113c0, 0x0},
{0x1113c0, 0x0},
{0x2113c0, 0x0},
{0x0114c0, 0x0},
{0x1114c0, 0x0},
{0x2114c0, 0x0},
{0x0115c0, 0x0},
{0x1115c0, 0x0},
{0x2115c0, 0x0},
{0x0116c0, 0x0},
{0x1116c0, 0x0},
{0x2116c0, 0x0},
{0x0117c0, 0x0},
{0x1117c0, 0x0},
{0x2117c0, 0x0},
{0x0118c0, 0x0},
{0x1118c0, 0x0},
{0x2118c0, 0x0},
{0x0110c1, 0x0},
{0x1110c1, 0x0},
{0x2110c1, 0x0},
{0x0111c1, 0x0},
{0x1111c1, 0x0},
{0x2111c1, 0x0},
{0x0112c1, 0x0},
{0x1112c1, 0x0},
{0x2112c1, 0x0},
{0x0113c1, 0x0},
{0x1113c1, 0x0},
{0x2113c1, 0x0},
{0x0114c1, 0x0},
{0x1114c1, 0x0},
{0x2114c1, 0x0},
{0x0115c1, 0x0},
{0x1115c1, 0x0},
{0x2115c1, 0x0},
{0x0116c1, 0x0},
{0x1116c1, 0x0},
{0x2116c1, 0x0},
{0x0117c1, 0x0},
{0x1117c1, 0x0},
{0x2117c1, 0x0},
{0x0118c1, 0x0},
{0x1118c1, 0x0},
{0x2118c1, 0x0},
{0x0110c2, 0x0},
{0x1110c2, 0x0},
{0x2110c2, 0x0},
{0x0111c2, 0x0},
{0x1111c2, 0x0},
{0x2111c2, 0x0},
{0x0112c2, 0x0},
{0x1112c2, 0x0},
{0x2112c2, 0x0},
{0x0113c2, 0x0},
{0x1113c2, 0x0},
{0x2113c2, 0x0},
{0x0114c2, 0x0},
{0x1114c2, 0x0},
{0x2114c2, 0x0},
{0x0115c2, 0x0},
{0x1115c2, 0x0},
{0x2115c2, 0x0},
{0x0116c2, 0x0},
{0x1116c2, 0x0},
{0x2116c2, 0x0},
{0x0117c2, 0x0},
{0x1117c2, 0x0},
{0x2117c2, 0x0},
{0x0118c2, 0x0},
{0x1118c2, 0x0},
{0x2118c2, 0x0},
{0x0110c3, 0x0},
{0x1110c3, 0x0},
{0x2110c3, 0x0},
{0x0111c3, 0x0},
{0x1111c3, 0x0},
{0x2111c3, 0x0},
{0x0112c3, 0x0},
{0x1112c3, 0x0},
{0x2112c3, 0x0},
{0x0113c3, 0x0},
{0x1113c3, 0x0},
{0x2113c3, 0x0},
{0x0114c3, 0x0},
{0x1114c3, 0x0},
{0x2114c3, 0x0},
{0x0115c3, 0x0},
{0x1115c3, 0x0},
{0x2115c3, 0x0},
{0x0116c3, 0x0},
{0x1116c3, 0x0},
{0x2116c3, 0x0},
{0x0117c3, 0x0},
{0x1117c3, 0x0},
{0x2117c3, 0x0},
{0x0118c3, 0x0},
{0x1118c3, 0x0},
{0x2118c3, 0x0},
{0x010020, 0x0},
{0x110020, 0x0},
{0x210020, 0x0},
{0x011020, 0x0},
{0x111020, 0x0},
{0x211020, 0x0},
{0x02007d, 0x0},
{0x12007d, 0x0},
{0x22007d, 0x0},
};
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0x640 },
{ 0x54004, 0x2 },
{ 0x54005, 0x283c },
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
{ 0x5400b, 0x31f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1d70 },
{ 0x54030, 0x4 },
{ 0x54031, 0x18 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x1 },
{ 0x54003, 0x29c },
{ 0x54004, 0x2 },
{ 0x54005, 0x283c },
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
{ 0x90002, 0x10e },
{ 0x90003, 0x0 },
{ 0x90004, 0x0 },
{ 0x90005, 0x8 },
{ 0x90029, 0xb },
{ 0x9002a, 0x480 },
{ 0x9002b, 0x109 },
{ 0x9002c, 0x8 },
{ 0x9002d, 0x448 },
{ 0x9002e, 0x139 },
{ 0x9002f, 0x8 },
{ 0x90030, 0x478 },
{ 0x90031, 0x109 },
{ 0x90032, 0x2 },
{ 0x90033, 0x10 },
{ 0x90034, 0x139 },
{ 0x90035, 0xb },
{ 0x90036, 0x7c0 },
{ 0x90037, 0x139 },
{ 0x90038, 0x44 },
{ 0x90039, 0x633 },
{ 0x9003a, 0x159 },
{ 0x9003b, 0x14f },
{ 0x9003c, 0x630 },
{ 0x9003d, 0x159 },
{ 0x9003e, 0x47 },
{ 0x9003f, 0x633 },
{ 0x90040, 0x149 },
{ 0x90041, 0x4f },
{ 0x90042, 0x633 },
{ 0x90043, 0x179 },
{ 0x90044, 0x8 },
{ 0x90045, 0xe0 },
{ 0x90046, 0x109 },
{ 0x90047, 0x0 },
{ 0x90048, 0x7c8 },
{ 0x90049, 0x109 },
{ 0x9004a, 0x0 },
{ 0x9004b, 0x1 },
{ 0x9004c, 0x8 },
{ 0x9004d, 0x0 },
{ 0x9004e, 0x45a },
{ 0x9004f, 0x9 },
{ 0x90050, 0x0 },
{ 0x90051, 0x448 },
{ 0x90052, 0x109 },
{ 0x90053, 0x40 },
{ 0x90054, 0x633 },
{ 0x90055, 0x179 },
{ 0x90056, 0x1 },
{ 0x90057, 0x618 },
{ 0x90058, 0x109 },
{ 0x90059, 0x40c0 },
{ 0x9005a, 0x633 },
{ 0x9005b, 0x149 },
{ 0x9005c, 0x8 },
{ 0x9005d, 0x4 },
{ 0x9005e, 0x48 },
{ 0x9005f, 0x4040 },
{ 0x90060, 0x633 },
{ 0x90061, 0x149 },
{ 0x90062, 0x0 },
{ 0x90063, 0x4 },
{ 0x90064, 0x48 },
{ 0x90065, 0x40 },
{ 0x90066, 0x633 },
{ 0x90067, 0x149 },
{ 0x90068, 0x10 },
{ 0x90069, 0x4 },
{ 0x9006a, 0x18 },
{ 0x9006b, 0x0 },
{ 0x9006c, 0x4 },
{ 0x9006d, 0x78 },
{ 0x9006e, 0x549 },
{ 0x9006f, 0x633 },
{ 0x90070, 0x159 },
{ 0x90071, 0xd49 },
{ 0x90072, 0x633 },
{ 0x90073, 0x159 },
{ 0x90074, 0x94a },
{ 0x90075, 0x633 },
{ 0x90076, 0x159 },
{ 0x90077, 0x441 },
{ 0x90078, 0x633 },
{ 0x90079, 0x149 },
{ 0x9007a, 0x42 },
{ 0x9007b, 0x633 },
{ 0x9007c, 0x149 },
{ 0x9007d, 0x1 },
{ 0x9007e, 0x633 },
{ 0x9007f, 0x149 },
{ 0x90080, 0x0 },
{ 0x90081, 0xe0 },
{ 0x90082, 0x109 },
{ 0x90083, 0xa },
{ 0x90084, 0x10 },
{ 0x90085, 0x109 },
{ 0x90086, 0x9 },
{ 0x90087, 0x3c0 },
{ 0x90088, 0x149 },
{ 0x90089, 0x9 },
{ 0x9008a, 0x3c0 },
{ 0x9008b, 0x159 },
{ 0x9008c, 0x18 },
{ 0x9008d, 0x10 },
{ 0x9008e, 0x109 },
{ 0x9008f, 0x0 },
{ 0x90090, 0x3c0 },
{ 0x90091, 0x109 },
{ 0x90092, 0x18 },
{ 0x90093, 0x4 },
{ 0x90094, 0x48 },
{ 0x90095, 0x18 },
{ 0x90096, 0x4 },
{ 0x90097, 0x58 },
{ 0x90098, 0xb },
{ 0x90099, 0x10 },
{ 0x9009a, 0x109 },
{ 0x9009b, 0x1 },
{ 0x9009c, 0x10 },
{ 0x9009d, 0x109 },
{ 0x9009e, 0x5 },
{ 0x9009f, 0x7c0 },
{ 0x900a0, 0x109 },
{ 0x900a1, 0x0 },
{ 0x900a2, 0x8140 },
{ 0x900a3, 0x10c },
{ 0x900a4, 0x10 },
{ 0x900a5, 0x8138 },
{ 0x900a6, 0x10c },
{ 0x900a7, 0x8 },
{ 0x900a8, 0x7c8 },
{ 0x900a9, 0x101 },
{ 0x900aa, 0x8 },
{ 0x900ab, 0x448 },
{ 0x900ac, 0x109 },
{ 0x900ad, 0xf },
{ 0x900ae, 0x7c0 },
{ 0x900af, 0x109 },
{ 0x900b0, 0x47 },
{ 0x900b1, 0x630 },
{ 0x900b2, 0x109 },
{ 0x900b3, 0x8 },
{ 0x900b4, 0x618 },
{ 0x900b5, 0x109 },
{ 0x900b6, 0x8 },
{ 0x900b7, 0xe0 },
{ 0x900b8, 0x109 },
{ 0x900b9, 0x0 },
{ 0x900ba, 0x7c8 },
{ 0x900bb, 0x109 },
{ 0x900bc, 0x8 },
{ 0x900bd, 0x8140 },
{ 0x900be, 0x10c },
{ 0x900bf, 0x0 },
{ 0x900c0, 0x1 },
{ 0x900c1, 0x8 },
{ 0x900c2, 0x8 },
{ 0x900c3, 0x4 },
{ 0x900c4, 0x8 },
{ 0x900c5, 0x8 },
{ 0x900c6, 0x7c8 },
{ 0x900c7, 0x101 },
{ 0x90006, 0x0 },
{ 0x90007, 0x0 },
{ 0x90008, 0x8 },
{ 0x90009, 0x0 },
{ 0x9000a, 0x0 },
{ 0x9000b, 0x0 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
{ 0x2000b, 0x32 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x14 },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
{ 0x9000c, 0x0 },
{ 0x9000d, 0x173 },
{ 0x9000e, 0x60 },
{ 0x9000f, 0x6110 },
{ 0x90010, 0x2152 },
{ 0x90011, 0xdfbd },
{ 0x90012, 0xffff },
{ 0x90013, 0x6152 },
{ 0x20089, 0x1 },
{ 0x20088, 0x19 },
{ 0xc0080, 0x0 },
{ 0xd0000, 0x1 }
};
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
/* P0 1600mts 1D */
.drate = 1600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
/* P1 667mts 1D */
.drate = 667,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
};
/* ddr timing config params */
struct dram_timing_info dram_timing = {
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
.fsp_msg = ddr_dram_fsp_msg,
.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 1600, 667, },
};

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@ -0,0 +1,941 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2019 NXP
*
* Generated code from MX8M_DDR_tool
*
* Align with uboot version:
* imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.1.0_ga
* For imx_v2019.04_5.4.x and above version:
* please replace #include <asm/arch/imx8m_ddr.h> with #include <asm/arch/ddr.h>
*/
#include <linux/kernel.h>
#include <asm/arch/ddr.h>
struct dram_cfg_param ddr_ddrc_cfg[] = {
/** Initialize DDRC registers **/
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x20 },
{ 0x3d400000, 0xa1040001 },
{ 0x3d400064, 0x610068 },
{ 0x3d4000d0, 0xc00200c5 },
{ 0x3d4000d4, 0x1000b },
{ 0x3d4000dc, 0x1d700004 },
{ 0x3d4000e0, 0x180000 },
{ 0x3d4000e4, 0x90000 },
{ 0x3d4000f0, 0x0 },
{ 0x3d4000f4, 0xee5 },
{ 0x3d400100, 0xc101b0e },
{ 0x3d400104, 0x30314 },
{ 0x3d400108, 0x4060509 },
{ 0x3d40010c, 0x2006 },
{ 0x3d400110, 0x6020306 },
{ 0x3d400114, 0x4040302 },
{ 0x3d400120, 0x909 },
{ 0x3d400180, 0x40800020 },
{ 0x3d400184, 0xc350 },
{ 0x3d400190, 0x3868203 },
{ 0x3d400194, 0x20303 },
{ 0x3d4001b4, 0x603 },
{ 0x3d400198, 0x7000000 },
{ 0x3d4001b0, 0x11 },
{ 0x3d4001a0, 0x400018 },
{ 0x3d4001a4, 0x5003c },
{ 0x3d4001a8, 0x80000000 },
{ 0x3d4001c4, 0x0 },
{ 0x3d400200, 0x1f },
{ 0x3d400204, 0x80808 },
{ 0x3d400208, 0x0 },
{ 0x3d40020c, 0x0 },
{ 0x3d400210, 0x1f1f },
{ 0x3d400214, 0x7070707 },
{ 0x3d400218, 0xf070707 },
{ 0x3d400240, 0x600060c },
{ 0x3d400244, 0x1323 },
{ 0x3d400400, 0x100 },
{ 0x3d400250, 0x7ab50b07 },
{ 0x3d400254, 0x22 },
{ 0x3d40025c, 0x7b00665e },
{ 0x3d400264, 0xb0000040 },
{ 0x3d40026c, 0x50000a0c },
{ 0x3d400300, 0x17 },
{ 0x3d40036c, 0x10000 },
{ 0x3d400404, 0x3051 },
{ 0x3d400408, 0x61d2 },
{ 0x3d400494, 0xe00 },
{ 0x3d400498, 0x7ff },
{ 0x3d40049c, 0xe00 },
{ 0x3d4004a0, 0x7ff },
{ 0x3d402064, 0x28003c },
{ 0x3d4020dc, 0x12200004 },
{ 0x3d4020e0, 0x0 },
{ 0x3d402100, 0x7090b07 },
{ 0x3d402104, 0x20209 },
{ 0x3d402108, 0x3030407 },
{ 0x3d40210c, 0x2006 },
{ 0x3d402110, 0x3020203 },
{ 0x3d402114, 0x3030202 },
{ 0x3d402120, 0x909 },
{ 0x3d402180, 0x40800020 },
{ 0x3d402190, 0x3818200 },
{ 0x3d402194, 0x20303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d402240, 0x6000604 },
{ 0x3d4020f4, 0xee5 },
{ 0x3d400028, 0x1 },
};
/* PHY Initialize Configuration */
struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x1005f, 0x3ff },
{ 0x1015f, 0x3ff },
{ 0x1105f, 0x3ff },
{ 0x1115f, 0x3ff },
{ 0x11005f, 0x3ff },
{ 0x11015f, 0x3ff },
{ 0x11105f, 0x3ff },
{ 0x11115f, 0x3ff },
{ 0x55, 0x3ff },
{ 0x1055, 0x3ff },
{ 0x2055, 0x3ff },
{ 0x3055, 0x3ff },
{ 0x4055, 0xff },
{ 0x5055, 0xff },
{ 0x6055, 0x3ff },
{ 0x7055, 0x3ff },
{ 0x8055, 0x3ff },
{ 0x9055, 0x3ff },
{ 0x200c5, 0xb },
{ 0x1200c5, 0x7 },
{ 0x2002e, 0x1 },
{ 0x12002e, 0x1 },
{ 0x20024, 0x0 },
{ 0x2003a, 0x0 },
{ 0x120024, 0x0 },
{ 0x2003a, 0x0 },
{ 0x20056, 0xa },
{ 0x120056, 0xa },
{ 0x1004d, 0x208 },
{ 0x1014d, 0x208 },
{ 0x1104d, 0x208 },
{ 0x1114d, 0x208 },
{ 0x11004d, 0x208 },
{ 0x11014d, 0x208 },
{ 0x11104d, 0x208 },
{ 0x11114d, 0x208 },
{ 0x10049, 0xe38 },
{ 0x10149, 0xe38 },
{ 0x11049, 0xe38 },
{ 0x11149, 0xe38 },
{ 0x110049, 0xe38 },
{ 0x110149, 0xe38 },
{ 0x111049, 0xe38 },
{ 0x111149, 0xe38 },
{ 0x43, 0x63 },
{ 0x1043, 0x63 },
{ 0x2043, 0x63 },
{ 0x3043, 0x63 },
{ 0x4043, 0x63 },
{ 0x5043, 0x63 },
{ 0x6043, 0x63 },
{ 0x7043, 0x63 },
{ 0x8043, 0x63 },
{ 0x9043, 0x63 },
{ 0x20018, 0x1 },
{ 0x20075, 0x0 },
{ 0x20050, 0x0 },
{ 0x20008, 0x190 },
{ 0x120008, 0xa7 },
{ 0x20088, 0x9 },
{ 0x200b2, 0x32c },
{ 0x10043, 0x581 },
{ 0x10143, 0x581 },
{ 0x11043, 0x581 },
{ 0x11143, 0x581 },
{ 0x1200b2, 0x32c },
{ 0x110043, 0x581 },
{ 0x110143, 0x581 },
{ 0x111043, 0x581 },
{ 0x111143, 0x581 },
{ 0x200fa, 0x1 },
{ 0x1200fa, 0x1 },
{ 0x20019, 0x5 },
{ 0x120019, 0x5 },
{ 0x200f0, 0x5555 },
{ 0x200f1, 0x5555 },
{ 0x200f2, 0x5555 },
{ 0x200f3, 0x5555 },
{ 0x200f4, 0x5555 },
{ 0x200f5, 0x5555 },
{ 0x200f6, 0x5555 },
{ 0x200f7, 0xf000 },
{ 0x20025, 0x0 },
{ 0x2007d, 0x212 },
{ 0x12007d, 0x212 },
{ 0x2007c, 0x61 },
{ 0x12007c, 0x61 },
{ 0x1004a, 0x500 },
{ 0x1104a, 0x500 },
{ 0x2002c, 0x0 },
};
/* ddr phy trained csr */
struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
{0x0200b2, 0x0},
{0x1200b2, 0x0},
{0x2200b2, 0x0},
{0x0200cb, 0x0},
{0x010043, 0x0},
{0x110043, 0x0},
{0x210043, 0x0},
{0x010143, 0x0},
{0x110143, 0x0},
{0x210143, 0x0},
{0x011043, 0x0},
{0x111043, 0x0},
{0x211043, 0x0},
{0x011143, 0x0},
{0x111143, 0x0},
{0x211143, 0x0},
{0x000080, 0x0},
{0x100080, 0x0},
{0x200080, 0x0},
{0x001080, 0x0},
{0x101080, 0x0},
{0x201080, 0x0},
{0x002080, 0x0},
{0x102080, 0x0},
{0x202080, 0x0},
{0x003080, 0x0},
{0x103080, 0x0},
{0x203080, 0x0},
{0x004080, 0x0},
{0x104080, 0x0},
{0x204080, 0x0},
{0x005080, 0x0},
{0x105080, 0x0},
{0x205080, 0x0},
{0x006080, 0x0},
{0x106080, 0x0},
{0x206080, 0x0},
{0x007080, 0x0},
{0x107080, 0x0},
{0x207080, 0x0},
{0x008080, 0x0},
{0x108080, 0x0},
{0x208080, 0x0},
{0x009080, 0x0},
{0x109080, 0x0},
{0x209080, 0x0},
{0x010080, 0x0},
{0x110080, 0x0},
{0x210080, 0x0},
{0x010180, 0x0},
{0x110180, 0x0},
{0x210180, 0x0},
{0x010081, 0x0},
{0x110081, 0x0},
{0x210081, 0x0},
{0x010181, 0x0},
{0x110181, 0x0},
{0x210181, 0x0},
{0x010082, 0x0},
{0x110082, 0x0},
{0x210082, 0x0},
{0x010182, 0x0},
{0x110182, 0x0},
{0x210182, 0x0},
{0x010083, 0x0},
{0x110083, 0x0},
{0x210083, 0x0},
{0x010183, 0x0},
{0x110183, 0x0},
{0x210183, 0x0},
{0x011080, 0x0},
{0x111080, 0x0},
{0x211080, 0x0},
{0x011180, 0x0},
{0x111180, 0x0},
{0x211180, 0x0},
{0x011081, 0x0},
{0x111081, 0x0},
{0x211081, 0x0},
{0x011181, 0x0},
{0x111181, 0x0},
{0x211181, 0x0},
{0x011082, 0x0},
{0x111082, 0x0},
{0x211082, 0x0},
{0x011182, 0x0},
{0x111182, 0x0},
{0x211182, 0x0},
{0x011083, 0x0},
{0x111083, 0x0},
{0x211083, 0x0},
{0x011183, 0x0},
{0x111183, 0x0},
{0x211183, 0x0},
{0x0100d0, 0x0},
{0x1100d0, 0x0},
{0x2100d0, 0x0},
{0x0101d0, 0x0},
{0x1101d0, 0x0},
{0x2101d0, 0x0},
{0x0100d1, 0x0},
{0x1100d1, 0x0},
{0x2100d1, 0x0},
{0x0101d1, 0x0},
{0x1101d1, 0x0},
{0x2101d1, 0x0},
{0x0100d2, 0x0},
{0x1100d2, 0x0},
{0x2100d2, 0x0},
{0x0101d2, 0x0},
{0x1101d2, 0x0},
{0x2101d2, 0x0},
{0x0100d3, 0x0},
{0x1100d3, 0x0},
{0x2100d3, 0x0},
{0x0101d3, 0x0},
{0x1101d3, 0x0},
{0x2101d3, 0x0},
{0x0110d0, 0x0},
{0x1110d0, 0x0},
{0x2110d0, 0x0},
{0x0111d0, 0x0},
{0x1111d0, 0x0},
{0x2111d0, 0x0},
{0x0110d1, 0x0},
{0x1110d1, 0x0},
{0x2110d1, 0x0},
{0x0111d1, 0x0},
{0x1111d1, 0x0},
{0x2111d1, 0x0},
{0x0110d2, 0x0},
{0x1110d2, 0x0},
{0x2110d2, 0x0},
{0x0111d2, 0x0},
{0x1111d2, 0x0},
{0x2111d2, 0x0},
{0x0110d3, 0x0},
{0x1110d3, 0x0},
{0x2110d3, 0x0},
{0x0111d3, 0x0},
{0x1111d3, 0x0},
{0x2111d3, 0x0},
{0x010068, 0x0},
{0x010168, 0x0},
{0x010268, 0x0},
{0x010368, 0x0},
{0x010468, 0x0},
{0x010568, 0x0},
{0x010668, 0x0},
{0x010768, 0x0},
{0x010868, 0x0},
{0x010069, 0x0},
{0x010169, 0x0},
{0x010269, 0x0},
{0x010369, 0x0},
{0x010469, 0x0},
{0x010569, 0x0},
{0x010669, 0x0},
{0x010769, 0x0},
{0x010869, 0x0},
{0x01006a, 0x0},
{0x01016a, 0x0},
{0x01026a, 0x0},
{0x01036a, 0x0},
{0x01046a, 0x0},
{0x01056a, 0x0},
{0x01066a, 0x0},
{0x01076a, 0x0},
{0x01086a, 0x0},
{0x01006b, 0x0},
{0x01016b, 0x0},
{0x01026b, 0x0},
{0x01036b, 0x0},
{0x01046b, 0x0},
{0x01056b, 0x0},
{0x01066b, 0x0},
{0x01076b, 0x0},
{0x01086b, 0x0},
{0x011068, 0x0},
{0x011168, 0x0},
{0x011268, 0x0},
{0x011368, 0x0},
{0x011468, 0x0},
{0x011568, 0x0},
{0x011668, 0x0},
{0x011768, 0x0},
{0x011868, 0x0},
{0x011069, 0x0},
{0x011169, 0x0},
{0x011269, 0x0},
{0x011369, 0x0},
{0x011469, 0x0},
{0x011569, 0x0},
{0x011669, 0x0},
{0x011769, 0x0},
{0x011869, 0x0},
{0x01106a, 0x0},
{0x01116a, 0x0},
{0x01126a, 0x0},
{0x01136a, 0x0},
{0x01146a, 0x0},
{0x01156a, 0x0},
{0x01166a, 0x0},
{0x01176a, 0x0},
{0x01186a, 0x0},
{0x01106b, 0x0},
{0x01116b, 0x0},
{0x01126b, 0x0},
{0x01136b, 0x0},
{0x01146b, 0x0},
{0x01156b, 0x0},
{0x01166b, 0x0},
{0x01176b, 0x0},
{0x01186b, 0x0},
{0x01008c, 0x0},
{0x11008c, 0x0},
{0x21008c, 0x0},
{0x01018c, 0x0},
{0x11018c, 0x0},
{0x21018c, 0x0},
{0x01008d, 0x0},
{0x11008d, 0x0},
{0x21008d, 0x0},
{0x01018d, 0x0},
{0x11018d, 0x0},
{0x21018d, 0x0},
{0x01008e, 0x0},
{0x11008e, 0x0},
{0x21008e, 0x0},
{0x01018e, 0x0},
{0x11018e, 0x0},
{0x21018e, 0x0},
{0x01008f, 0x0},
{0x11008f, 0x0},
{0x21008f, 0x0},
{0x01018f, 0x0},
{0x11018f, 0x0},
{0x21018f, 0x0},
{0x01108c, 0x0},
{0x11108c, 0x0},
{0x21108c, 0x0},
{0x01118c, 0x0},
{0x11118c, 0x0},
{0x21118c, 0x0},
{0x01108d, 0x0},
{0x11108d, 0x0},
{0x21108d, 0x0},
{0x01118d, 0x0},
{0x11118d, 0x0},
{0x21118d, 0x0},
{0x01108e, 0x0},
{0x11108e, 0x0},
{0x21108e, 0x0},
{0x01118e, 0x0},
{0x11118e, 0x0},
{0x21118e, 0x0},
{0x01108f, 0x0},
{0x11108f, 0x0},
{0x21108f, 0x0},
{0x01118f, 0x0},
{0x11118f, 0x0},
{0x21118f, 0x0},
{0x0100c0, 0x0},
{0x1100c0, 0x0},
{0x2100c0, 0x0},
{0x0101c0, 0x0},
{0x1101c0, 0x0},
{0x2101c0, 0x0},
{0x0102c0, 0x0},
{0x1102c0, 0x0},
{0x2102c0, 0x0},
{0x0103c0, 0x0},
{0x1103c0, 0x0},
{0x2103c0, 0x0},
{0x0104c0, 0x0},
{0x1104c0, 0x0},
{0x2104c0, 0x0},
{0x0105c0, 0x0},
{0x1105c0, 0x0},
{0x2105c0, 0x0},
{0x0106c0, 0x0},
{0x1106c0, 0x0},
{0x2106c0, 0x0},
{0x0107c0, 0x0},
{0x1107c0, 0x0},
{0x2107c0, 0x0},
{0x0108c0, 0x0},
{0x1108c0, 0x0},
{0x2108c0, 0x0},
{0x0100c1, 0x0},
{0x1100c1, 0x0},
{0x2100c1, 0x0},
{0x0101c1, 0x0},
{0x1101c1, 0x0},
{0x2101c1, 0x0},
{0x0102c1, 0x0},
{0x1102c1, 0x0},
{0x2102c1, 0x0},
{0x0103c1, 0x0},
{0x1103c1, 0x0},
{0x2103c1, 0x0},
{0x0104c1, 0x0},
{0x1104c1, 0x0},
{0x2104c1, 0x0},
{0x0105c1, 0x0},
{0x1105c1, 0x0},
{0x2105c1, 0x0},
{0x0106c1, 0x0},
{0x1106c1, 0x0},
{0x2106c1, 0x0},
{0x0107c1, 0x0},
{0x1107c1, 0x0},
{0x2107c1, 0x0},
{0x0108c1, 0x0},
{0x1108c1, 0x0},
{0x2108c1, 0x0},
{0x0100c2, 0x0},
{0x1100c2, 0x0},
{0x2100c2, 0x0},
{0x0101c2, 0x0},
{0x1101c2, 0x0},
{0x2101c2, 0x0},
{0x0102c2, 0x0},
{0x1102c2, 0x0},
{0x2102c2, 0x0},
{0x0103c2, 0x0},
{0x1103c2, 0x0},
{0x2103c2, 0x0},
{0x0104c2, 0x0},
{0x1104c2, 0x0},
{0x2104c2, 0x0},
{0x0105c2, 0x0},
{0x1105c2, 0x0},
{0x2105c2, 0x0},
{0x0106c2, 0x0},
{0x1106c2, 0x0},
{0x2106c2, 0x0},
{0x0107c2, 0x0},
{0x1107c2, 0x0},
{0x2107c2, 0x0},
{0x0108c2, 0x0},
{0x1108c2, 0x0},
{0x2108c2, 0x0},
{0x0100c3, 0x0},
{0x1100c3, 0x0},
{0x2100c3, 0x0},
{0x0101c3, 0x0},
{0x1101c3, 0x0},
{0x2101c3, 0x0},
{0x0102c3, 0x0},
{0x1102c3, 0x0},
{0x2102c3, 0x0},
{0x0103c3, 0x0},
{0x1103c3, 0x0},
{0x2103c3, 0x0},
{0x0104c3, 0x0},
{0x1104c3, 0x0},
{0x2104c3, 0x0},
{0x0105c3, 0x0},
{0x1105c3, 0x0},
{0x2105c3, 0x0},
{0x0106c3, 0x0},
{0x1106c3, 0x0},
{0x2106c3, 0x0},
{0x0107c3, 0x0},
{0x1107c3, 0x0},
{0x2107c3, 0x0},
{0x0108c3, 0x0},
{0x1108c3, 0x0},
{0x2108c3, 0x0},
{0x0110c0, 0x0},
{0x1110c0, 0x0},
{0x2110c0, 0x0},
{0x0111c0, 0x0},
{0x1111c0, 0x0},
{0x2111c0, 0x0},
{0x0112c0, 0x0},
{0x1112c0, 0x0},
{0x2112c0, 0x0},
{0x0113c0, 0x0},
{0x1113c0, 0x0},
{0x2113c0, 0x0},
{0x0114c0, 0x0},
{0x1114c0, 0x0},
{0x2114c0, 0x0},
{0x0115c0, 0x0},
{0x1115c0, 0x0},
{0x2115c0, 0x0},
{0x0116c0, 0x0},
{0x1116c0, 0x0},
{0x2116c0, 0x0},
{0x0117c0, 0x0},
{0x1117c0, 0x0},
{0x2117c0, 0x0},
{0x0118c0, 0x0},
{0x1118c0, 0x0},
{0x2118c0, 0x0},
{0x0110c1, 0x0},
{0x1110c1, 0x0},
{0x2110c1, 0x0},
{0x0111c1, 0x0},
{0x1111c1, 0x0},
{0x2111c1, 0x0},
{0x0112c1, 0x0},
{0x1112c1, 0x0},
{0x2112c1, 0x0},
{0x0113c1, 0x0},
{0x1113c1, 0x0},
{0x2113c1, 0x0},
{0x0114c1, 0x0},
{0x1114c1, 0x0},
{0x2114c1, 0x0},
{0x0115c1, 0x0},
{0x1115c1, 0x0},
{0x2115c1, 0x0},
{0x0116c1, 0x0},
{0x1116c1, 0x0},
{0x2116c1, 0x0},
{0x0117c1, 0x0},
{0x1117c1, 0x0},
{0x2117c1, 0x0},
{0x0118c1, 0x0},
{0x1118c1, 0x0},
{0x2118c1, 0x0},
{0x0110c2, 0x0},
{0x1110c2, 0x0},
{0x2110c2, 0x0},
{0x0111c2, 0x0},
{0x1111c2, 0x0},
{0x2111c2, 0x0},
{0x0112c2, 0x0},
{0x1112c2, 0x0},
{0x2112c2, 0x0},
{0x0113c2, 0x0},
{0x1113c2, 0x0},
{0x2113c2, 0x0},
{0x0114c2, 0x0},
{0x1114c2, 0x0},
{0x2114c2, 0x0},
{0x0115c2, 0x0},
{0x1115c2, 0x0},
{0x2115c2, 0x0},
{0x0116c2, 0x0},
{0x1116c2, 0x0},
{0x2116c2, 0x0},
{0x0117c2, 0x0},
{0x1117c2, 0x0},
{0x2117c2, 0x0},
{0x0118c2, 0x0},
{0x1118c2, 0x0},
{0x2118c2, 0x0},
{0x0110c3, 0x0},
{0x1110c3, 0x0},
{0x2110c3, 0x0},
{0x0111c3, 0x0},
{0x1111c3, 0x0},
{0x2111c3, 0x0},
{0x0112c3, 0x0},
{0x1112c3, 0x0},
{0x2112c3, 0x0},
{0x0113c3, 0x0},
{0x1113c3, 0x0},
{0x2113c3, 0x0},
{0x0114c3, 0x0},
{0x1114c3, 0x0},
{0x2114c3, 0x0},
{0x0115c3, 0x0},
{0x1115c3, 0x0},
{0x2115c3, 0x0},
{0x0116c3, 0x0},
{0x1116c3, 0x0},
{0x2116c3, 0x0},
{0x0117c3, 0x0},
{0x1117c3, 0x0},
{0x2117c3, 0x0},
{0x0118c3, 0x0},
{0x1118c3, 0x0},
{0x2118c3, 0x0},
{0x010020, 0x0},
{0x110020, 0x0},
{0x210020, 0x0},
{0x011020, 0x0},
{0x111020, 0x0},
{0x211020, 0x0},
{0x02007d, 0x0},
{0x12007d, 0x0},
{0x22007d, 0x0},
};
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54003, 0x640 },
{ 0x54004, 0x2 },
{ 0x54005, 0x283c },
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
{ 0x5400b, 0x31f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1d70 },
{ 0x54030, 0x4 },
{ 0x54031, 0x18 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
/* P1 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp1_cfg[] = {
{ 0xd0000, 0x0 },
{ 0x54002, 0x1 },
{ 0x54003, 0x29c },
{ 0x54004, 0x2 },
{ 0x54005, 0x283c },
{ 0x54006, 0x140 },
{ 0x54007, 0x1000 },
{ 0x54008, 0x101 },
{ 0x5400b, 0x21f },
{ 0x5400c, 0xc8 },
{ 0x54012, 0x1 },
{ 0x5402f, 0x1220 },
{ 0x54030, 0x4 },
{ 0x5403a, 0x1323 },
{ 0xd0000, 0x1 },
};
/* DRAM PHY init engine image */
struct dram_cfg_param ddr_phy_pie[] = {
{ 0xd0000, 0x0 },
{ 0x90000, 0x10 },
{ 0x90001, 0x400 },
{ 0x90002, 0x10e },
{ 0x90003, 0x0 },
{ 0x90004, 0x0 },
{ 0x90005, 0x8 },
{ 0x90029, 0xb },
{ 0x9002a, 0x480 },
{ 0x9002b, 0x109 },
{ 0x9002c, 0x8 },
{ 0x9002d, 0x448 },
{ 0x9002e, 0x139 },
{ 0x9002f, 0x8 },
{ 0x90030, 0x478 },
{ 0x90031, 0x109 },
{ 0x90032, 0x2 },
{ 0x90033, 0x10 },
{ 0x90034, 0x139 },
{ 0x90035, 0xb },
{ 0x90036, 0x7c0 },
{ 0x90037, 0x139 },
{ 0x90038, 0x44 },
{ 0x90039, 0x633 },
{ 0x9003a, 0x159 },
{ 0x9003b, 0x14f },
{ 0x9003c, 0x630 },
{ 0x9003d, 0x159 },
{ 0x9003e, 0x47 },
{ 0x9003f, 0x633 },
{ 0x90040, 0x149 },
{ 0x90041, 0x4f },
{ 0x90042, 0x633 },
{ 0x90043, 0x179 },
{ 0x90044, 0x8 },
{ 0x90045, 0xe0 },
{ 0x90046, 0x109 },
{ 0x90047, 0x0 },
{ 0x90048, 0x7c8 },
{ 0x90049, 0x109 },
{ 0x9004a, 0x0 },
{ 0x9004b, 0x1 },
{ 0x9004c, 0x8 },
{ 0x9004d, 0x0 },
{ 0x9004e, 0x45a },
{ 0x9004f, 0x9 },
{ 0x90050, 0x0 },
{ 0x90051, 0x448 },
{ 0x90052, 0x109 },
{ 0x90053, 0x40 },
{ 0x90054, 0x633 },
{ 0x90055, 0x179 },
{ 0x90056, 0x1 },
{ 0x90057, 0x618 },
{ 0x90058, 0x109 },
{ 0x90059, 0x40c0 },
{ 0x9005a, 0x633 },
{ 0x9005b, 0x149 },
{ 0x9005c, 0x8 },
{ 0x9005d, 0x4 },
{ 0x9005e, 0x48 },
{ 0x9005f, 0x4040 },
{ 0x90060, 0x633 },
{ 0x90061, 0x149 },
{ 0x90062, 0x0 },
{ 0x90063, 0x4 },
{ 0x90064, 0x48 },
{ 0x90065, 0x40 },
{ 0x90066, 0x633 },
{ 0x90067, 0x149 },
{ 0x90068, 0x10 },
{ 0x90069, 0x4 },
{ 0x9006a, 0x18 },
{ 0x9006b, 0x0 },
{ 0x9006c, 0x4 },
{ 0x9006d, 0x78 },
{ 0x9006e, 0x549 },
{ 0x9006f, 0x633 },
{ 0x90070, 0x159 },
{ 0x90071, 0xd49 },
{ 0x90072, 0x633 },
{ 0x90073, 0x159 },
{ 0x90074, 0x94a },
{ 0x90075, 0x633 },
{ 0x90076, 0x159 },
{ 0x90077, 0x441 },
{ 0x90078, 0x633 },
{ 0x90079, 0x149 },
{ 0x9007a, 0x42 },
{ 0x9007b, 0x633 },
{ 0x9007c, 0x149 },
{ 0x9007d, 0x1 },
{ 0x9007e, 0x633 },
{ 0x9007f, 0x149 },
{ 0x90080, 0x0 },
{ 0x90081, 0xe0 },
{ 0x90082, 0x109 },
{ 0x90083, 0xa },
{ 0x90084, 0x10 },
{ 0x90085, 0x109 },
{ 0x90086, 0x9 },
{ 0x90087, 0x3c0 },
{ 0x90088, 0x149 },
{ 0x90089, 0x9 },
{ 0x9008a, 0x3c0 },
{ 0x9008b, 0x159 },
{ 0x9008c, 0x18 },
{ 0x9008d, 0x10 },
{ 0x9008e, 0x109 },
{ 0x9008f, 0x0 },
{ 0x90090, 0x3c0 },
{ 0x90091, 0x109 },
{ 0x90092, 0x18 },
{ 0x90093, 0x4 },
{ 0x90094, 0x48 },
{ 0x90095, 0x18 },
{ 0x90096, 0x4 },
{ 0x90097, 0x58 },
{ 0x90098, 0xb },
{ 0x90099, 0x10 },
{ 0x9009a, 0x109 },
{ 0x9009b, 0x1 },
{ 0x9009c, 0x10 },
{ 0x9009d, 0x109 },
{ 0x9009e, 0x5 },
{ 0x9009f, 0x7c0 },
{ 0x900a0, 0x109 },
{ 0x900a1, 0x0 },
{ 0x900a2, 0x8140 },
{ 0x900a3, 0x10c },
{ 0x900a4, 0x10 },
{ 0x900a5, 0x8138 },
{ 0x900a6, 0x10c },
{ 0x900a7, 0x8 },
{ 0x900a8, 0x7c8 },
{ 0x900a9, 0x101 },
{ 0x900aa, 0x8 },
{ 0x900ab, 0x448 },
{ 0x900ac, 0x109 },
{ 0x900ad, 0xf },
{ 0x900ae, 0x7c0 },
{ 0x900af, 0x109 },
{ 0x900b0, 0x47 },
{ 0x900b1, 0x630 },
{ 0x900b2, 0x109 },
{ 0x900b3, 0x8 },
{ 0x900b4, 0x618 },
{ 0x900b5, 0x109 },
{ 0x900b6, 0x8 },
{ 0x900b7, 0xe0 },
{ 0x900b8, 0x109 },
{ 0x900b9, 0x0 },
{ 0x900ba, 0x7c8 },
{ 0x900bb, 0x109 },
{ 0x900bc, 0x8 },
{ 0x900bd, 0x8140 },
{ 0x900be, 0x10c },
{ 0x900bf, 0x0 },
{ 0x900c0, 0x1 },
{ 0x900c1, 0x8 },
{ 0x900c2, 0x8 },
{ 0x900c3, 0x4 },
{ 0x900c4, 0x8 },
{ 0x900c5, 0x8 },
{ 0x900c6, 0x7c8 },
{ 0x900c7, 0x101 },
{ 0x90006, 0x0 },
{ 0x90007, 0x0 },
{ 0x90008, 0x8 },
{ 0x90009, 0x0 },
{ 0x9000a, 0x0 },
{ 0x9000b, 0x0 },
{ 0xd00e7, 0x400 },
{ 0x90017, 0x0 },
{ 0x90026, 0x2b },
{ 0x2000b, 0x32 },
{ 0x2000c, 0x64 },
{ 0x2000d, 0x3e8 },
{ 0x2000e, 0x2c },
{ 0x12000b, 0x14 },
{ 0x12000c, 0x26 },
{ 0x12000d, 0x1a1 },
{ 0x12000e, 0x10 },
{ 0x9000c, 0x0 },
{ 0x9000d, 0x173 },
{ 0x9000e, 0x60 },
{ 0x9000f, 0x6110 },
{ 0x90010, 0x2152 },
{ 0x90011, 0xdfbd },
{ 0x90012, 0xffff },
{ 0x90013, 0x6152 },
{ 0x20089, 0x1 },
{ 0x20088, 0x19 },
{ 0xc0080, 0x0 },
{ 0xd0000, 0x1 }
};
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
/* P0 1600mts 1D */
.drate = 1600,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
},
{
/* P1 667mts 1D */
.drate = 667,
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp1_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg),
},
};
/* ddr timing config params */
struct dram_timing_info dram_timing = {
.ddrc_cfg = ddr_ddrc_cfg,
.ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
.ddrphy_cfg = ddr_ddrphy_cfg,
.ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg),
.fsp_msg = ddr_dram_fsp_msg,
.fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg),
.ddrphy_trained_csr = ddr_ddrphy_trained_csr,
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
.fsp_table = { 1600, 667, },
};

23
board/bsh/imx8mn_smm_s2/imx8mn_smm_s2.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <env.h>
int board_init(void)
{
return 0;
}
int board_late_init(void)
{
if (is_usb_boot()) {
env_set("bootcmd", "run bootcmd_mfg");
env_set("bootdelay", "0");
}
return 0;
}

8
board/bsh/imx8mn_smm_s2/imximage-8mn-ddr3.cfg Normal file
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@ -0,0 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Collabora Ltd.
*/
ROM_VERSION v2
BOOT_FROM sd
LOADER u-boot-spl-ddr.bin 0x912000

97
board/bsh/imx8mn_smm_s2/spl.c Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
*
*/
#include <hang.h>
#include <init.h>
#include <spl.h>
#include <asm/arch/clock.h>
#include <asm/arch/ddr.h>
#include <asm/arch/imx8mn_pins.h>
#include <asm/arch/sys_proto.h>
#include <asm/mach-imx/boot_mode.h>
#include <asm/mach-imx/gpio.h>
#include <dm/device.h>
#include <dm/uclass.h>
int spl_board_boot_device(enum boot_device boot_dev_spl)
{
return BOOT_DEVICE_BOOTROM;
}
void spl_dram_init(void)
{
ddr_init(&dram_timing);
}
void spl_board_init(void)
{
struct udevice *dev;
int ret;
debug("Normal Boot\n");
ret = uclass_get_device_by_name(UCLASS_CLK,
"clock-controller@30380000",
&dev);
if (ret < 0)
puts("Failed to find clock node. Check device tree\n");
}
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
static const iomux_v3_cfg_t uart_pads[] = {
IMX8MN_PAD_UART4_RXD__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
IMX8MN_PAD_UART4_TXD__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
};
static const iomux_v3_cfg_t wdog_pads[] = {
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
};
int board_early_init_f(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
set_wdog_reset(wdog);
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
init_uart_clk(3);
if (IS_ENABLED(CONFIG_NAND_MXS)) {
init_nand_clk();
}
return 0;
}
void board_init_f(ulong dummy)
{
int ret;
/* Clear the BSS. */
memset(__bss_start, 0, __bss_end - __bss_start);
arch_cpu_init();
board_early_init_f();
timer_init();
preloader_console_init();
ret = spl_init();
if (ret) {
debug("spl_init() failed: %d\n", ret);
hang();
}
/* DDR initialization */
spl_dram_init();
board_init_r(NULL, 0);
}

96
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CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BSH_SMM_S2=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="> "
CONFIG_CMD_FUSE=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=gpmi-nand"
CONFIG_MTDPARTS_DEFAULT="gpmi-nand:64m(nandboot),16m(nandfit),32m(nandkernel),1m(nanddtb),8m(nandtee),-(nandrootfs)"
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x40480000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_SYS_NAND_USE_FLASH_BBT=y
CONFIG_NAND_MXS=y
CONFIG_NAND_MXS_DT=y
CONFIG_SYS_NAND_ONFI_DETECTION=y
CONFIG_PHYLIB=y
CONFIG_PHY_NXP_TJA11XX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_IMX_WATCHDOG=y
# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT_OVERLAY=y

93
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CONFIG_ARM=y
CONFIG_ARCH_IMX8M=y
CONFIG_SYS_TEXT_BASE=0x40200000
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_DM_GPIO=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-bsh-smm-s2pro"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_BSH_SMM_S2PRO=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000
CONFIG_SYS_LOAD_ADDR=0x40480000
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_FIT_EXTERNAL_OFFSET=0x3000
CONFIG_SPL_LOAD_FIT=y
# CONFIG_USE_SPL_FIT_GENERATOR is not set
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_DEFAULT_FDT_FILE="freescale/imx8mn-bsh-smm-s2pro.dtb"
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_LATE_INIT=y
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_BOOTROM_SUPPORT=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x300
CONFIG_SPL_I2C=y
CONFIG_SPL_POWER=y
CONFIG_SPL_WATCHDOG=y
CONFIG_SYS_PROMPT="> "
CONFIG_CMD_FUSE=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
CONFIG_SPL_DM=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_CLK_IMX8MN=y
CONFIG_CLK_IMX8MN=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x40480000
CONFIG_FASTBOOT_BUF_SIZE=0x20000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_MXC_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_FSL_USDHC=y
CONFIG_PHYLIB=y
CONFIG_PHY_NXP_TJA11XX=y
CONFIG_DM_ETH=y
CONFIG_FEC_MXC=y
CONFIG_MII=y
CONFIG_PINCTRL=y
CONFIG_SPL_PINCTRL=y
CONFIG_PINCTRL_IMX8M=y
CONFIG_DM_PMIC=y
CONFIG_DM_PMIC_BD71837=y
CONFIG_SPL_DM_PMIC_BD71837=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_MXC_UART=y
CONFIG_SYSRESET=y
CONFIG_SYSRESET_PSCI=y
CONFIG_SYSRESET_WATCHDOG=y
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_IMX_WATCHDOG=y
# CONFIG_FAT_WRITE is not set
CONFIG_OF_LIBFDT_OVERLAY=y

61
doc/board/bsh/imx8mn_bsh_smm_s2.rst Normal file
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.. SPDX-License-Identifier: GPL-2.0+
imx8mn_bsh_smm_s2
=================
U-Boot for the BSH SystemMaster (SMM) S2 board family.
Quick Start
-----------
- Build the ARM Trusted firmware binary
- Get firmware-imx package
- Build U-Boot
- Boot
Get and Build the ARM Trusted firmware
--------------------------------------
Note: srctree is U-Boot source directory
Get ATF from: https://github.com/ARM-software/arm-trusted-firmware
tag: v2.5
.. code-block:: bash
$ make PLAT=imx8mn IMX_BOOT_UART_BASE=0x30a60000 bl31
$ cp build/imx8mn/release/bl31.bin $(srctree)
Get the ddr firmware
--------------------
.. code-block:: bash
$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-8.9.bin
$ chmod +x firmware-imx-8.9.bin
$ ./firmware-imx-8.9
$ cp firmware-imx-8.9/firmware/ddr/synopsys/ddr3*.bin $(srctree)
Build U-Boot
------------
.. code-block:: bash
$ export CROSS_COMPILE=aarch64-linux-gnu-
$ make imx8mn_bsh_smm_s2_defconfig
$ make
Burn the flash.bin to MicroSD card offset 32KB:
.. code-block:: bash
$ dd if=flash.bin of=/dev/sd[x] bs=1024 seek=32 conv=notrunc
Boot
----
Start the board in USB serial downloader mode, plug-in the USB-OTG port and
load flash.bin using Freescale/NXP UUU tool:
.. code-block:: bash
$ uuu -v flash.bin

9
doc/board/bsh/index.rst Normal file
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@ -0,0 +1,9 @@
.. SPDX-License-Identifier: GPL-2.0+
BSH Hausgeraete GmbH
====================
.. toctree::
:maxdepth: 2
imx8mn_bsh_smm_s2

1
doc/board/index.rst
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@ -15,6 +15,7 @@ Board-specific doc
armltd/index
atmel/index
broadcom/index
bsh/index
congatec/index
coreboot/index
emulation/index

51
include/configs/imx8mn_bsh_smm_s2.h Normal file
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Collabora Ltd.
*/
#ifndef __IMX8MN_BSH_SMM_S2_H
#define __IMX8MN_BSH_SMM_S2_H
#include <configs/imx8mn_bsh_smm_s2_common.h>
#define BOOT_TARGET_DEVICES(func) \
func(NAND, nand, 0) \
#include <config_distro_bootcmd.h>
#define NANDARGS \
"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
"nandargs=setenv bootargs console=${console} " \
"${optargs} " \
"root=${nandroot} " \
"rootfstype=${nandrootfstype}\0" \
"nandroot=ubi0:root rw ubi.mtd=nandrootfs\0" \
"nandrootfstype=ubifs rootwait=1\0" \
"nandboot=echo Booting from nand ...; " \
"run nandargs; " \
"nand read ${fdt_addr_r} nanddtb; " \
"nand read ${loadaddr} nandkernel; " \
"booti ${loadaddr} - ${fdt_addr_r}\0"
#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \
"bootcmd_" #devtypel #instance "=" \
"run nandboot\0"
#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \
#devtypel #instance " "
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
NANDARGS \
BOOTENV
#define PHYS_SDRAM_SIZE SZ_256M
/* NAND */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
#endif /* __IMX8MN_BSH_SMM_S2_H */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Collabora Ltd.
*/
#ifndef __IMX8MN_BSH_SMM_S2_COMMON_H
#define __IMX8MN_BSH_SMM_S2_COMMON_H
#include <linux/sizes.h>
#include <linux/stringify.h>
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M)
#define CONFIG_SPL_MAX_SIZE (148 * SZ_1K)
#define CONFIG_SYS_MONITOR_LEN SZ_512K
#define CONFIG_SYS_UBOOT_BASE \
(QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#define CONFIG_SPL_STACK 0x980000
#define CONFIG_SPL_BSS_START_ADDR 0x950000
#define CONFIG_SPL_BSS_MAX_SIZE SZ_8K
#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_512K
#define MEM_LAYOUT_ENV_SETTINGS \
"scriptaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"kernel_addr_r=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramdisk_addr_r=0x43800000\0" \
"fdt_addr_r=0x43000000\0" \
"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
"bootcmd_mfg=echo Running fastboot mode; fastboot usb 0\0" \
/* Link Definitions */
#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE SZ_512K
#define CONFIG_SYS_INIT_SP_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#define CONFIG_SYS_SDRAM_BASE 0x40000000
#define PHYS_SDRAM 0x40000000
#define CONFIG_MXC_UART_BASE UART4_BASE_ADDR
/* Monitor Command Prompt */
#define CONFIG_SYS_CBSIZE SZ_2K
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)
/* I2C */
#endif /* __IMX8MN_BSH_SMM_S2_COMMON_H */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2021 Collabora Ltd.
*/
#ifndef __IMX8MN_BSH_SMM_S2PRO_H
#define __IMX8MN_BSH_SMM_S2PRO_H
#include <configs/imx8mn_bsh_smm_s2_common.h>
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
#include <config_distro_bootcmd.h>
#define EMMCARGS \
"fastboot_partition_alias_all=" \
__stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".0:0\0" \
"fastboot_partition_alias_bootloader=" \
__stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) ".1:0\0" \
"emmc_dev=" __stringify(CONFIG_FASTBOOT_FLASH_MMC_DEV) "\0" \
"emmc_ack=1\0" \
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
MEM_LAYOUT_ENV_SETTINGS \
EMMCARGS \
BOOTENV
#define PHYS_SDRAM_SIZE SZ_512M
/* USDHC */
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_BSH_SMM_S2PRO_H */