fdt: add crypto node handling for MPC8{3, 5}xxE processors
Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Kim Phillips
Andrew Fleming-AFLEMING
parent
ab5cda9f88
commit
6b70ffb9d1
@ -442,3 +442,90 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd)
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prop, compat, fdt_strerror(err));
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}
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#endif /* CONFIG_HAS_FSL_DR_USB */
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#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx)
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/*
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* update crypto node properties to a specified revision of the SEC
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* called with sec_rev == 0 if not on an mpc8xxxE processor
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*/
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void fdt_fixup_crypto_node(void *blob, int sec_rev)
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{
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const struct sec_rev_prop {
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u32 sec_rev;
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u32 num_channels;
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u32 channel_fifo_len;
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u32 exec_units_mask;
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u32 descriptor_types_mask;
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} sec_rev_prop_list [] = {
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{ 0x0200, 4, 24, 0x07e, 0x01010ebf }, /* SEC 2.0 */
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{ 0x0201, 4, 24, 0x0fe, 0x012b0ebf }, /* SEC 2.1 */
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{ 0x0202, 1, 24, 0x04c, 0x0122003f }, /* SEC 2.2 */
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{ 0x0204, 4, 24, 0x07e, 0x012b0ebf }, /* SEC 2.4 */
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{ 0x0300, 4, 24, 0x9fe, 0x03ab0ebf }, /* SEC 3.0 */
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{ 0x0303, 4, 24, 0x97c, 0x03ab0abf }, /* SEC 3.3 */
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};
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char compat_strlist[ARRAY_SIZE(sec_rev_prop_list) *
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sizeof("fsl,secX.Y")];
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int crypto_node, sec_idx, err;
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char *p;
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u32 val;
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/* locate crypto node based on lowest common compatible */
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crypto_node = fdt_node_offset_by_compatible(blob, -1, "fsl,sec2.0");
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if (crypto_node == -FDT_ERR_NOTFOUND)
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return;
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/* delete it if not on an E-processor */
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if (crypto_node > 0 && !sec_rev) {
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fdt_del_node(blob, crypto_node);
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return;
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}
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/* else we got called for possible uprev */
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for (sec_idx = 0; sec_idx < ARRAY_SIZE(sec_rev_prop_list); sec_idx++)
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if (sec_rev_prop_list[sec_idx].sec_rev == sec_rev)
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break;
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if (sec_idx == ARRAY_SIZE(sec_rev_prop_list)) {
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puts("warning: unknown SEC revision number\n");
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return;
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}
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val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].num_channels);
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err = fdt_setprop(blob, crypto_node, "fsl,num-channels", &val, 4);
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if (err < 0)
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].descriptor_types_mask);
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err = fdt_setprop(blob, crypto_node, "fsl,descriptor-types-mask", &val, 4);
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if (err < 0)
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].exec_units_mask);
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err = fdt_setprop(blob, crypto_node, "fsl,exec-units-mask", &val, 4);
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if (err < 0)
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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val = cpu_to_fdt32(sec_rev_prop_list[sec_idx].channel_fifo_len);
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err = fdt_setprop(blob, crypto_node, "fsl,channel-fifo-len", &val, 4);
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if (err < 0)
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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val = 0;
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while (sec_idx >= 0) {
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p = compat_strlist + val;
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val += sprintf(p, "fsl,sec%d.%d",
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(sec_rev_prop_list[sec_idx].sec_rev & 0xff00) >> 8,
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sec_rev_prop_list[sec_idx].sec_rev & 0x00ff) + 1;
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sec_idx--;
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}
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err = fdt_setprop(blob, crypto_node, "compatible", &compat_strlist, val);
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if (err < 0)
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printf("WARNING: could not set crypto property: %s\n",
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fdt_strerror(err));
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}
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#endif /* defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) */
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@ -26,6 +26,7 @@
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#include <common.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <asm/processor.h>
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extern void ft_qe_setup(void *blob);
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@ -33,6 +34,23 @@ DECLARE_GLOBAL_DATA_PTR;
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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immap_t *immr = (immap_t *)CFG_IMMR;
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int spridr = immr->sysconf.spridr;
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/*
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* delete crypto node if not on an E-processor
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* initial revisions of the MPC834xE/6xE have the original SEC 2.0.
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* EA revisions got the SEC uprevved to 2.4 but since the default device
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* tree contains SEC 2.0 properties we uprev them here.
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*/
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if (!IS_E_PROCESSOR(spridr))
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fdt_fixup_crypto_node(blob, 0);
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else if (IS_E_PROCESSOR(spridr) &&
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(SPR_FAMILY(spridr) == SPR_834X_FAMILY ||
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SPR_FAMILY(spridr) == SPR_836X_FAMILY) &&
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REVID_MAJOR(spridr) >= 2)
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fdt_fixup_crypto_node(blob, 0x0204);
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#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
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defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
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fdt_fixup_ethernet(blob, bd);
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@ -29,6 +29,7 @@
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#include <asm/processor.h>
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extern void ft_qe_setup(void *blob);
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#ifdef CONFIG_MP
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#include "mp.h"
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DECLARE_GLOBAL_DATA_PTR;
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@ -205,6 +206,10 @@ static inline void ft_fixup_cache(void *blob)
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void ft_cpu_setup(void *blob, bd_t *bd)
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{
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/* delete crypto node if not on an E-processor */
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if (!IS_E_PROCESSOR(get_svr()))
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fdt_fixup_crypto_node(blob, 0);
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#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
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defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
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fdt_fixup_ethernet(blob, bd);
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@ -885,6 +885,15 @@
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/* Some parts define SVR[0:23] as the SOC version */
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#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFF) /* SOC Version fields */
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/* whether MPC8xxxE (i.e. has SEC) */
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#if defined(CONFIG_MPC85xx)
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#define IS_E_PROCESSOR(svr) (svr & 0x80000)
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#else
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#if defined(CONFIG_MPC83XX)
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#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000))
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#endif
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#endif
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/*
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* SVR_SOC_VER() Version Values
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*/
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@ -56,6 +56,12 @@ void fdt_fixup_dr_usb(void *blob, bd_t *bd);
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static inline void fdt_fixup_dr_usb(void *blob, bd_t *bd) {}
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#endif /* CONFIG_HAS_FSL_DR_USB */
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC83XX)
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void fdt_fixup_crypto_node(void *blob, int sec_rev);
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#else
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static inline void fdt_fixup_crypto_node(void *blob, int sec_rev) {}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_board_setup(void *blob, bd_t *bd);
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void ft_cpu_setup(void *blob, bd_t *bd);
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@ -61,21 +61,26 @@
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#endif
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#define PARTID_NO_E(spridr) ((spridr & 0xFFFE0000) >> 16)
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#define IS_E_PROCESSOR(spridr) (!(spridr & 0x00010000)) /* has SEC */
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#define SPR_FAMILY(spridr) ((spridr & 0xFFF00000) >> 20)
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#define SPR_831X_FAMILY 0x80B
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#define SPR_8311 0x80B2
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#define SPR_8313 0x80B0
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#define SPR_8314 0x80B6
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#define SPR_8315 0x80B4
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#define SPR_832X_FAMILY 0x806
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#define SPR_8321 0x8066
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#define SPR_8323 0x8062
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#define SPR_834X_FAMILY 0x803
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#define SPR_8343 0x8036
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#define SPR_8347_TBGA_ 0x8032
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#define SPR_8347_PBGA_ 0x8034
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#define SPR_8349 0x8030
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#define SPR_836X_FAMILY 0x804
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#define SPR_8358_TBGA_ 0x804A
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#define SPR_8358_PBGA_ 0x804E
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#define SPR_8360 0x8048
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#define SPR_837X_FAMILY 0x80C
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#define SPR_8377 0x80C6
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#define SPR_8378 0x80C4
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#define SPR_8379 0x80C2
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