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net: jr2: Reset switch

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Make sure to reset the switch core at probe time.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
This commit is contained in:
Horatiu Vultur
2021-03-10 09:31:38 +01:00
committed by Daniel Schwierzeck
parent 842d049be2
commit 6b59304602
2 changed files with 19 additions and 3 deletions
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16
drivers/net/mscc_eswitch/jr2_switch.c
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@@ -235,7 +235,7 @@ static const char * const regs_names[] = {
"port36", "port37", "port38", "port39", "port40", "port41", "port42",
"port43", "port44", "port45", "port46", "port47",
"ana_ac", "ana_cl", "ana_l2", "asm", "hsio", "lrn",
"qfwd", "qs", "qsys", "rew",
"qfwd", "qs", "qsys", "rew", "gcb", "icpu",
};
#define REGS_NAMES_COUNT ARRAY_SIZE(regs_names) + 1
@@ -252,6 +252,8 @@ enum jr2_ctrl_regs {
QS,
QSYS,
REW,
GCB,
ICPU,
};
#define JR2_MIIM_BUS_COUNT 3
@@ -850,6 +852,7 @@ static int jr2_probe(struct udevice *dev)
struct mii_dev *bus;
struct ofnode_phandle_args phandle;
struct phy_device *phy;
u32 val;
if (!priv)
return -EINVAL;
@@ -865,6 +868,17 @@ static int jr2_probe(struct udevice *dev)
}
}
val = readl(priv->regs[ICPU] + ICPU_RESET);
val |= ICPU_RESET_CORE_RST_PROTECT;
writel(val, priv->regs[ICPU] + ICPU_RESET);
val = readl(priv->regs[GCB] + PERF_SOFT_RST);
val |= PERF_SOFT_RST_SOFT_SWC_RST;
writel(val, priv->regs[GCB] + PERF_SOFT_RST);
while (readl(priv->regs[GCB] + PERF_SOFT_RST) & PERF_SOFT_RST_SOFT_SWC_RST)
;
/* Initialize miim buses */
memset(&miim, 0x0, sizeof(struct mscc_miim_dev) * JR2_MIIM_BUS_COUNT);