siemens,am33x: add draco etamin board
In the draco CPU board family, etamin is a new variant with bigger flash and more RAM. Due to new flash that uses larger pages (4K) some changes are necessary because it impacts the MTD partition layout and the ubi mount parameters. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Signed-off-by: Heiko Schocher <hs@denx.de> [trini: Move BOOTDELAY into defconfig, just always be 3 now] Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Heiko Schocher
Tom Rini
@@ -83,8 +83,12 @@ int board_init(void)
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#ifdef CONFIG_FACTORYSET
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factoryset_read_eeprom(CONFIG_SYS_I2C_EEPROM_ADDR);
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#endif
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gpmc_init();
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#ifdef CONFIG_NAND_CS_INIT
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board_nand_cs_init();
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#endif
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#ifdef CONFIG_VIDEO
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board_video_init();
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#endif
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@@ -45,3 +45,19 @@ config SYS_CONFIG_NAME
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default "rastaban"
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endif
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if TARGET_ETAMIN
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config SYS_BOARD
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default "draco"
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config SYS_VENDOR
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default "siemens"
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config SYS_SOC
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default "am33xx"
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config SYS_CONFIG_NAME
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default "etamin"
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endif
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@@ -4,6 +4,7 @@ S: Maintained
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F: board/siemens/draco/
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F: include/configs/draco.h
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F: configs/draco_defconfig
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F: configs/etamin_defconfig
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F: include/configs/thuban.h
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F: configs/thuban_defconfig
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F: include/configs/rastaban.h
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@@ -24,6 +24,7 @@
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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@@ -33,6 +34,7 @@
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#include <watchdog.h>
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#include "board.h"
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#include "../common/factoryset.h"
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#include <nand.h>
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DECLARE_GLOBAL_DATA_PTR;
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@@ -40,6 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
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static struct draco_baseboard_id __attribute__((section(".data"))) settings;
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#if DDR_PLL_FREQ == 303
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#if !defined(CONFIG_TARGET_ETAMIN)
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/* Default@303MHz-i0 */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e35, 0x0080, 0x0000, 0x003A, 0x003F, 0x009F,
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@@ -48,6 +51,16 @@ const struct ddr3_data ddr3_default = {
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"default name @303MHz \0",
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"default marking \0",
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};
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#else
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/* etamin board */
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const struct ddr3_data ddr3_default = {
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0x33524444, 0x56312e36, 0x0080, 0x0000, 0x003A, 0x0010, 0x009F,
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0x0050, 0x0888A39B, 0x266D7FDA, 0x501F86AF, 0x00100206, 0x61A44BB2,
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0x0000093B, 0x0000018A,
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"test-etamin \0",
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"generic-8Gbit \0",
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};
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#endif
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#elif DDR_PLL_FREQ == 400
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/* Default@400MHz-i0 */
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const struct ddr3_data ddr3_default = {
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@@ -210,6 +223,7 @@ struct ctrl_ioregs draco_ddr3_ioregs = {
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draco_ddr3_emif_reg_data.emif_ddr_phy_ctlr_1 =
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settings.ddr3.emif_ddr_phy_ctlr_1;
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draco_ddr3_emif_reg_data.sdram_config = settings.ddr3.sdram_config;
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draco_ddr3_emif_reg_data.sdram_config2 = 0x08000000;
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draco_ddr3_emif_reg_data.ref_ctrl = settings.ddr3.ref_ctrl;
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draco_ddr3_data.datardsratio0 = settings.ddr3.dt0rdsratio0;
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@@ -251,6 +265,10 @@ int board_late_init(void)
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nand_curr_device = 0;
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omap_nand_switch_ecc(1, ecc_type);
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#ifdef CONFIG_TARGET_ETAMIN
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nand_curr_device = 1;
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omap_nand_switch_ecc(1, ecc_type);
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#endif
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#ifdef CONFIG_FACTORYSET
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/* Set ASN in environment*/
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if (factory_dat.asn[0] != 0) {
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@@ -326,7 +344,7 @@ int board_eth_init(bd_t *bis)
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}
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static int do_switch_reset(cmd_tbl_t *cmdtp, int flag, int argc,
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char *const argv[])
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char *const argv[])
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{
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/* Reset SMSC LAN9303 switch for default configuration */
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gpio_request(GPIO_LAN9303_NRST, "nRST");
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@@ -346,4 +364,23 @@ U_BOOT_CMD(
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#endif /* #if defined(CONFIG_DRIVER_TI_CPSW) */
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#endif /* #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) */
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#ifdef CONFIG_NAND_CS_INIT
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/* GPMC definitions for second nand cs1 */
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static const u32 gpmc_nand_config[] = {
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ETAMIN_NAND_GPMC_CONFIG1,
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ETAMIN_NAND_GPMC_CONFIG2,
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ETAMIN_NAND_GPMC_CONFIG3,
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ETAMIN_NAND_GPMC_CONFIG4,
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ETAMIN_NAND_GPMC_CONFIG5,
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ETAMIN_NAND_GPMC_CONFIG6,
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/*CONFIG7- computed as params */
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};
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static void board_nand_cs_init(void)
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{
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enable_gpmc_cs_config(gpmc_nand_config, &gpmc_cfg->cs[1],
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0x18000000, GPMC_SIZE_16M);
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}
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#endif
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#include "../common/board.c"
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@@ -51,6 +51,7 @@ static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_csn1), MODE(0) | PULLUDEN | PULLUP_EN}, /* NAND_CS1 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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@@ -68,7 +69,6 @@ static struct module_pin_mux gpios_pin_mux[] = {
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{OFFSET(mmc0_dat1), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y3 GPIO2_28*/
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{OFFSET(mmc0_dat2), MODE(7) | PULLUDDIS | RXACTIVE}, /* Y7 GPIO2_27*/
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/* Triacs initial HW Rev */
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{OFFSET(gpmc_csn1), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_30 Y0 */
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{OFFSET(gpmc_be1n), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_28 Y1 */
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{OFFSET(gpmc_csn2), MODE(7) | RXACTIVE | PULLUDDIS}, /* 1_31 Y2 */
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{OFFSET(lcd_data15), MODE(7) | RXACTIVE | PULLUDDIS}, /* 0_11 Y3 */
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