sh: ms7722: Remove the board
Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Vladimir Zapolskiy <vz@mleia.com> Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut
Marek Vasut
parent
ea349270e3
commit
6b371a7a4b
@ -21,10 +21,6 @@ choice
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prompt "Target select"
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optional
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config TARGET_MS7722SE
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bool "SolutionEngine 7722"
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select CPU_SH4
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config TARGET_MS7750SE
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bool "SolutionEngine 7750"
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select CPU_SH4
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@ -80,7 +76,6 @@ config SYS_CPU
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source "arch/sh/lib/Kconfig"
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source "board/alphaproject/ap_sh4a_4a/Kconfig"
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source "board/ms7722se/Kconfig"
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source "board/ms7750se/Kconfig"
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source "board/renesas/MigoR/Kconfig"
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source "board/renesas/ap325rxa/Kconfig"
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@ -1,9 +0,0 @@
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if TARGET_MS7722SE
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config SYS_BOARD
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default "ms7722se"
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config SYS_CONFIG_NAME
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default "ms7722se"
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endif
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@ -1,7 +0,0 @@
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MS7722SE BOARD
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M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
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M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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S: Maintained
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F: board/ms7722se/
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F: include/configs/ms7722se.h
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F: configs/ms7722se_defconfig
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@ -1,13 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2007
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# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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#
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# Copyright (C) 2007
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# Kenati Technologies, Inc.
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#
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# board/ms7722se/Makefile
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#
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obj-y := ms7722se.o
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extra-y += lowlevel_init.o
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@ -1,224 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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* board/ms7722se/lowlevel_init.S
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*/
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#include <config.h>
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#include <asm/processor.h>
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#include <asm/macro.h>
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/*
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* Board specific low level init code, called _very_ early in the
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* startup sequence. Relocation to SDRAM has not happened yet, no
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* stack is available, bss section has not been initialised, etc.
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*
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* (Note: As no stack is available, no subroutines can be called...).
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*/
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.global lowlevel_init
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.text
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.align 2
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lowlevel_init:
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/*
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* Cache Control Register
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* Instruction Cache Invalidate
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*/
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write32 CCR_A, CCR_D
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/*
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* Address of MMU Control Register
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* TI == TLB Invalidate bit
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*/
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write32 MMUCR_A, MMUCR_D
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/* Address of Power Control Register 0 */
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write32 MSTPCR0_A, MSTPCR0_D
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/* Address of Power Control Register 2 */
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write32 MSTPCR2_A, MSTPCR2_D
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write16 SBSCR_A, SBSCR_D
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write16 PSCR_A, PSCR_D
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/* 0xA4520004 (Watchdog Control / Status Register) */
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! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
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/* 0xA4520000 (Watchdog Count Register) */
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write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
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/* 0xA4520004 (Watchdog Control / Status Register) */
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write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
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/* 0xA4150000 Frequency control register */
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write32 FRQCR_A, FRQCR_D
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write32 CCR_A, CCR_D_2
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bsc_init:
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write16 PSELA_A, PSELA_D
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write16 DRVCR_A, DRVCR_D
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write16 PCCR_A, PCCR_D
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write16 PECR_A, PECR_D
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write16 PJCR_A, PJCR_D
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write16 PXCR_A, PXCR_D
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write32 CMNCR_A, CMNCR_D
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write32 CS0BCR_A, CS0BCR_D
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write32 CS2BCR_A, CS2BCR_D
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write32 CS4BCR_A, CS4BCR_D
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write32 CS5ABCR_A, CS5ABCR_D
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write32 CS5BBCR_A, CS5BBCR_D
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write32 CS6ABCR_A, CS6ABCR_D
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write32 CS0WCR_A, CS0WCR_D
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write32 CS2WCR_A, CS2WCR_D
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write32 CS4WCR_A, CS4WCR_D
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write32 CS5AWCR_A, CS5AWCR_D
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write32 CS5BWCR_A, CS5BWCR_D
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write32 CS6AWCR_A, CS6AWCR_D
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! SDRAM initialization
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write32 SDCR_A, SDCR_D
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write32 SDWCR_A, SDWCR_D
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write32 SDPCR_A, SDPCR_D
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write32 RTCOR_A, RTCOR_D
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write32 RTCSR_A, RTCSR_D
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write8 SDMR3_A, SDMR3_D
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! BL bit off (init = ON) (?!?)
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stc sr, r0 ! BL bit off(init=ON)
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mov.l SR_MASK_D, r1
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and r1, r0
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ldc r0, sr
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rts
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mov #0, r0
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.align 2
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CCR_A: .long CCR
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MMUCR_A: .long MMUCR
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MSTPCR0_A: .long MSTPCR0
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MSTPCR2_A: .long MSTPCR2
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SBSCR_A: .long SBSCR
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PSCR_A: .long PSCR
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RWTCSR_A: .long RWTCSR
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RWTCNT_A: .long RWTCNT
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FRQCR_A: .long FRQCR
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CCR_D: .long 0x00000800
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CCR_D_2: .long 0x00000103
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MMUCR_D: .long 0x00000004
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MSTPCR0_D: .long 0x00001001
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MSTPCR2_D: .long 0xffffffff
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FRQCR_D: .long 0x07022538
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PSELA_A: .long 0xa405014E
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PSELA_D: .word 0x0A10
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.align 2
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DRVCR_A: .long 0xa405018A
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DRVCR_D: .word 0x0554
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.align 2
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PCCR_A: .long 0xa4050104
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PCCR_D: .word 0x8800
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.align 2
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PECR_A: .long 0xa4050108
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PECR_D: .word 0x0000
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.align 2
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PJCR_A: .long 0xa4050110
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PJCR_D: .word 0x1000
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.align 2
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PXCR_A: .long 0xa4050148
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PXCR_D: .word 0x0AAA
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.align 2
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CMNCR_A: .long CMNCR
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CMNCR_D: .long 0x00000013
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CS0BCR_A: .long CS0BCR ! Flash bank 1
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CS0BCR_D: .long 0x24920400
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CS2BCR_A: .long CS2BCR ! SRAM
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CS2BCR_D: .long 0x24920400
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CS4BCR_A: .long CS4BCR ! FPGA, PCMCIA, USB, ext slot
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CS4BCR_D: .long 0x24920400
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CS5ABCR_A: .long CS5ABCR ! Ext slot
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CS5ABCR_D: .long 0x24920400
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CS5BBCR_A: .long CS5BBCR ! USB controller
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CS5BBCR_D: .long 0x24920400
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CS6ABCR_A: .long CS6ABCR ! Ethernet
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CS6ABCR_D: .long 0x24920400
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CS0WCR_A: .long CS0WCR
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CS0WCR_D: .long 0x00000300
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CS2WCR_A: .long CS2WCR
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CS2WCR_D: .long 0x00000300
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CS4WCR_A: .long CS4WCR
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CS4WCR_D: .long 0x00000300
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CS5AWCR_A: .long CS5AWCR
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CS5AWCR_D: .long 0x00000300
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CS5BWCR_A: .long CS5BWCR
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CS5BWCR_D: .long 0x00000300
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CS6AWCR_A: .long CS6AWCR
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CS6AWCR_D: .long 0x00000300
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SDCR_A: .long SBSC_SDCR
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SDCR_D: .long 0x00020809
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SDWCR_A: .long SBSC_SDWCR
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SDWCR_D: .long 0x00164d0d
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SDPCR_A: .long SBSC_SDPCR
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SDPCR_D: .long 0x00000087
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RTCOR_A: .long SBSC_RTCOR
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RTCOR_D: .long 0xA55A0034
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RTCSR_A: .long SBSC_RTCSR
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RTCSR_D: .long 0xA55A0010
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SDMR3_A: .long 0xFE500180
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SDMR3_D: .long 0x0
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.align 1
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SBSCR_D: .word 0x0040
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PSCR_D: .word 0x0000
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RWTCSR_D_1: .word 0xA507
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RWTCSR_D_2: .word 0xA507
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RWTCNT_D: .word 0x5A00
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.align 2
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SR_MASK_D: .long 0xEFFFFF0F
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@ -1,47 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2007,2008
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* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*
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* Copyright (C) 2007
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* Kenati Technologies, Inc.
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*
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* board/ms7722se/ms7722se.c
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*/
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#include <common.h>
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#include <netdev.h>
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#include <asm/io.h>
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#include <asm/processor.h>
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#define LED_BASE 0xB0800000
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int checkboard(void)
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{
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puts("BOARD: Hitachi UL MS7722SE\n");
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return 0;
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}
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int board_init(void)
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{
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/* Setup PTXMD[1:0] for /CS6A */
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outw(inw(PXCR) & ~0xf000, PXCR);
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return 0;
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}
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void led_set_state(unsigned short value)
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{
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writew(value & 0xFF, LED_BASE);
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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int rc = 0;
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#ifdef CONFIG_SMC91111
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rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
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#endif
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return rc;
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}
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#endif
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@ -1,33 +0,0 @@
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CONFIG_SH=y
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CONFIG_SYS_TEXT_BASE=0x8FFC0000
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CONFIG_TARGET_MS7722SE=y
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CONFIG_BOOTDELAY=3
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CONFIG_USE_BOOTARGS=y
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CONFIG_BOOTARGS="console=ttySC0,115200 root=1f01"
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CONFIG_VERSION_VARIABLE=y
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# CONFIG_CMDLINE_EDITING is not set
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# CONFIG_AUTO_COMPLETE is not set
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# CONFIG_CMD_BDI is not set
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# CONFIG_CMD_CONSOLE is not set
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# CONFIG_CMD_BOOTD is not set
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# CONFIG_CMD_RUN is not set
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EDITENV is not set
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# CONFIG_CMD_ENV_EXISTS is not set
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# CONFIG_CMD_LOADB is not set
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# CONFIG_CMD_LOADS is not set
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CONFIG_CMD_SDRAM=y
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# CONFIG_CMD_ECHO is not set
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# CONFIG_CMD_ITEST is not set
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# CONFIG_CMD_SOURCE is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_CMD_PING=y
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# CONFIG_CMD_MISC is not set
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CONFIG_CMD_JFFS2=y
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CONFIG_ENV_IS_IN_FLASH=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_SCIF_CONSOLE=y
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CONFIG_USE_PRIVATE_LIBGCC=y
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@ -1,83 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Configuation settings for the Hitachi Solution Engine 7722
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*
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* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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*/
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#ifndef __MS7722SE_H
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#define __MS7722SE_H
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#define CONFIG_CPU_SH7722 1
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#define CONFIG_DISPLAY_BOARDINFO
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#undef CONFIG_SHOW_BOOT_PROGRESS
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/* SMC9111 */
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#define CONFIG_SMC91111
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#define CONFIG_SMC91111_BASE (0xB8000000)
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/* MEMORY */
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#define MS7722SE_SDRAM_BASE (0x8C000000)
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#define MS7722SE_FLASH_BASE_1 (0xA0000000)
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#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
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#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
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#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
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/* SCIF */
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#define CONFIG_CONS_SCIF0 1
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#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
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#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
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#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
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#define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE)
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#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
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#define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
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in Flash (NOT run time address in SDRAM) ?!? */
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#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
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#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
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#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
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/* FLASH */
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#undef CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
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#define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
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#define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each
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Flash chip */
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/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
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#define CONFIG_SYS_MAX_FLASH_BANKS 2
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
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CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
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}
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#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
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#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
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#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
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#undef CONFIG_SYS_DIRECT_FLASH_TFTP
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#define CONFIG_ENV_OVERWRITE 1
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#define CONFIG_ENV_SECT_SIZE (8 * 1024)
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#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
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#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
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#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
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#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
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/* Board Clock */
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#define CONFIG_SYS_CLK_FREQ 33333333
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#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
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#endif /* __MS7722SE_H */
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