Merge branch '2022-01-18-platform-updates'
- cubieboard7 MMC support, AST2600 MAC support
This commit is contained in:
Tom Rini
commit
6a685753ce
@ -163,6 +163,74 @@
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pinctrl-0 = <&pinctrl_i2c9_default>;
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};
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&mdio0 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mdio1 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mdio2 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy2: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mdio3 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy3: ethernet-phy@0 {
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reg = <0>;
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};
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};
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&mac0 {
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status = "okay";
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phy-mode = "rgmii-rxid";
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phy-handle = <ðphy0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii1_default>;
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};
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&mac1 {
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status = "okay";
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phy-mode = "rgmii-rxid";
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phy-handle = <ðphy1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii2_default>;
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};
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&mac2 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <ðphy2>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii3_default>;
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};
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&mac3 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <ðphy3>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rgmii4_default>;
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};
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&scu {
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mac0-clk-delay = <0x1d 0x1c
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0x10 0x17
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@ -210,13 +210,49 @@
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
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};
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mdio: ethernet@1e650000 {
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compatible = "aspeed,aspeed-mdio";
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reg = <0x1e650000 0x40>;
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mdio: bus@1e650000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x1e650000 0x100>;
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mdio0: mdio@0 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0 0x8>;
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resets = <&rst ASPEED_RESET_MII>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio1_default>;
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status = "disabled";
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};
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mdio1: mdio@8 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x8 0x8>;
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resets = <&rst ASPEED_RESET_MII>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio2_default>;
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status = "disabled";
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};
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mdio2: mdio@10 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x10 0x8>;
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resets = <&rst ASPEED_RESET_MII>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio3_default>;
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status = "disabled";
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};
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mdio3: mdio@18 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x18 0x8>;
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resets = <&rst ASPEED_RESET_MII>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio4_default>;
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status = "disabled";
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};
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};
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mac0: ftgmac@1e660000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
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@ -19,6 +19,16 @@
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status = "okay";
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};
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mmc0: mmc@e0210000 {
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compatible = "actions,s700-mmc", "actions,owl-mmc";
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reg = <0x0 0xe0210000 0x0 0x4000>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cmu CLK_SD0>;
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dmas = <&dma 2>;
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dma-names = "mmc";
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bus-width = <4>;
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status = "okay";
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};
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};
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};
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@ -5,6 +5,7 @@
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#include <dt-bindings/clock/actions,s700-cmu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/owl-s700-powergate.h>
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#include <dt-bindings/reset/actions,s700-reset.h>
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/ {
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@ -231,7 +232,7 @@
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pinctrl: pinctrl@e01b0000 {
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compatible = "actions,s700-pinctrl";
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reg = <0x0 0xe01b0000 0x0 0x1000>;
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reg = <0x0 0xe01b0000 0x0 0x100>;
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clocks = <&cmu CLK_GPIO>;
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gpio-controller;
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gpio-ranges = <&pinctrl 0 0 136>;
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@ -244,5 +245,19 @@
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<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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};
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dma: dma-controller@e0230000 {
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compatible = "actions,s700-dma";
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reg = <0x0 0xe0230000 0x0 0x1000>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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dma-channels = <10>;
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dma-requests = <44>;
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clocks = <&cmu CLK_DMAC>;
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power-domains = <&sps S700_PD_DMA>;
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};
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};
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};
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@ -16,3 +16,6 @@ CONFIG_PHY_REALTEK=y
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CONFIG_RTL8201F_PHY_S700_RMII_TIMINGS=y
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CONFIG_ETH_DESIGNWARE=y
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CONFIG_ETH_DESIGNWARE_S700=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_OWL=y
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CONFIG_CMD_MMC=y
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@ -64,7 +64,9 @@ CONFIG_MMC_SDHCI=y
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CONFIG_MMC_SDHCI_ASPEED=y
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CONFIG_PHY_REALTEK=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_FTGMAC100=y
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CONFIG_ASPEED_MDIO=y
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CONFIG_PHY=y
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CONFIG_PINCTRL=y
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CONFIG_RAM=y
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@ -19,10 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
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#define CLKIN_25M 25000000UL
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/* MAC Clock Delay settings */
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#define MAC12_DEF_DELAY_1G 0x0041b75d
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#define MAC12_DEF_DELAY_100M 0x00417410
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#define MAC12_DEF_DELAY_10M 0x00417410
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#define MAC34_DEF_DELAY_1G 0x0010438a
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#define MAC12_DEF_DELAY_1G 0x0028a410
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#define MAC12_DEF_DELAY_100M 0x00410410
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#define MAC12_DEF_DELAY_10M 0x00410410
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#define MAC34_DEF_DELAY_1G 0x00104208
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#define MAC34_DEF_DELAY_100M 0x00104208
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#define MAC34_DEF_DELAY_10M 0x00104208
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@ -20,6 +20,8 @@
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#define CMU_DEVCLKEN0_SD0 BIT(22)
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void owl_clk_init(struct owl_clk_priv *priv)
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{
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u32 bus_clk = 0, core_pll, dev_pll;
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@ -92,6 +94,9 @@ int owl_clk_enable(struct clk *clk)
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setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
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setbits_le32(priv->base + CMU_ETHERNETPLL, 5);
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break;
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case CLK_SD0:
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setbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0);
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break;
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default:
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return -EINVAL;
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}
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@ -121,6 +126,9 @@ int owl_clk_disable(struct clk *clk)
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case CLK_ETHERNET:
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clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_ETH);
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break;
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case CLK_SD0:
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clrbits_le32(priv->base + CMU_DEVCLKEN0, CMU_DEVCLKEN0_SD0);
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break;
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default:
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return -EINVAL;
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}
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@ -128,6 +136,95 @@ int owl_clk_disable(struct clk *clk)
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return 0;
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}
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static ulong get_sd_parent_rate(struct owl_clk_priv *priv, u32 dev_index)
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{
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ulong rate;
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u32 reg;
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reg = readl(priv->base + (CMU_SD0CLK + dev_index * 0x4));
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/* Clock output of DEV/NAND_PLL
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* Range: 48M ~ 756M
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* Frequency= PLLCLK * 6
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*/
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if (reg & 0x200)
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rate = readl(priv->base + CMU_NANDPLL) & 0x7f;
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else
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rate = readl(priv->base + CMU_DEVPLL) & 0x7f;
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rate *= 6000000;
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return rate;
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}
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static ulong owl_get_sd_clk_rate(struct owl_clk_priv *priv, int sd_index)
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{
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uint div, val;
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ulong parent_rate = get_sd_parent_rate(priv, sd_index);
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val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4));
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div = (val & 0x1f) + 1;
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return (parent_rate / div);
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}
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static ulong owl_set_sd_clk_rate(struct owl_clk_priv *priv, ulong rate,
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int sd_index)
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{
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uint div, val;
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ulong parent_rate = get_sd_parent_rate(priv, sd_index);
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if (rate == 0)
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return rate;
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div = (parent_rate / rate);
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val = readl(priv->base + (CMU_SD0CLK + sd_index * 0x4));
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/* Bits 4..0 is used to program div value and bit 8 to enable
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* divide by 128 circuit
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*/
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val &= ~0x11f;
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if (div >= 128) {
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div = div / 128;
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val |= 0x100; /* enable divide by 128 circuit */
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}
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val |= ((div - 1) & 0x1f);
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writel(val, priv->base + (CMU_SD0CLK + sd_index * 0x4));
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return owl_get_sd_clk_rate(priv, 0);
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}
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static ulong owl_clk_get_rate(struct clk *clk)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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ulong rate;
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switch (clk->id) {
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case CLK_SD0:
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rate = owl_get_sd_clk_rate(priv, 0);
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break;
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default:
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return -ENOENT;
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}
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return rate;
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}
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static ulong owl_clk_set_rate(struct clk *clk, ulong rate)
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{
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struct owl_clk_priv *priv = dev_get_priv(clk->dev);
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ulong new_rate;
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switch (clk->id) {
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case CLK_SD0:
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new_rate = owl_set_sd_clk_rate(priv, rate, 0);
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break;
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default:
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return -ENOENT;
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}
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|
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return new_rate;
|
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}
|
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|
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static int owl_clk_probe(struct udevice *dev)
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{
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struct owl_clk_priv *priv = dev_get_priv(dev);
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@ -145,6 +242,8 @@ static int owl_clk_probe(struct udevice *dev)
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static const struct clk_ops owl_clk_ops = {
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.enable = owl_clk_enable,
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.disable = owl_clk_disable,
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.get_rate = owl_clk_get_rate,
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.set_rate = owl_clk_set_rate,
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};
|
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|
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static const struct udevice_id owl_clk_ids[] = {
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||||
|
||||
@ -295,6 +295,13 @@ config MMC_MXC
|
||||
|
||||
If unsure, say N.
|
||||
|
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config MMC_OWL
|
||||
bool "Actions OWL Multimedia Card Interface support"
|
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depends on ARCH_OWL && DM_MMC && BLK
|
||||
help
|
||||
This selects the OWL SD/MMC host controller found on board
|
||||
based on Actions S700/S900 SoC.
|
||||
|
||||
config MMC_MXS
|
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bool "Freescale MXS Multimedia Card Interface support"
|
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depends on MX23 || MX28 || MX6 || MX7
|
||||
|
||||
@ -39,6 +39,7 @@ obj-$(CONFIG_MMC_OMAP_HS) += omap_hsmmc.o
|
||||
obj-$(CONFIG_MMC_MXC) += mxcmmc.o
|
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obj-$(CONFIG_MMC_MXS) += mxsmmc.o
|
||||
obj-$(CONFIG_MMC_OCTEONTX) += octeontx_hsmmc.o
|
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obj-$(CONFIG_MMC_OWL) += owl_mmc.o
|
||||
obj-$(CONFIG_MMC_PCI) += pci_mmc.o
|
||||
obj-$(CONFIG_PXA_MMC_GENERIC) += pxa_mmc_gen.o
|
||||
obj-$(CONFIG_$(SPL_TPL_)SUPPORT_EMMC_RPMB) += rpmb.o
|
||||
|
||||
408
drivers/mmc/owl_mmc.c
Normal file
408
drivers/mmc/owl_mmc.c
Normal file
@ -0,0 +1,408 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright (C) 2020 Amit Singh Tomar <amittomer25@gmail.com>
|
||||
*
|
||||
* Driver for SD/MMC controller present on Actions Semi S700/S900 SoC, based
|
||||
* on Linux Driver "drivers/mmc/host/owl-mmc.c".
|
||||
*
|
||||
* Though, there is a bit (BSEL, BUS or DMA Special Channel Selection) that
|
||||
* controls the data transfer from SDx_DAT register either using CPU AHB Bus
|
||||
* or DMA channel, but seems like, it only works correctly using external DMA
|
||||
* channel, and those special bits used in this driver is picked from vendor
|
||||
* source exclusively for MMC/SD.
|
||||
*/
|
||||
#include <common.h>
|
||||
#include <clk.h>
|
||||
#include <cpu_func.h>
|
||||
#include <dm.h>
|
||||
#include <errno.h>
|
||||
#include <log.h>
|
||||
#include <mmc.h>
|
||||
#include <asm/io.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/iopoll.h>
|
||||
|
||||
/*
|
||||
* SDC registers
|
||||
*/
|
||||
#define OWL_REG_SD_EN 0x0000
|
||||
#define OWL_REG_SD_CTL 0x0004
|
||||
#define OWL_REG_SD_STATE 0x0008
|
||||
#define OWL_REG_SD_CMD 0x000c
|
||||
#define OWL_REG_SD_ARG 0x0010
|
||||
#define OWL_REG_SD_RSPBUF0 0x0014
|
||||
#define OWL_REG_SD_RSPBUF1 0x0018
|
||||
#define OWL_REG_SD_RSPBUF2 0x001c
|
||||
#define OWL_REG_SD_RSPBUF3 0x0020
|
||||
#define OWL_REG_SD_RSPBUF4 0x0024
|
||||
#define OWL_REG_SD_DAT 0x0028
|
||||
#define OWL_REG_SD_BLK_SIZE 0x002c
|
||||
#define OWL_REG_SD_BLK_NUM 0x0030
|
||||
#define OWL_REG_SD_BUF_SIZE 0x0034
|
||||
|
||||
/* SD_EN Bits */
|
||||
#define OWL_SD_EN_RANE BIT(31)
|
||||
#define OWL_SD_EN_RESE BIT(10)
|
||||
#define OWL_SD_ENABLE BIT(7)
|
||||
#define OWL_SD_EN_BSEL BIT(6)
|
||||
#define OWL_SD_EN_DATAWID(x) (((x) & 0x3) << 0)
|
||||
#define OWL_SD_EN_DATAWID_MASK 0x03
|
||||
|
||||
/* SD_CTL Bits */
|
||||
#define OWL_SD_CTL_TOUTEN BIT(31)
|
||||
#define OWL_SD_CTL_DELAY_MSK GENMASK(23, 16)
|
||||
#define OWL_SD_CTL_RDELAY(x) (((x) & 0xf) << 20)
|
||||
#define OWL_SD_CTL_WDELAY(x) (((x) & 0xf) << 16)
|
||||
#define OWL_SD_CTL_TS BIT(7)
|
||||
#define OWL_SD_CTL_LBE BIT(6)
|
||||
#define OWL_SD_CTL_TM(x) (((x) & 0xf) << 0)
|
||||
|
||||
#define OWL_SD_DELAY_LOW_CLK 0x0f
|
||||
#define OWL_SD_DELAY_MID_CLK 0x0a
|
||||
#define OWL_SD_RDELAY_HIGH 0x08
|
||||
#define OWL_SD_WDELAY_HIGH 0x09
|
||||
|
||||
/* SD_STATE Bits */
|
||||
#define OWL_SD_STATE_DAT0S BIT(7)
|
||||
#define OWL_SD_STATE_CLNR BIT(4)
|
||||
#define OWL_SD_STATE_CRC7ER BIT(0)
|
||||
|
||||
#define OWL_MMC_OCR (MMC_VDD_32_33 | MMC_VDD_33_34 | \
|
||||
MMC_VDD_165_195)
|
||||
|
||||
#define DATA_TRANSFER_TIMEOUT 3000000
|
||||
#define DMA_TRANSFER_TIMEOUT 5000000
|
||||
|
||||
/*
|
||||
* Simple DMA transfer operations defines for MMC/SD card
|
||||
*/
|
||||
#define SD_DMA_CHANNEL(base, channel) ((base) + 0x100 + 0x100 * (channel))
|
||||
|
||||
#define DMA_MODE 0x0000
|
||||
#define DMA_SOURCE 0x0004
|
||||
#define DMA_DESTINATION 0x0008
|
||||
#define DMA_FRAME_LEN 0x000C
|
||||
#define DMA_FRAME_CNT 0x0010
|
||||
#define DMA_START 0x0024
|
||||
|
||||
/* DMAx_MODE */
|
||||
#define DMA_MODE_ST(x) (((x) & 0x3) << 8)
|
||||
#define DMA_MODE_ST_DEV DMA_MODE_ST(0)
|
||||
#define DMA_MODE_DT(x) (((x) & 0x3) << 10)
|
||||
#define DMA_MODE_DT_DCU DMA_MODE_DT(2)
|
||||
#define DMA_MODE_SAM(x) (((x) & 0x3) << 16)
|
||||
#define DMA_MODE_SAM_CONST DMA_MODE_SAM(0)
|
||||
#define DMA_MODE_DAM(x) (((x) & 0x3) << 18)
|
||||
#define DMA_MODE_DAM_INC DMA_MODE_DAM(1)
|
||||
|
||||
#define DMA_ENABLE 0x1
|
||||
|
||||
struct owl_mmc_plat {
|
||||
struct mmc_config cfg;
|
||||
struct mmc mmc;
|
||||
};
|
||||
|
||||
struct owl_mmc_priv {
|
||||
void *reg_base;
|
||||
void *dma_channel;
|
||||
struct clk clk;
|
||||
unsigned int clock; /* Current clock */
|
||||
unsigned int dma_drq; /* Trigger Source */
|
||||
};
|
||||
|
||||
static void owl_dma_config(struct owl_mmc_priv *priv, unsigned int src,
|
||||
unsigned int dst, unsigned int len)
|
||||
{
|
||||
unsigned int mode = priv->dma_drq;
|
||||
|
||||
/* Set Source and Destination adderess mode */
|
||||
mode |= (DMA_MODE_ST_DEV | DMA_MODE_SAM_CONST | DMA_MODE_DT_DCU |
|
||||
DMA_MODE_DAM_INC);
|
||||
|
||||
writel(mode, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_MODE);
|
||||
writel(src, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_SOURCE);
|
||||
writel(dst, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_DESTINATION);
|
||||
writel(len, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_LEN);
|
||||
writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_FRAME_CNT);
|
||||
}
|
||||
|
||||
static void owl_mmc_prepare_data(struct owl_mmc_priv *priv,
|
||||
struct mmc_data *data)
|
||||
{
|
||||
unsigned int total;
|
||||
u32 buf = 0;
|
||||
|
||||
setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_EN_BSEL);
|
||||
|
||||
writel(data->blocks, priv->reg_base + OWL_REG_SD_BLK_NUM);
|
||||
writel(data->blocksize, priv->reg_base + OWL_REG_SD_BLK_SIZE);
|
||||
total = data->blocksize * data->blocks;
|
||||
|
||||
if (total < 512)
|
||||
writel(total, priv->reg_base + OWL_REG_SD_BUF_SIZE);
|
||||
else
|
||||
writel(512, priv->reg_base + OWL_REG_SD_BUF_SIZE);
|
||||
|
||||
/* DMA STOP */
|
||||
writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
|
||||
|
||||
if (data) {
|
||||
if (data->flags == MMC_DATA_READ) {
|
||||
buf = (ulong) (data->dest);
|
||||
owl_dma_config(priv, (ulong) priv->reg_base +
|
||||
OWL_REG_SD_DAT, buf, total);
|
||||
invalidate_dcache_range(buf, buf + total);
|
||||
} else {
|
||||
buf = (ulong) (data->src);
|
||||
owl_dma_config(priv, buf, (ulong) priv->reg_base +
|
||||
OWL_REG_SD_DAT, total);
|
||||
flush_dcache_range(buf, buf + total);
|
||||
}
|
||||
/* DMA START */
|
||||
writel(0x1, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
|
||||
}
|
||||
}
|
||||
|
||||
static int owl_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
|
||||
struct mmc_data *data)
|
||||
{
|
||||
struct owl_mmc_priv *priv = dev_get_priv(dev);
|
||||
unsigned int cmd_rsp_mask, mode, reg;
|
||||
int ret;
|
||||
|
||||
setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_ENABLE);
|
||||
|
||||
/* setup response */
|
||||
mode = 0;
|
||||
if (cmd->resp_type != MMC_RSP_NONE)
|
||||
cmd_rsp_mask = OWL_SD_STATE_CLNR | OWL_SD_STATE_CRC7ER;
|
||||
if (cmd->resp_type == MMC_RSP_R1) {
|
||||
if (data) {
|
||||
if (data->flags == MMC_DATA_READ)
|
||||
mode |= OWL_SD_CTL_TM(4);
|
||||
else
|
||||
mode |= OWL_SD_CTL_TM(5);
|
||||
} else
|
||||
mode |= OWL_SD_CTL_TM(1);
|
||||
} else if (cmd->resp_type == MMC_RSP_R2) {
|
||||
mode = OWL_SD_CTL_TM(2);
|
||||
} else if (cmd->resp_type == MMC_RSP_R1b) {
|
||||
mode = OWL_SD_CTL_TM(3);
|
||||
} else if (cmd->resp_type == MMC_RSP_R3) {
|
||||
cmd_rsp_mask = OWL_SD_STATE_CLNR;
|
||||
mode = OWL_SD_CTL_TM(1);
|
||||
}
|
||||
|
||||
mode |= (readl(priv->reg_base + OWL_REG_SD_CTL) & (0xff << 16));
|
||||
|
||||
/* setup command */
|
||||
writel(cmd->cmdidx, priv->reg_base + OWL_REG_SD_CMD);
|
||||
writel(cmd->cmdarg, priv->reg_base + OWL_REG_SD_ARG);
|
||||
|
||||
/* Set LBE to send clk at the end of last read block */
|
||||
if (data)
|
||||
mode |= (OWL_SD_CTL_TS | OWL_SD_CTL_LBE | 0xE4000000);
|
||||
else
|
||||
mode |= OWL_SD_CTL_TS;
|
||||
|
||||
if (data)
|
||||
owl_mmc_prepare_data(priv, data);
|
||||
|
||||
/* Start transfer */
|
||||
writel(mode, priv->reg_base + OWL_REG_SD_CTL);
|
||||
|
||||
ret = readl_poll_timeout(priv->reg_base + OWL_REG_SD_CTL, reg,
|
||||
!(reg & OWL_SD_CTL_TS), DATA_TRANSFER_TIMEOUT);
|
||||
|
||||
if (ret == -ETIMEDOUT) {
|
||||
debug("error: transferred data timeout\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
reg = readl(priv->reg_base + OWL_REG_SD_STATE) & cmd_rsp_mask;
|
||||
if (cmd->resp_type & MMC_RSP_PRESENT) {
|
||||
if (reg & OWL_SD_STATE_CLNR) {
|
||||
printf("Error CMD_NO_RSP\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (reg & OWL_SD_STATE_CRC7ER) {
|
||||
printf("Error CMD_RSP_CRC\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (cmd->resp_type & MMC_RSP_136) {
|
||||
cmd->response[3] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
|
||||
cmd->response[2] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
|
||||
cmd->response[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF2);
|
||||
cmd->response[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF3);
|
||||
} else {
|
||||
u32 rsp[2];
|
||||
|
||||
rsp[0] = readl(priv->reg_base + OWL_REG_SD_RSPBUF0);
|
||||
rsp[1] = readl(priv->reg_base + OWL_REG_SD_RSPBUF1);
|
||||
cmd->response[0] = rsp[1] << 24 | rsp[0] >> 8;
|
||||
cmd->response[1] = rsp[1] >> 8;
|
||||
}
|
||||
}
|
||||
|
||||
if (data) {
|
||||
ret = readl_poll_timeout(SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START,
|
||||
reg, !(reg & DMA_ENABLE), DMA_TRANSFER_TIMEOUT);
|
||||
|
||||
if (ret == -ETIMEDOUT) {
|
||||
debug("error: DMA transfer timeout\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* DMA STOP */
|
||||
writel(0x0, SD_DMA_CHANNEL(priv->dma_channel, 0) + DMA_START);
|
||||
/* Transmission STOP */
|
||||
while (readl(priv->reg_base + OWL_REG_SD_CTL) & OWL_SD_CTL_TS)
|
||||
clrbits_le32(priv->reg_base + OWL_REG_SD_CTL,
|
||||
OWL_SD_CTL_TS);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_mmc_clk_set(struct owl_mmc_priv *priv, int rate)
|
||||
{
|
||||
u32 reg, wdelay, rdelay;
|
||||
|
||||
reg = readl(priv->reg_base + OWL_REG_SD_CTL);
|
||||
reg &= ~OWL_SD_CTL_DELAY_MSK;
|
||||
|
||||
/* Set RDELAY and WDELAY based on the clock */
|
||||
if (rate <= 1000000)
|
||||
rdelay = wdelay = OWL_SD_DELAY_LOW_CLK;
|
||||
else if ((rate > 1000000) && (rate <= 26000000))
|
||||
rdelay = wdelay = OWL_SD_DELAY_MID_CLK;
|
||||
else if ((rate > 26000000) && (rate <= 52000000)) {
|
||||
rdelay = OWL_SD_RDELAY_HIGH;
|
||||
wdelay = OWL_SD_WDELAY_HIGH;
|
||||
} else {
|
||||
debug("SD clock rate not supported\n");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
writel(reg | OWL_SD_CTL_RDELAY(rdelay) | OWL_SD_CTL_WDELAY(wdelay),
|
||||
priv->reg_base + OWL_REG_SD_CTL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_mmc_set_ios(struct udevice *dev)
|
||||
{
|
||||
struct owl_mmc_priv *priv = dev_get_priv(dev);
|
||||
struct owl_mmc_plat *plat = dev_get_plat(dev);
|
||||
struct mmc *mmc = &plat->mmc;
|
||||
u32 reg, ret;
|
||||
|
||||
if (mmc->clock != priv->clock) {
|
||||
priv->clock = mmc->clock;
|
||||
ret = owl_mmc_clk_set(priv, mmc->clock);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
|
||||
ret = clk_set_rate(&priv->clk, mmc->clock);
|
||||
if (IS_ERR_VALUE(ret))
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (mmc->clk_disable)
|
||||
ret = clk_disable(&priv->clk);
|
||||
else
|
||||
ret = clk_enable(&priv->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Set the Bus width */
|
||||
reg = readl(priv->reg_base + OWL_REG_SD_EN);
|
||||
reg &= ~OWL_SD_EN_DATAWID_MASK;
|
||||
if (mmc->bus_width == 8)
|
||||
reg |= OWL_SD_EN_DATAWID(2);
|
||||
else if (mmc->bus_width == 4)
|
||||
reg |= OWL_SD_EN_DATAWID(1);
|
||||
|
||||
writel(reg, priv->reg_base + OWL_REG_SD_EN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct dm_mmc_ops owl_mmc_ops = {
|
||||
.send_cmd = owl_mmc_send_cmd,
|
||||
.set_ios = owl_mmc_set_ios,
|
||||
};
|
||||
|
||||
static int owl_mmc_probe(struct udevice *dev)
|
||||
{
|
||||
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
|
||||
struct owl_mmc_plat *plat = dev_get_plat(dev);
|
||||
struct owl_mmc_priv *priv = dev_get_priv(dev);
|
||||
struct mmc_config *cfg = &plat->cfg;
|
||||
struct ofnode_phandle_args args;
|
||||
int ret;
|
||||
fdt_addr_t addr;
|
||||
|
||||
cfg->name = dev->name;
|
||||
cfg->voltages = OWL_MMC_OCR;
|
||||
cfg->f_min = 400000;
|
||||
cfg->f_max = 52000000;
|
||||
cfg->b_max = 512;
|
||||
cfg->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz;
|
||||
|
||||
ret = mmc_of_parse(dev, cfg);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
addr = dev_read_addr(dev);
|
||||
if (addr == FDT_ADDR_T_NONE)
|
||||
return -EINVAL;
|
||||
|
||||
priv->reg_base = (void *)addr;
|
||||
|
||||
ret = dev_read_phandle_with_args(dev, "dmas", "#dma-cells", 0, 0,
|
||||
&args);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
priv->dma_channel = (void *)ofnode_get_addr(args.node);
|
||||
priv->dma_drq = args.args[0];
|
||||
|
||||
ret = clk_get_by_index(dev, 0, &priv->clk);
|
||||
if (ret) {
|
||||
debug("clk_get_by_index() failed: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
upriv->mmc = &plat->mmc;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int owl_mmc_bind(struct udevice *dev)
|
||||
{
|
||||
struct owl_mmc_plat *plat = dev_get_plat(dev);
|
||||
|
||||
return mmc_bind(dev, &plat->mmc, &plat->cfg);
|
||||
}
|
||||
|
||||
static const struct udevice_id owl_mmc_ids[] = {
|
||||
{ .compatible = "actions,s700-mmc" },
|
||||
{ .compatible = "actions,owl-mmc" },
|
||||
{ }
|
||||
};
|
||||
|
||||
U_BOOT_DRIVER(owl_mmc_drv) = {
|
||||
.name = "owl_mmc",
|
||||
.id = UCLASS_MMC,
|
||||
.of_match = owl_mmc_ids,
|
||||
.bind = owl_mmc_bind,
|
||||
.probe = owl_mmc_probe,
|
||||
.ops = &owl_mmc_ops,
|
||||
.plat_auto = sizeof(struct owl_mmc_plat),
|
||||
.priv_auto = sizeof(struct owl_mmc_priv),
|
||||
};
|
||||
@ -220,7 +220,11 @@ static int ftgmac100_phy_init(struct udevice *dev)
|
||||
struct phy_device *phydev;
|
||||
int ret;
|
||||
|
||||
if (IS_ENABLED(CONFIG_DM_MDIO))
|
||||
phydev = dm_eth_phy_connect(dev);
|
||||
else
|
||||
phydev = phy_connect(priv->bus, priv->phy_addr, dev, priv->phy_mode);
|
||||
|
||||
if (!phydev)
|
||||
return -ENODEV;
|
||||
|
||||
@ -589,11 +593,17 @@ static int ftgmac100_probe(struct udevice *dev)
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
/*
|
||||
* If DM MDIO is enabled, the MDIO bus will be initialized later in
|
||||
* dm_eth_phy_connect
|
||||
*/
|
||||
if (!IS_ENABLED(CONFIG_DM_MDIO)) {
|
||||
ret = ftgmac100_mdio_init(dev);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to initialize mdiobus: %d\n", ret);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
ret = ftgmac100_phy_init(dev);
|
||||
if (ret) {
|
||||
@ -634,6 +644,7 @@ static const struct eth_ops ftgmac100_ops = {
|
||||
static const struct udevice_id ftgmac100_ids[] = {
|
||||
{ .compatible = "faraday,ftgmac100", .data = FTGMAC100_MODEL_FARADAY },
|
||||
{ .compatible = "aspeed,ast2500-mac", .data = FTGMAC100_MODEL_ASPEED },
|
||||
{ .compatible = "aspeed,ast2600-mac", .data = FTGMAC100_MODEL_ASPEED },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
||||
19
include/dt-bindings/power/owl-s700-powergate.h
Normal file
19
include/dt-bindings/power/owl-s700-powergate.h
Normal file
@ -0,0 +1,19 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
||||
/*
|
||||
* Actions Semi S700 SPS
|
||||
*
|
||||
* Copyright (c) 2017 Andreas Färber
|
||||
*/
|
||||
#ifndef DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
|
||||
#define DT_BINDINGS_POWER_OWL_S700_POWERGATE_H
|
||||
|
||||
#define S700_PD_VDE 0
|
||||
#define S700_PD_VCE_SI 1
|
||||
#define S700_PD_USB2_1 2
|
||||
#define S700_PD_HDE 3
|
||||
#define S700_PD_DMA 4
|
||||
#define S700_PD_DS 5
|
||||
#define S700_PD_USB3 6
|
||||
#define S700_PD_USB2_0 7
|
||||
|
||||
#endif
|
||||
@ -126,8 +126,6 @@ int bb_miiphy_write(struct mii_dev *miidev, int addr, int devad, int reg,
|
||||
#define ESTATUS_1000XF 0x8000
|
||||
#define ESTATUS_1000XH 0x4000
|
||||
|
||||
#ifdef CONFIG_DM_MDIO
|
||||
|
||||
/**
|
||||
* struct mdio_perdev_priv - Per-device class data for MDIO DM
|
||||
*
|
||||
@ -185,10 +183,6 @@ struct phy_device *dm_mdio_phy_connect(struct udevice *mdiodev, int phyaddr,
|
||||
*/
|
||||
struct phy_device *dm_eth_phy_connect(struct udevice *ethdev);
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DM_MDIO_MUX
|
||||
|
||||
/* indicates none of the child buses is selected */
|
||||
#define MDIO_MUX_SELECT_NONE -1
|
||||
|
||||
@ -206,5 +200,3 @@ struct mdio_mux_ops {
|
||||
#define mdio_mux_get_ops(dev) ((struct mdio_mux_ops *)(dev)->driver->ops)
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user