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mx6: ddr: Do not access MMDC_P1_BASE_ADDR on i.MX6ULL

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i.MX6ULL also does not have a MMDC_P1_BASE_ADDR, so do not try to
access it.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <ssbabic@denx.de>
This commit is contained in:
Fabio Estevam 2018-01-01 22:51:45 -02:00 committed by Stefano Babic
parent 67b71df277
commit 6a2ccd64c3
1 changed files with 2 additions and 2 deletions
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4
arch/arm/mach-imx/mx6/ddr.c
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@ -908,7 +908,7 @@ void mx6sdl_dram_iocfg(unsigned width,
#define MR(val, ba, cmd, cs1) \
((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
#define MMDC1(entry, value) do { \
if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl()) \
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl()) \
mmdc1->entry = value; \
} while (0)
@ -1215,7 +1215,7 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo,
u16 mem_speed = ddr3_cfg->mem_speed;
mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
if (!is_mx6sx() && !is_mx6ul() && !is_mx6sl())
if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull() && !is_mx6sl())
mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
/* Limit mem_speed for MX6D/MX6Q */