ARM: dts: stm32mp15: alignment with v5.19
Device tree alignment with Linux kernel v5.19-rc1 - ARM: dts: stm32: Add alternate pinmux for ethernet0 pins - ARM: dts: stm32: Add alternate pinmux for mco2 pins - ARM: dts: stm32: fix pinctrl node name warnings (MPU soc) - ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group - dt-bindings: clock: add IDs for SCMI clocks on stm32mp15 - dt-bindings: reset: add IDs for SCMI reset domains on stm32mp15 - dt-bindings: clock: stm32mp15: rename CK_SCMI define - dt-bindings: reset: stm32mp15: rename RST_SCMI define - dt-bindings: reset: add MCU HOLD BOOT ID for SCMI reset domains on stm32mp15 - dt-bindings: clk: cleanup comments - ARM: dts: align SPI NOR node name with dtschema - ARM: dts: stm32: enable optee firmware and SCMI support on STM32MP15 - ARM: dts: stm32: Add SCMI version of STM32 boards (DK1/DK2/ED1/EV1) - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 + patch from stm32-dt-for-v5.19-fixes-2 - ARM: dts: stm32: move SCMI related nodes in a dedicated file for stm32mp15 - ARM: dts: stm32: fix pwr regulators references to use scmi - ARM: dts: stm32: use the correct clock source for CEC on stm32mp151 - ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board - ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI - ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15 Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
This commit is contained in:
Patrick Delaunay
parent
cb8edb996b
commit
69ef98b209
@ -379,6 +379,40 @@
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};
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};
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ethernet0_rmii_pins_c: rmii-2 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 1, AF11)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */
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<STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */
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<STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */
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bias-disable;
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};
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};
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ethernet0_rmii_sleep_pins_c: rmii-sleep-2 {
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pins1 {
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pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */
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<STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */
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<STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */
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<STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */
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<STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */
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<STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */
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<STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */
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<STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */
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<STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */
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};
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};
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fmc_pins_a: fmc-0 {
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pins1 {
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pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
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@ -889,6 +923,21 @@
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};
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};
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mco2_pins_a: mco2-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, AF1)>; /* MCO2 */
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bias-disable;
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drive-push-pull;
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slew-rate = <2>;
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};
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};
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mco2_sleep_pins_a: mco2-sleep-0 {
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pins {
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pinmux = <STM32_PINMUX('G', 2, ANALOG)>; /* MCO2 */
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};
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};
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m_can1_pins_a: m-can1-0 {
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pins1 {
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pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */
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@ -2331,4 +2380,19 @@
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bias-disable;
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};
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};
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spi1_pins_b: spi1-1 {
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pins1 {
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pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
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<STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
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bias-disable;
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drive-push-pull;
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slew-rate = <1>;
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};
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pins2 {
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pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
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bias-disable;
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};
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};
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};
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109
arch/arm/dts/stm32mp15-scmi.dtsi
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109
arch/arm/dts/stm32mp15-scmi.dtsi
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@ -0,0 +1,109 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/ {
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firmware {
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optee: optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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scmi: scmi {
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compatible = "linaro,scmi-optee";
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#address-cells = <1>;
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#size-cells = <0>;
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linaro,optee-channel-id = <0>;
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shmem = <&scmi_shm>;
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scmi_clk: protocol@14 {
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reg = <0x14>;
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#clock-cells = <1>;
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};
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scmi_reset: protocol@16 {
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reg = <0x16>;
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#reset-cells = <1>;
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};
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scmi_voltd: protocol@17 {
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reg = <0x17>;
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scmi_reguls: regulators {
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#address-cells = <1>;
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#size-cells = <0>;
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scmi_reg11: reg11@0 {
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reg = <0>;
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regulator-name = "reg11";
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regulator-min-microvolt = <1100000>;
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regulator-max-microvolt = <1100000>;
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};
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scmi_reg18: reg18@1 {
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voltd-name = "reg18";
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reg = <1>;
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regulator-name = "reg18";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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scmi_usb33: usb33@2 {
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reg = <2>;
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regulator-name = "usb33";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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};
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};
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};
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soc {
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scmi_sram: sram@2ffff000 {
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compatible = "mmio-sram";
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reg = <0x2ffff000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x2ffff000 0x1000>;
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scmi_shm: scmi-sram@0 {
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compatible = "arm,scmi-shmem";
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reg = <0 0x80>;
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};
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};
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};
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};
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®11 {
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status = "disabled";
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};
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®18 {
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status = "disabled";
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};
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&usb33 {
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status = "disabled";
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};
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&usbotg_hs {
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usb33d-supply = <&scmi_usb33>;
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};
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&usbphyc {
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vdda1v1-supply = <&scmi_reg11>;
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vdda1v8-supply = <&scmi_reg18>;
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};
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/delete-node/ &clk_hse;
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/delete-node/ &clk_hsi;
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/delete-node/ &clk_lse;
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/delete-node/ &clk_lsi;
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/delete-node/ &clk_csi;
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/delete-node/ ®11;
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/delete-node/ ®18;
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/delete-node/ &usb33;
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/delete-node/ &pwr_regulators;
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@ -583,7 +583,7 @@
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compatible = "st,stm32-cec";
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reg = <0x40016000 0x400>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rcc CEC_K>, <&clk_lse>;
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clocks = <&rcc CEC_K>, <&rcc CEC>;
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clock-names = "cec", "hdmi-cec";
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status = "disabled";
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};
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@ -1504,7 +1504,7 @@
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usbh_ohci: usb@5800c000 {
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compatible = "generic-ohci";
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reg = <0x5800c000 0x1000>;
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clocks = <&rcc USBH>, <&usbphyc>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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@ -1513,7 +1513,7 @@
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usbh_ehci: usb@5800d000 {
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compatible = "generic-ehci";
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reg = <0x5800d000 0x1000>;
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clocks = <&rcc USBH>;
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clocks = <&usbphyc>, <&rcc USBH>;
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resets = <&rcc USBH_R>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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companion = <&usbh_ohci>;
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@ -1656,7 +1656,7 @@
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* Break node order to solve dependency probe issue between
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* pinctrl and exti.
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*/
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pinctrl: pin-controller@50002000 {
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pinctrl: pinctrl@50002000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-pinctrl";
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@ -1788,7 +1788,7 @@
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};
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};
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pinctrl_z: pin-controller-z@54004000 {
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pinctrl_z: pinctrl@54004000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "st,stm32mp157-z-pinctrl";
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79
arch/arm/dts/stm32mp157a-dk1-scmi.dts
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79
arch/arm/dts/stm32mp157a-dk1-scmi.dts
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@ -0,0 +1,79 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include "stm32mp157a-dk1.dts"
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#include "stm32mp15-scmi.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157A-DK1 SCMI Discovery Board";
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compatible = "st,stm32mp157a-dk1-scmi", "st,stm32mp157a-dk1", "st,stm32mp157";
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reserved-memory {
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optee@de000000 {
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reg = <0xde000000 0x2000000>;
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no-map;
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};
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};
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};
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&cpu0 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cpu1 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&dsi {
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clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
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};
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&gpioz {
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clocks = <&scmi_clk CK_SCMI_GPIOZ>;
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};
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&hash1 {
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clocks = <&scmi_clk CK_SCMI_HASH1>;
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resets = <&scmi_reset RST_SCMI_HASH1>;
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};
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&i2c4 {
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clocks = <&scmi_clk CK_SCMI_I2C4>;
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resets = <&scmi_reset RST_SCMI_I2C4>;
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};
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&iwdg2 {
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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};
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&mdma1 {
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resets = <&scmi_reset RST_SCMI_MDMA>;
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};
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&mlahb {
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resets = <&scmi_reset RST_SCMI_MCU>;
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};
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&rcc {
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compatible = "st,stm32mp1-rcc-secure", "syscon";
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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&rng1 {
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clocks = <&scmi_clk CK_SCMI_RNG1>;
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resets = <&scmi_reset RST_SCMI_RNG1>;
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};
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&rtc {
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clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
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};
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85
arch/arm/dts/stm32mp157c-dk2-scmi.dts
Normal file
85
arch/arm/dts/stm32mp157c-dk2-scmi.dts
Normal file
@ -0,0 +1,85 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
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*/
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/dts-v1/;
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#include "stm32mp157c-dk2.dts"
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#include "stm32mp15-scmi.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157C-DK2 SCMI Discovery Board";
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compatible = "st,stm32mp157c-dk2-scmi", "st,stm32mp157c-dk2", "st,stm32mp157";
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reserved-memory {
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optee@de000000 {
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reg = <0xde000000 0x2000000>;
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no-map;
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};
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};
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};
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&cpu0 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cpu1 {
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clocks = <&scmi_clk CK_SCMI_MPU>;
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};
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&cryp1 {
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clocks = <&scmi_clk CK_SCMI_CRYP1>;
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resets = <&scmi_reset RST_SCMI_CRYP1>;
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};
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&dsi {
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phy-dsi-supply = <&scmi_reg18>;
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clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
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};
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&gpioz {
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clocks = <&scmi_clk CK_SCMI_GPIOZ>;
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};
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&hash1 {
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clocks = <&scmi_clk CK_SCMI_HASH1>;
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resets = <&scmi_reset RST_SCMI_HASH1>;
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};
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&i2c4 {
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clocks = <&scmi_clk CK_SCMI_I2C4>;
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resets = <&scmi_reset RST_SCMI_I2C4>;
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};
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&iwdg2 {
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clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
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};
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&mdma1 {
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resets = <&scmi_reset RST_SCMI_MDMA>;
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};
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&mlahb {
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resets = <&scmi_reset RST_SCMI_MCU>;
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};
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&rcc {
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compatible = "st,stm32mp1-rcc-secure", "syscon";
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clock-names = "hse", "hsi", "csi", "lse", "lsi";
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clocks = <&scmi_clk CK_SCMI_HSE>,
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<&scmi_clk CK_SCMI_HSI>,
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<&scmi_clk CK_SCMI_CSI>,
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<&scmi_clk CK_SCMI_LSE>,
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<&scmi_clk CK_SCMI_LSI>;
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};
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&rng1 {
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clocks = <&scmi_clk CK_SCMI_RNG1>;
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resets = <&scmi_reset RST_SCMI_RNG1>;
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};
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&rtc {
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clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
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};
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84
arch/arm/dts/stm32mp157c-ed1-scmi.dts
Normal file
84
arch/arm/dts/stm32mp157c-ed1-scmi.dts
Normal file
@ -0,0 +1,84 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
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/*
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* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
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* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
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*/
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/dts-v1/;
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#include "stm32mp157c-ed1.dts"
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#include "stm32mp15-scmi.dtsi"
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/ {
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model = "STMicroelectronics STM32MP157C-ED1 SCMI eval daughter";
|
||||
compatible = "st,stm32mp157c-ed1-scmi", "st,stm32mp157c-ed1", "st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@fe000000 {
|
||||
reg = <0xfe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&mlahb {
|
||||
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
90
arch/arm/dts/stm32mp157c-ev1-scmi.dts
Normal file
90
arch/arm/dts/stm32mp157c-ev1-scmi.dts
Normal file
@ -0,0 +1,90 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
|
||||
/*
|
||||
* Copyright (C) STMicroelectronics 2022 - All Rights Reserved
|
||||
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "stm32mp157c-ev1.dts"
|
||||
#include "stm32mp15-scmi.dtsi"
|
||||
|
||||
/ {
|
||||
model = "STMicroelectronics STM32MP157C-EV1 SCMI eval daughter on eval mother";
|
||||
compatible = "st,stm32mp157c-ev1-scmi", "st,stm32mp157c-ev1", "st,stm32mp157c-ed1",
|
||||
"st,stm32mp157";
|
||||
|
||||
reserved-memory {
|
||||
optee@fe000000 {
|
||||
reg = <0xfe000000 0x2000000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cpu1 {
|
||||
clocks = <&scmi_clk CK_SCMI_MPU>;
|
||||
};
|
||||
|
||||
&cryp1 {
|
||||
clocks = <&scmi_clk CK_SCMI_CRYP1>;
|
||||
resets = <&scmi_reset RST_SCMI_CRYP1>;
|
||||
};
|
||||
|
||||
&dsi {
|
||||
phy-dsi-supply = <&scmi_reg18>;
|
||||
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
|
||||
};
|
||||
|
||||
&gpioz {
|
||||
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
|
||||
};
|
||||
|
||||
&hash1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HASH1>;
|
||||
resets = <&scmi_reset RST_SCMI_HASH1>;
|
||||
};
|
||||
|
||||
&i2c4 {
|
||||
clocks = <&scmi_clk CK_SCMI_I2C4>;
|
||||
resets = <&scmi_reset RST_SCMI_I2C4>;
|
||||
};
|
||||
|
||||
&iwdg2 {
|
||||
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&m_can1 {
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
|
||||
};
|
||||
|
||||
&mdma1 {
|
||||
resets = <&scmi_reset RST_SCMI_MDMA>;
|
||||
};
|
||||
|
||||
&mlahb {
|
||||
resets = <&scmi_reset RST_SCMI_MCU>;
|
||||
};
|
||||
|
||||
&rcc {
|
||||
compatible = "st,stm32mp1-rcc-secure", "syscon";
|
||||
clock-names = "hse", "hsi", "csi", "lse", "lsi";
|
||||
clocks = <&scmi_clk CK_SCMI_HSE>,
|
||||
<&scmi_clk CK_SCMI_HSI>,
|
||||
<&scmi_clk CK_SCMI_CSI>,
|
||||
<&scmi_clk CK_SCMI_LSE>,
|
||||
<&scmi_clk CK_SCMI_LSI>;
|
||||
};
|
||||
|
||||
&rng1 {
|
||||
clocks = <&scmi_clk CK_SCMI_RNG1>;
|
||||
resets = <&scmi_reset RST_SCMI_RNG1>;
|
||||
};
|
||||
|
||||
&rtc {
|
||||
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
|
||||
};
|
||||
@ -262,7 +262,7 @@
|
||||
#size-cells = <0>;
|
||||
status = "okay";
|
||||
|
||||
flash0: mx66l51235l@0 {
|
||||
flash0: flash@0 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <0>;
|
||||
spi-rx-bus-width = <4>;
|
||||
@ -271,7 +271,7 @@
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
flash1: mx66l51235l@1 {
|
||||
flash1: flash@1 {
|
||||
compatible = "jedec,spi-nor";
|
||||
reg = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
|
||||
@ -7,10 +7,10 @@
|
||||
*/
|
||||
|
||||
/*
|
||||
* List of clocks wich are not derived from system clock (SYSCLOCK)
|
||||
* List of clocks which are not derived from system clock (SYSCLOCK)
|
||||
*
|
||||
* The index of these clocks is the secondary index of DT bindings
|
||||
* (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
|
||||
* (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
|
||||
*
|
||||
* e.g:
|
||||
<assigned-clocks = <&rcc 1 CLK_LSE>;
|
||||
|
||||
@ -248,4 +248,27 @@
|
||||
|
||||
#define STM32MP1_LAST_CLK 232
|
||||
|
||||
/* SCMI clock identifiers */
|
||||
#define CK_SCMI_HSE 0
|
||||
#define CK_SCMI_HSI 1
|
||||
#define CK_SCMI_CSI 2
|
||||
#define CK_SCMI_LSE 3
|
||||
#define CK_SCMI_LSI 4
|
||||
#define CK_SCMI_PLL2_Q 5
|
||||
#define CK_SCMI_PLL2_R 6
|
||||
#define CK_SCMI_MPU 7
|
||||
#define CK_SCMI_AXI 8
|
||||
#define CK_SCMI_BSEC 9
|
||||
#define CK_SCMI_CRYP1 10
|
||||
#define CK_SCMI_GPIOZ 11
|
||||
#define CK_SCMI_HASH1 12
|
||||
#define CK_SCMI_I2C4 13
|
||||
#define CK_SCMI_I2C6 14
|
||||
#define CK_SCMI_IWDG1 15
|
||||
#define CK_SCMI_RNG1 16
|
||||
#define CK_SCMI_RTC 17
|
||||
#define CK_SCMI_RTCAPB 18
|
||||
#define CK_SCMI_SPI6 19
|
||||
#define CK_SCMI_USART1 20
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */
|
||||
|
||||
@ -39,3 +39,4 @@
|
||||
#define STM32MP_PKG_AD 0x8
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
|
||||
|
||||
|
||||
@ -106,4 +106,18 @@
|
||||
#define GPIOJ_R 19785
|
||||
#define GPIOK_R 19786
|
||||
|
||||
/* SCMI reset domain identifiers */
|
||||
#define RST_SCMI_SPI6 0
|
||||
#define RST_SCMI_I2C4 1
|
||||
#define RST_SCMI_I2C6 2
|
||||
#define RST_SCMI_USART1 3
|
||||
#define RST_SCMI_STGEN 4
|
||||
#define RST_SCMI_GPIOZ 5
|
||||
#define RST_SCMI_CRYP1 6
|
||||
#define RST_SCMI_HASH1 7
|
||||
#define RST_SCMI_RNG1 8
|
||||
#define RST_SCMI_MDMA 9
|
||||
#define RST_SCMI_MCU 10
|
||||
#define RST_SCMI_MCU_HOLD_BOOT 11
|
||||
|
||||
#endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user