crypto/fsl: Correct 64-bit write when MMU disabled
When MMU is disabled, 64-bit write must be aligned at 64-bit boundary. Becaue the memory location is not guaranteed to be 64-bit aligned, the 64-bit write needs to be split into two 32-bit writes to avoid the alignment exception. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
4a97a0c91d
commit
69b6a796f7
@ -112,10 +112,9 @@ static inline void append_ptr(u32 *desc, dma_addr_t ptr)
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
/* The Position of low and high part of 64 bit address
|
||||
* will depend on the endianness of CAAM Block */
|
||||
union ptr_addr_t ptr_addr;
|
||||
ptr_addr.m_halfs.high = (u32)(ptr >> 32);
|
||||
ptr_addr.m_halfs.low = (u32)ptr;
|
||||
*offset = ptr_addr.m_whole;
|
||||
union ptr_addr_t *ptr_addr = (union ptr_addr_t *)offset;
|
||||
ptr_addr->m_halfs.high = (u32)(ptr >> 32);
|
||||
ptr_addr->m_halfs.low = (u32)ptr;
|
||||
#else
|
||||
*offset = ptr;
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user