leandrof/u-boot
1
0
Fork 1
Code Issues Pull Requests Packages Projects Releases Wiki Activity

* Patches by Udi Finkelstein, 2 June 2003:

Browse Source 
- Added support for custom keyboards, initialized by defining a
    board-specific drv_keyboard_init as well as defining CONFIG_KEYBOARD .
  - Added support for the RBC823 board.
  - cpu/mpc8xx/lcd.c now automatically calculates the
    Horizontal Pixel Count field.

* Fix alignment problem in BOOTP (dhcp_leasetime option)
  [pointed out by Nicolas Lacressonnire, 2 Jun 2003]

* Patch by Mark Rakes, 14 May 2003:
  add support for Intel e1000 gig cards.

* Patch by Nye Liu, 3 Jun 2003:
  fix critical typo in MAMR definition (include/mpc8xx.h)

* Fix requirement to align U-Boot image on 16 kB boundaries on PPC.

* Patch by Klaus Heydeck, 2 Jun 2003
  Minor changes for KUP4K configuration
This commit is contained in:
wdenk
2003-06-03 23:54:09 +00:00
parent 7a8e9bed17
commit 682011ff69
39 changed files with 6968 additions and 426 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
board/kup4k/flash.c
View File

@@ -172,6 +172,9 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
value = value|(value<<16);
switch (value) {
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
@@ -191,6 +194,16 @@ static ulong flash_get_size (vu_long *addr, flash_info_t *info)
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
case AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00200000;
break; /* => 2 MB */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */

461
board/kup4k/kup4k.c
View File

@@ -54,10 +54,7 @@ const uint sdram_table[] =
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04,
0xEEAEFC04,
0x11ADFC04,
0xEFBBBC00,
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
@@ -68,57 +65,37 @@ const uint sdram_table[] =
* sequence, which is executed by a RUN command.
*
*/
0x1FF77C35,
0xEFEABC34,
0x1FB57C35, /* last */
0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04,
0xEEAEFC04,
0x10ADFC04,
0xF0AFFC00,
0xF0AFFC00,
0xF1AFFC00,
0xEFBBBC00,
0x1FF77C47, /* last */
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F27FC04,
0xEEAEBC00,
0x01B93C04,
0x1FF77C47, /* last */
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04,
0xEEAEBC00,
0x10AD7C00,
0xF0AFFC00,
0xF0AFFC00,
0xE1BBBC04,
0x1FF77C47, /* last */
_NOT_USED_,
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF5FC84,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC04,
0xFFFFFC84,
0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
@@ -146,89 +123,96 @@ int checkboard (void)
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0 = 0;
long int size_b1 = 0;
long int size_b2 = 0;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0 = 0;
long int size_b1 = 0;
long int size_b2 = 0;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR;
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_mar = 0x00000088;
memctl->memc_mar = 0x00000088;
/*
* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
/* memctl->memc_or1 = CFG_OR1_PRELIM; */
/* memctl->memc_br1 = CFG_BR1_PRELIM; */
/*
* Map controller banks 1 and 2 to the SDRAM banks 2 and 3 at
* preliminary addresses - these have to be modified after the
* SDRAM size has been determined.
*/
/* memctl->memc_or1 = CFG_OR1_PRELIM; */
/* memctl->memc_br1 = CFG_BR1_PRELIM; */
/* memctl->memc_or2 = CFG_OR2_PRELIM; */
/* memctl->memc_br2 = CFG_BR2_PRELIM; */
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
udelay (200);
/* perform SDRAM initializsation sequence */
/* perform SDRAM initializsation sequence */
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
udelay(1);
memctl->memc_mcr = 0x80002105; /* SDRAM bank 0 */
udelay (1);
memctl->memc_mcr = 0x80002830; /* SDRAM bank 0 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80002106; /* SDRAM bank 0 - RUN MRS Pattern from loc 6 */
udelay (1);
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
udelay(1);
memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
udelay(1);
memctl->memc_mcr = 0x80004105; /* SDRAM bank 1 */
udelay (1);
memctl->memc_mcr = 0x80004830; /* SDRAM bank 1 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80004106; /* SDRAM bank 1 - RUN MRS Pattern from loc 6 */
udelay (1);
memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
udelay(1);
memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
udelay(1);
memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
udelay(1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
size_b0 = 0x00800000;
size_b1 = 0x00800000;
size_b2 = 0x00800000;
memctl->memc_mcr = 0x80006105; /* SDRAM bank 2 */
udelay (1);
memctl->memc_mcr = 0x80006830; /* SDRAM bank 2 - execute twice */
udelay (1);
memctl->memc_mcr = 0x80006106; /* SDRAM bank 2 - RUN MRS Pattern from loc 6 */
udelay (1);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
#if 0 /* 3 x 8MB */
size_b0 = 0x00800000;
size_b1 = 0x00800000;
size_b2 = 0x00800000;
memctl->memc_mptpr = CFG_MPTPR;
udelay(1000);
udelay (1000);
memctl->memc_or1 = 0xFF800A00;
memctl->memc_br1 = 0x00000081;
memctl->memc_or2 = 0xFF000A00;
memctl->memc_br2 = 0x00800081;
memctl->memc_or2 = 0xFF000A00;
memctl->memc_br2 = 0x00800081;
memctl->memc_or3 = 0xFE000A00;
memctl->memc_br3 = 0x01000081;
#else /* 3 x 16 MB */
size_b0 = 0x01000000;
size_b1 = 0x01000000;
size_b2 = 0x01000000;
memctl->memc_mptpr = CFG_MPTPR;
udelay (1000);
memctl->memc_or1 = 0xFF000A00;
memctl->memc_br1 = 0x00000081;
memctl->memc_or2 = 0xFE000A00;
memctl->memc_br2 = 0x01000081;
memctl->memc_or3 = 0xFC000A00;
memctl->memc_br3 = 0x02000081;
#endif
udelay(10000);
udelay (10000);
return (size_b0 + size_b1 + size_b2);
return (size_b0 + size_b1 + size_b2);
}
/* ------------------------------------------------------------------------- */
@@ -241,46 +225,47 @@ long int initdram (int board_type)
* - short between data lines
*/
#if 0
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
static long int dram_size (long int mamr_value, long int *base,
long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
ulong cnt, val;
ulong save[32]; /* to make test non-destructive */
unsigned char i = 0;
memctl->memc_mamr = mamr_value;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
for (cnt = maxsize / sizeof (long); cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
save[i++] = *addr;
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize/sizeof(long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof(long));
save[i++] = *addr;
*addr = ~cnt;
}
}
return (maxsize);
/* write 0 to base address */
addr = base;
save[i] = *addr;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
*addr = save[i];
return (0);
}
for (cnt = 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
*addr = save[--i];
if (val != (~cnt)) {
return (cnt * sizeof (long));
}
}
return (maxsize);
}
#endif
@@ -289,155 +274,175 @@ int misc_init_r (void)
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_STATUS_LED
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
#endif
#ifdef CONFIG_KUP4K_LOGO
bd_t *bd = gd->bd;
lcd_logo(bd);
#endif /* CONFIG_KUP4K_LOGO */
lcd_logo (bd);
#endif /* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED
/* Configure PA8 as output port */
immap->im_ioport.iop_padir |= 0x80;
immap->im_ioport.iop_paodr |= 0x80;
immap->im_ioport.iop_papar &= ~0x80;
immap->im_ioport.iop_padat |= 0x80; /* turn it off */
immap->im_ioport.iop_padat |= 0x80; /* turn it off */
#endif
return(0);
return (0);
}
#ifdef CONFIG_KUP4K_LOGO
void lcd_logo(bd_t *bd){
FB_INFO_S1D13xxx fb_info;
S1D_INDEX s1dReg;
S1D_VALUE s1dValue;
volatile immap_t *immr = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl;
#define PB_LCD_PWM ((uint)0x00004000) /* PB 17 */
void lcd_logo (bd_t * bd)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
FB_INFO_S1D13xxx fb_info;
S1D_INDEX s1dReg;
S1D_VALUE s1dValue;
volatile immap_t *immr = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl;
ushort i;
uchar *fb;
int rs, gs, bs;
int r = 8, g = 8, b = 4;
int r1,g1,b1;
int rs, gs, bs;
int r = 8, g = 8, b = 4;
int r1, g1, b1;
immr->im_cpm.cp_pbpar &= ~PB_LCD_PWM;
immr->im_cpm.cp_pbodr &= ~PB_LCD_PWM;
immr->im_cpm.cp_pbdat &= ~PB_LCD_PWM; /* set to 0 = enabled */
immr->im_cpm.cp_pbdir |= PB_LCD_PWM;
/*----------------------------------------------------------------------------- */
/**/
/**/
/* Initialize the chip and the frame buffer driver. */
/**/
/**/
/*----------------------------------------------------------------------------- */
memctl = &immr->im_memctl;
memctl = &immr->im_memctl;
/* memctl->memc_or5 = 0xFFC007F0; / * 4 MB 17 WS or externel TA */
/* memctl->memc_br5 = 0x80000801; / * Start at 0x80000000 */
memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
memctl->memc_or5 = 0xFFC00708; /* 4 MB 17 WS or externel TA */
memctl->memc_br5 = 0x80080801; /* Start at 0x80080000 */
fb_info.VmemAddr = (unsigned char*)(S1D_PHYSICAL_VMEM_ADDR);
fb_info.RegAddr = (unsigned char*)(S1D_PHYSICAL_REG_ADDR);
fb_info.VmemAddr = (unsigned char *) (S1D_PHYSICAL_VMEM_ADDR);
fb_info.RegAddr = (unsigned char *) (S1D_PHYSICAL_REG_ADDR);
if ((((S1D_VALUE*)fb_info.RegAddr)[0] != 0x28) || (((S1D_VALUE*)fb_info.RegAddr)[1] != 0x14))
{
printf("Warning:LCD Controller S1D13706 not found\n");
return;
}
if ((((S1D_VALUE *) fb_info.RegAddr)[0] != 0x28)
|| (((S1D_VALUE *) fb_info.RegAddr)[1] != 0x14)) {
printf ("Warning:LCD Controller S1D13706 not found\n");
return;
}
/* init controller */
for (i = 0; i < sizeof(aS1DRegs)/sizeof(aS1DRegs[0]); i++)
{
s1dReg = aS1DRegs[i].Index;
s1dValue = aS1DRegs[i].Value;
/* init controller */
for (i = 0; i < sizeof (aS1DRegs) / sizeof (aS1DRegs[0]); i++) {
s1dReg = aS1DRegs[i].Index;
s1dValue = aS1DRegs[i].Value;
/* printf("sid1 Index: %02x Register: %02x Wert: %02x\n",i, aS1DRegs[i].Index, aS1DRegs[i].Value); */
((S1D_VALUE*)fb_info.RegAddr)[s1dReg/sizeof(S1D_VALUE)] = s1dValue;
}
((S1D_VALUE *) fb_info.RegAddr)[s1dReg / sizeof (S1D_VALUE)] =
s1dValue;
}
#undef MONOCHROME
#ifdef MONOCHROME
switch(bd->bi_busfreq){
switch (bd->bi_busfreq) {
#if 0
case 24000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x28;
break;
case 32000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x33;
break;
case 24000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x28;
break;
case 32000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x33;
break;
#endif
case 40000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x40;
break;
case 48000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x4C;
break;
default:
printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
case 64000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x69;
break;
case 40000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x40;
break;
case 48000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x4C;
break;
default:
printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
bd->bi_busfreq);
case 64000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x69;
break;
}
((S1D_VALUE*)fb_info.RegAddr)[0x10] = 0x00;
((S1D_VALUE *) fb_info.RegAddr)[0x10] = 0x00;
#else
switch(bd->bi_busfreq){
switch (bd->bi_busfreq) {
#if 0
case 24000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
break;
case 32000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
break;
case 24000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
break;
case 32000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
break;
#endif
case 40000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x41;
break;
case 48000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x22;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x34;
break;
default:
printf("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",bd->bi_busfreq);
case 64000000:
((S1D_VALUE*)fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE*)fb_info.RegAddr)[0x12] = 0x66;
break;
case 40000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x41;
break;
case 48000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x22;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x34;
break;
default:
printf ("KUP4K S1D1: unknown busfrequency: %ld assuming 64 MHz\n",
bd->bi_busfreq);
case 64000000:
((S1D_VALUE *) fb_info.RegAddr)[0x05] = 0x32;
((S1D_VALUE *) fb_info.RegAddr)[0x12] = 0x66;
break;
}
#endif
/* create and set colormap */
rs = 256 / (r - 1);
gs = 256 / (g - 1);
bs = 256 / (b - 1);
for(i=0;i<256;i++){
r1=(rs * ((i / (g * b)) % r)) * 255;
g1=(gs * ((i / b) % g)) * 255;
b1=(bs * ((i) % b)) * 255;
/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
S1D_WRITE_PALETTE(fb_info.RegAddr,i,(r1>>4),(g1>>4),(b1>>4));
}
/* copy bitmap */
fb = (char *) (fb_info.VmemAddr);
memcpy (fb, (uchar *)CONFIG_KUP4K_LOGO, 320 * 240);
/* create and set colormap */
rs = 256 / (r - 1);
gs = 256 / (g - 1);
bs = 256 / (b - 1);
for (i = 0; i < 256; i++) {
r1 = (rs * ((i / (g * b)) % r)) * 255;
g1 = (gs * ((i / b) % g)) * 255;
b1 = (bs * ((i) % b)) * 255;
/* printf("%d %04x %04x %04x\n",i,r1>>4,g1>>4,b1>>4); */
S1D_WRITE_PALETTE (fb_info.RegAddr, i, (r1 >> 4), (g1 >> 4),
(b1 >> 4));
}
/* copy bitmap */
fb = (char *) (fb_info.VmemAddr);
memcpy (fb, (uchar *) CONFIG_KUP4K_LOGO, 320 * 240);
}
#endif /* CONFIG_KUP4K_LOGO */
#endif /* CONFIG_KUP4K_LOGO */
#ifdef CONFIG_IDE_LED
void ide_led (uchar led, uchar status)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile immap_t *immap = (immap_t *) CFG_IMMR;
/* We have one led for both pcmcia slots */
if (status) { /* led on */
if (status) { /* led on */
immap->im_ioport.iop_padat &= ~0x80;
} else {
immap->im_ioport.iop_padat |= 0x80;

114
board/kup4k/s1d13706.h
View File

@@ -50,66 +50,64 @@ typedef struct
static S1D_REGS aS1DRegs[] =
{
{0x04,0x10}, /* BUSCLK MEMCLK Config Register */
{0x04,0x10}, /* BUSCLK MEMCLK Config Register */
#if 0
{0x05,0x32}, /* PCLK Config Register */
{0x05,0x32}, /* PCLK Config Register */
#endif
{0x10,0xD0}, /* PANEL Type Register */
{0x11,0x00}, /* MOD Rate Register */
{0x10,0xD0}, /* PANEL Type Register */
{0x11,0x00}, /* MOD Rate Register */
#if 0
{0x12,0x34}, /* Horizontal Total Register */
{0x12,0x34}, /* Horizontal Total Register */
#endif
{0x14,0x27}, /* Horizontal Display Period Register */
{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
{0x18,0xF0}, /* Vertical Total Register 0 */
{0x19,0x00}, /* Vertical Total Register 1 */
{0x1C,0xEF}, /* Vertical Display Period Register 0 */
{0x1D,0x00}, /* Vertical Display Period Register 1 */
{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
{0x20,0x87}, /* Horizontal Sync Pulse Width Register */
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
{0x24,0x80}, /* Vertical Sync Pulse Width Register */
{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
{0x70,0x83}, /* Display Mode Register */
{0x71,0x00}, /* Special Effects Register */
{0x74,0x00}, /* Main Window Display Start Address Register 0 */
{0x75,0x00}, /* Main Window Display Start Address Register 1 */
{0x76,0x00}, /* Main Window Display Start Address Register 2 */
{0x78,0x50}, /* Main Window Address Offset Register 0 */
{0x79,0x00}, /* Main Window Address Offset Register 1 */
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
{0x80,0x50}, /* Sub Window Address Offset Register 0 */
{0x81,0x00}, /* Sub Window Address Offset Register 1 */
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */
{0xA0,0x00}, /* Power Save Config Register */
{0xA1,0x00}, /* CPU Access Control Register */
{0xA2,0x00}, /* Software Reset Register */
{0xA3,0x00}, /* BIG Endian Support Register */
{0xA4,0x00}, /* Scratch Pad Register 0 */
{0xA5,0x00}, /* Scratch Pad Register 1 */
{0xA8,0x01}, /* GPIO Config Register 0 */
{0xA9,0x80}, /* GPIO Config Register 1 */
{0xAC,0x01}, /* GPIO Status Control Register 0 */
{0xAD,0x00}, /* GPIO Status Control Register 1 */
{0xB0,0x00}, /* PWM CV Clock Control Register */
{0xB1,0x00}, /* PWM CV Clock Config Register */
{0xB2,0x00}, /* CV Clock Burst Length Register */
{0xB3,0x00}, /* PWM Clock Duty Cycle Register */
{0xAD,0x80}, /* reset seq */
{0x70,0x03}, /* */
{0x14,0x27}, /* Horizontal Display Period Register */
{0x16,0x00}, /* Horizontal Display Period Start Pos Register 0 */
{0x17,0x00}, /* Horizontal Display Period Start Pos Register 1 */
{0x18,0xF0}, /* Vertical Total Register 0 */
{0x19,0x00}, /* Vertical Total Register 1 */
{0x1C,0xEF}, /* Vertical Display Period Register 0 */
{0x1D,0x00}, /* Vertical Display Period Register 1 */
{0x1E,0x00}, /* Vertical Display Period Start Pos Register 0 */
{0x1F,0x00}, /* Vertical Display Period Start Pos Register 1 */
{0x20,0x87}, /* Horizontal Sync Pulse Width Register */
{0x22,0x00}, /* Horizontal Sync Pulse Start Pos Register 0 */
{0x23,0x00}, /* Horizontal Sync Pulse Start Pos Register 1 */
{0x24,0x80}, /* Vertical Sync Pulse Width Register */
{0x26,0x01}, /* Vertical Sync Pulse Start Pos Register 0 */
{0x27,0x00}, /* Vertical Sync Pulse Start Pos Register 1 */
{0x70,0x83}, /* Display Mode Register */
{0x71,0x00}, /* Special Effects Register */
{0x74,0x00}, /* Main Window Display Start Address Register 0 */
{0x75,0x00}, /* Main Window Display Start Address Register 1 */
{0x76,0x00}, /* Main Window Display Start Address Register 2 */
{0x78,0x50}, /* Main Window Address Offset Register 0 */
{0x79,0x00}, /* Main Window Address Offset Register 1 */
{0x7C,0x00}, /* Sub Window Display Start Address Register 0 */
{0x7D,0x00}, /* Sub Window Display Start Address Register 1 */
{0x7E,0x00}, /* Sub Window Display Start Address Register 2 */
{0x80,0x50}, /* Sub Window Address Offset Register 0 */
{0x81,0x00}, /* Sub Window Address Offset Register 1 */
{0x84,0x00}, /* Sub Window X Start Pos Register 0 */
{0x85,0x00}, /* Sub Window X Start Pos Register 1 */
{0x88,0x00}, /* Sub Window Y Start Pos Register 0 */
{0x89,0x00}, /* Sub Window Y Start Pos Register 1 */
{0x8C,0x4F}, /* Sub Window X End Pos Register 0 */
{0x8D,0x00}, /* Sub Window X End Pos Register 1 */
{0x90,0xEF}, /* Sub Window Y End Pos Register 0 */
{0x91,0x00}, /* Sub Window Y End Pos Register 1 */
{0xA0,0x00}, /* Power Save Config Register */
{0xA1,0x00}, /* CPU Access Control Register */
{0xA2,0x00}, /* Software Reset Register */
{0xA3,0x00}, /* BIG Endian Support Register */
{0xA4,0x00}, /* Scratch Pad Register 0 */
{0xA5,0x00}, /* Scratch Pad Register 1 */
{0xA8,0x01}, /* GPIO Config Register 0 */
{0xA9,0x80}, /* GPIO Config Register 1 */
{0xAC,0x01}, /* GPIO Status Control Register 0 */
{0xAD,0x00}, /* GPIO Status Control Register 1 */
{0xB0,0x10}, /* PWM CV Clock Control Register */
{0xB1,0x80}, /* PWM CV Clock Config Register */
{0xB2,0x00}, /* CV Clock Burst Length Register */
{0xB3,0xA0}, /* PWM Clock Duty Cycle Register */
{0xAD,0x80}, /* reset seq */
{0x70,0x03}, /* */
};

40
board/rbc823/Makefile Normal file
View File

@@ -0,0 +1,40 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o kbd.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $^
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################

28
board/rbc823/config.mk Normal file
View File

@@ -0,0 +1,28 @@
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# RBC823 boards
#
TEXT_BASE = 0xFFF00000

470
board/rbc823/flash.c Normal file
View File

@@ -0,0 +1,470 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <mpc8xx.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info);
static int write_word (flash_info_t *info, ulong dest, ulong data);
static void flash_get_offsets (ulong base, flash_info_t *info);
/*-----------------------------------------------------------------------
*/
unsigned long flash_init (void)
{
unsigned long size_b0, size_b1;
int i;
/* Init: no FLASHes known */
for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
flash_info[i].flash_id = FLASH_UNKNOWN;
/* Detect size */
size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
/* Setup offsets */
flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE+monitor_flash_len-1,
&flash_info[0]);
#endif
size_b1 = 0 ;
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
return (size_b0 + size_b1);
}
/*-----------------------------------------------------------------------
* Fix this to support variable sector sizes
*/
static void flash_get_offsets (ulong base, flash_info_t *info)
{
int i;
/* set up sector start address table */
if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
/* set sector offsets for bottom boot block type */
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
}
}
/*-----------------------------------------------------------------------
*/
void flash_print_info (flash_info_t *info)
{
int i;
if (info->flash_id == FLASH_UNKNOWN)
{
puts ("missing or unknown FLASH type\n");
return;
}
switch (info->flash_id & FLASH_VENDMASK)
{
case FLASH_MAN_AMD: printf ("AMD "); break;
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_BM: printf ("BRIGHT MICRO "); break;
default: printf ("Unknown Vendor "); break;
}
switch (info->flash_id & FLASH_TYPEMASK)
{
case FLASH_AM040: printf ("29F040 or 29LV040 (4 Mbit, uniform sectors)\n");
break;
case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
break;
case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n");
break;
case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n");
break;
case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n");
break;
case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n");
break;
case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n");
break;
case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n");
break;
case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n");
break;
default: printf ("Unknown Chip Type\n");
break;
}
if (info->size >> 20) {
printf (" Size: %ld MB in %d Sectors\n",
info->size >> 20,
info->sector_count);
} else {
printf (" Size: %ld KB in %d Sectors\n",
info->size >> 10,
info->sector_count);
}
puts (" Sector Start Addresses:");
for (i=0; i<info->sector_count; ++i)
{
if ((i % 5) == 0)
{
puts ("\n ");
}
printf (" %08lX%s",
info->start[i],
info->protect[i] ? " (RO)" : " ");
}
putc ('\n');
return;
}
/*-----------------------------------------------------------------------
*/
/*
* The following code cannot be run from FLASH!
*/
static ulong flash_get_size (vu_long *addr, flash_info_t *info)
{
short i;
volatile unsigned char *caddr;
char value;
caddr = (volatile unsigned char *)addr ;
/* Write auto select command: read Manufacturer ID */
#if 0
printf("Base address is: %08x\n", caddr);
#endif
caddr[0x0555] = 0xAA;
caddr[0x02AA] = 0x55;
caddr[0x0555] = 0x90;
value = caddr[0];
#if 0
printf("Manufact ID: %02x\n", value);
#endif
switch (value)
{
case 0x01:
case AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD;
break;
case FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ;
break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
info->size = 0;
break;
}
value = caddr[1]; /* device ID */
#if 0
printf("Device ID: %02x\n", value);
#endif
switch (value)
{
case AMD_ID_LV040B:
info->flash_id += FLASH_AM040;
info->sector_count = 8;
info->size = 0x00080000;
break; /* => 512Kb */
default:
info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */
}
flash_get_offsets ((ulong)addr, &flash_info[0]);
/* check for protected sectors */
for (i = 0; i < info->sector_count; i++)
{
/* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */
caddr = (volatile unsigned char *)(info->start[i]);
info->protect[i] = caddr[2] & 1;
}
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN)
{
caddr = (volatile unsigned char *)info->start[0];
*caddr = 0xF0; /* reset bank */
}
return (info->size);
}
/*-----------------------------------------------------------------------
*/
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile unsigned char *addr = (volatile unsigned char *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (volatile unsigned char *)(info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
while ((addr[0] & 0xFF) != 0xFF)
{
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned char *)info->start[0];
addr[0] = 0xF0; /* reset bank */
printf (" done\n");
return 0;
}
/*-----------------------------------------------------------------------
* Copy memory to flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
{
ulong cp, wp, data;
int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */
/*
* handle unaligned start bytes
*/
if ((l = addr - wp) != 0) {
data = 0;
for (i=0, cp=wp; i<l; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
for (; i<4 && cnt>0; ++i) {
data = (data << 8) | *src++;
--cnt;
++cp;
}
for (; cnt==0 && i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
}
/*
* handle word aligned part
*/
while (cnt >= 4) {
data = 0;
for (i=0; i<4; ++i) {
data = (data << 8) | *src++;
}
if ((rc = write_word(info, wp, data)) != 0) {
return (rc);
}
wp += 4;
cnt -= 4;
}
if (cnt == 0) {
return (0);
}
/*
* handle unaligned tail bytes
*/
data = 0;
for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
data = (data << 8) | *src++;
--cnt;
}
for (; i<4; ++i, ++cp) {
data = (data << 8) | (*(uchar *)cp);
}
return (write_word(info, wp, data));
}
/*-----------------------------------------------------------------------
* Write a word to Flash, returns:
* 0 - OK
* 1 - write timeout
* 2 - Flash not erased
*/
static int write_word (flash_info_t *info, ulong dest, ulong data)
{
volatile unsigned char *addr = (volatile unsigned char*)(info->start[0]),
*cdest,*cdata;
ulong start;
int flag, count = 4 ;
cdest = (volatile unsigned char *)dest ;
cdata = (volatile unsigned char *)&data ;
/* Check if Flash is (sufficiently) erased */
if ((*((vu_long *)dest) & data) != data) {
return (2);
}
while(count--)
{
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0xA0;
*cdest = *cdata;
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* data polling for D7 */
start = get_timer (0);
while ((*cdest ^ *cdata) & 0x80)
{
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1);
}
}
cdata++ ;
cdest++ ;
}
return (0);
}
/*-----------------------------------------------------------------------
*/

269
board/rbc823/kbd.c Normal file
View File

@@ -0,0 +1,269 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/* Modified by Udi Finkelstein
*
* This file includes communication routines for SMC1 that can run even if
* SMC2 have already been initialized.
*/
#include <common.h>
#include <watchdog.h>
#include <commproc.h>
#include <devices.h>
#include <lcd.h>
#define SMC_INDEX 0
#define PROFF_SMC PROFF_SMC1
#define CPM_CR_CH_SMC CPM_CR_CH_SMC1
#define RBC823_KBD_BAUDRATE 38400
#define CPM_KEYBOARD_BASE 0x1000
/*
* Minimal serial functions needed to use one of the SMC ports
* as serial console interface.
*/
void smc1_setbrg (void)
{
DECLARE_GLOBAL_DATA_PTR;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cp = &(im->im_cpm);
/* Set up the baud rate generator.
* See 8xx_io/commproc.c for details.
*
* Wire BRG2 to SMC1, BRG1 to SMC2
*/
cp->cp_simode = 0x00001000;
cp->cp_brgc2 =
(((gd->cpu_clk / 16 / RBC823_KBD_BAUDRATE)-1) << 1) | CPM_BRG_EN;
}
int smc1_init (void)
{
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile smc_t *sp;
volatile smc_uart_t *up;
volatile cbd_t *tbdf, *rbdf;
volatile cpm8xx_t *cp = &(im->im_cpm);
uint dpaddr;
/* initialize pointers to SMC */
sp = (smc_t *) &(cp->cp_smc[SMC_INDEX]);
up = (smc_uart_t *) &cp->cp_dparam[PROFF_SMC];
/* Disable transmitter/receiver.
*/
sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
/* Enable SDMA.
*/
im->im_siu_conf.sc_sdcr = 1;
/* clear error conditions */
#ifdef CFG_SDSR
im->im_sdma.sdma_sdsr = CFG_SDSR;
#else
im->im_sdma.sdma_sdsr = 0x83;
#endif
/* clear SDMA interrupt mask */
#ifdef CFG_SDMR
im->im_sdma.sdma_sdmr = CFG_SDMR;
#else
im->im_sdma.sdma_sdmr = 0x00;
#endif
/* Use Port B for SMC1 instead of other functions.
*/
cp->cp_pbpar |= 0x000000c0;
cp->cp_pbdir &= ~0x000000c0;
cp->cp_pbodr &= ~0x000000c0;
/* Set the physical address of the host memory buffers in
* the buffer descriptors.
*/
#ifdef CFG_ALLOC_DPRAM
dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
#else
dpaddr = CPM_KEYBOARD_BASE ;
#endif
/* Allocate space for two buffer descriptors in the DP ram.
* For now, this address seems OK, but it may have to
* change with newer versions of the firmware.
* damm: allocating space after the two buffers for rx/tx data
*/
rbdf = (cbd_t *)&cp->cp_dpmem[dpaddr];
rbdf->cbd_bufaddr = (uint) (rbdf+2);
rbdf->cbd_sc = 0;
tbdf = rbdf + 1;
tbdf->cbd_bufaddr = ((uint) (rbdf+2)) + 1;
tbdf->cbd_sc = 0;
/* Set up the uart parameters in the parameter ram.
*/
up->smc_rbase = dpaddr;
up->smc_tbase = dpaddr+sizeof(cbd_t);
up->smc_rfcr = SMC_EB;
up->smc_tfcr = SMC_EB;
/* Set UART mode, 8 bit, no parity, one stop.
* Enable receive and transmit.
*/
sp->smc_smcmr = smcr_mk_clen(9) | SMCMR_SM_UART;
/* Mask all interrupts and remove anything pending.
*/
sp->smc_smcm = 0;
sp->smc_smce = 0xff;
/* Set up the baud rate generator.
*/
smc1_setbrg ();
/* Make the first buffer the only buffer.
*/
tbdf->cbd_sc |= BD_SC_WRAP;
rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
/* Single character receive.
*/
up->smc_mrblr = 1;
up->smc_maxidl = 0;
/* Initialize Tx/Rx parameters.
*/
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_SMC, CPM_CR_INIT_TRX) | CPM_CR_FLG;
while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
;
/* Enable transmitter/receiver.
*/
sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
return (0);
}
void smc1_putc(const char c)
{
volatile cbd_t *tbdf;
volatile char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
tbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_tbase];
/* Wait for last character to go.
*/
buf = (char *)tbdf->cbd_bufaddr;
*buf = c;
tbdf->cbd_datlen = 1;
tbdf->cbd_sc |= BD_SC_READY;
__asm__("eieio");
while (tbdf->cbd_sc & BD_SC_READY) {
WATCHDOG_RESET ();
__asm__("eieio");
}
}
int smc1_getc(void)
{
volatile cbd_t *rbdf;
volatile unsigned char *buf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
unsigned char c;
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
/* Wait for character to show up.
*/
buf = (unsigned char *)rbdf->cbd_bufaddr;
while (rbdf->cbd_sc & BD_SC_EMPTY)
WATCHDOG_RESET ();
c = *buf;
rbdf->cbd_sc |= BD_SC_EMPTY;
return(c);
}
int smc1_tstc(void)
{
volatile cbd_t *rbdf;
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CFG_IMMR;
volatile cpm8xx_t *cpmp = &(im->im_cpm);
up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
rbdf = (cbd_t *)&cpmp->cp_dpmem[up->smc_rbase];
return(!(rbdf->cbd_sc & BD_SC_EMPTY));
}
/* search for keyboard and register it if found */
int drv_keyboard_init(void)
{
int error = 0;
device_t kbd_dev;
if (0) {
/* register the keyboard */
memset (&kbd_dev, 0, sizeof(device_t));
strcpy(kbd_dev.name, "kbd");
kbd_dev.flags = DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM;
kbd_dev.putc = NULL;
kbd_dev.puts = NULL;
kbd_dev.getc = smc1_getc;
kbd_dev.tstc = smc1_tstc;
error = device_register (&kbd_dev);
} else {
lcd_is_enabled = 0;
lcd_disable();
}
return error;
}

292
board/rbc823/rbc823.c Normal file
View File

@@ -0,0 +1,292 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "mpc8xx.h"
#include <linux/mtd/doc2000.h>
extern int kbd_init(void);
extern int drv_kbd_init(void);
/* ------------------------------------------------------------------------- */
static long int dram_size (long int, long int *, long int);
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
const uint sdram_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x11ADFC04, 0xEFBBBC00,
0x1FF77C47, /* last */
/*
* SDRAM Initialization (offset 5 in UPMA RAM)
*
* This is no UPM entry point. The following definition uses
* the remaining space to establish an initialization
* sequence, which is executed by a RUN command.
*
*/
0x1FF77C34, 0xEFEABC34, 0x1FB57C35, /* last */
/*
* Burst Read. (Offset 8 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEFC04, 0x10ADFC04, 0xF0AFFC00,
0xF0AFFC00, 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x1F27FC04, 0xEEAEBC00, 0x01B93C04, 0x1FF77C47, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Burst Write. (Offset 20 in UPMA RAM)
*/
0x1F07FC04, 0xEEAEBC00, 0x10AD7C00, 0xF0AFFC00,
0xF0AFFC00, 0xE1BBBC04, 0x1FF77C47, /* last */
_NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Refresh (Offset 30 in UPMA RAM)
*/
0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
0xFFFFFC84, 0xFFFFFC07, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Exception. (Offset 3c in UPMA RAM)
*/
0x1FF7FC07, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_,
};
const uint static_table[] =
{
/*
* Single Read. (Offset 0 in UPMA RAM)
*/
0x0FFFFC04, 0x0FF3FC04, 0x0FF3CC04, 0x0FF3CC04,
0x0FF3EC04, 0x0FF3CC00, 0x0FF7FC04, 0x3FFFFC04,
0xFFFFFC04, 0xFFFFFC05, /* last */
_NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
/*
* Single Write. (Offset 18 in UPMA RAM)
*/
0x0FFFFC04, 0x00FFFC04, 0x00FFFC04, 0x00FFFC04,
0x01FFFC00, 0x3FFFFC04, 0xFFFFFC04, 0xFFFFFC05, /* last */
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
};
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*
* Test TQ ID string (TQM8xx...)
* If present, check for "L" type (no second DRAM bank),
* otherwise "L" type is assumed as default.
*
* Return 1 for "L" type, 0 else.
*/
int checkboard (void)
{
unsigned char *s = getenv("serial#");
if (!s || strncmp(s, "TQM8", 4)) {
printf ("### No HW ID - assuming RBC823\n");
return (0);
}
puts(s);
putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
long int size_b0, size8, size9;
upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
/*
* 1 Bank of 64Mbit x 2 devices
*/
memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
memctl->memc_mar = 0x00000088;
/*
* Map controller SDRAM bank 0
*/
memctl->memc_or4 = CFG_OR4_PRELIM;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
udelay(200);
/*
* Perform SDRAM initializsation sequence
*/
memctl->memc_mcr = 0x80008105; /* SDRAM bank 0 */
udelay(1);
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
udelay(200);
memctl->memc_mcr = 0x80008130; /* SDRAM bank 0 - execute twice */
udelay(1);
memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
udelay(200);
memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */
udelay (1000);
/*
* Preliminary prescaler for refresh (depends on number of
* banks): This value is selected for four cycles every 62.4 us
* with two SDRAM banks or four cycles every 31.2 us with one
* bank. It will be adjusted after memory sizing.
*/
memctl->memc_mptpr = CFG_MPTPR_2BK_4K; // 16: but should be: CFG_MPTPR_1BK_4K
/*
* Check Bank 0 Memory Size for re-configuration
*
* try 8 column mode
*/
size8 = dram_size (CFG_MAMR_8COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
udelay (1000);
/*
* try 9 column mode
*/
size9 = dram_size (CFG_MAMR_9COL, (ulong *)SDRAM_BASE4_PRELIM, SDRAM_MAX_SIZE);
if (size8 < size9) { /* leave configuration at 9 columns */
size_b0 = size9;
/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
} else { /* back to 8 columns */
size_b0 = size8;
memctl->memc_mamr = CFG_MAMR_8COL;
udelay(500);
/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
}
udelay (1000);
/*
* Adjust refresh rate depending on SDRAM type, both banks
* For types > 128 MBit leave it at the current (fast) rate
*/
if ((size_b0 < 0x02000000) ) {
/* reduce to 15.6 us (62.4 us / quad) */
memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
udelay(1000);
}
/* SDRAM Bank 0 is bigger - map first */
memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
udelay(10000);
return (size_b0);
}
/* ------------------------------------------------------------------------- */
/*
* Check memory range for valid RAM. A simple memory test determines
* the actually available RAM size between addresses `base' and
* `base + maxsize'. Some (not all) hardware errors are detected:
* - short between address lines
* - short between data lines
*/
static long int dram_size (long int mamr_value, long int *base, long int maxsize)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
volatile long int *addr;
long int cnt, val;
memctl->memc_mamr = mamr_value;
for (cnt = maxsize/sizeof(long)/2; cnt > 0; cnt >>= 1) {
addr = base + cnt; /* pointer arith! */
*addr = ~cnt;
}
/* write 0 to base address */
addr = base;
*addr = 0;
/* check at base address */
if ((val = *addr) != 0) {
return (0);
}
for (cnt = 1; cnt < maxsize/sizeof(long) ; cnt <<= 1) {
addr = base + cnt; /* pointer arith! */
val = *addr;
if (val != (~cnt)) {
return (cnt * sizeof(long));
}
}
return cnt * sizeof(long);
/* NOTREACHED */
}
void doc_init(void)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
upmconfig(UPMB, (uint *)static_table, sizeof(static_table)/sizeof(uint));
memctl->memc_mbmr = MAMR_DSA_1_CYCL;
doc_probe(FLASH_BASE1_PRELIM);
}

133
board/rbc823/u-boot.lds Normal file
View File

@@ -0,0 +1,133 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
. = env_offset;
common/environment.o(.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}