arm: K3: Add basic support for J721S2 SoC definition
Add basic support for J721S2 SoC definition Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
This commit is contained in:
David Huang
Tom Rini
@@ -10,6 +10,9 @@ config SOC_K3_AM6
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config SOC_K3_J721E
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bool "TI's K3 based J721E SoC Family Support"
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config SOC_K3_J721S2
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bool "TI's K3 based J721S2 SoC Family Support"
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config SOC_K3_AM642
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bool "TI's K3 based AM642 SoC Family Support"
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@@ -21,7 +24,7 @@ config SYS_SOC
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config SYS_K3_NON_SECURE_MSRAM_SIZE
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hex
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default 0x80000 if SOC_K3_AM6
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default 0x100000 if SOC_K3_J721E
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default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
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default 0x1c0000 if SOC_K3_AM642
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help
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Describes the total size of the MCU or OCMC MSRAM present on
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@@ -32,7 +35,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
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config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
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hex
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default 0x58000 if SOC_K3_AM6
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default 0xc0000 if SOC_K3_J721E
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default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
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default 0x180000 if SOC_K3_AM642
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help
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Describes the maximum size of the image that ROM can download
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@@ -41,14 +44,14 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
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config SYS_K3_MCU_SCRATCHPAD_BASE
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hex
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default 0x40280000 if SOC_K3_AM6
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default 0x40280000 if SOC_K3_J721E
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default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
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help
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Describes the base address of MCU Scratchpad RAM.
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config SYS_K3_MCU_SCRATCHPAD_SIZE
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hex
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default 0x200 if SOC_K3_AM6
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default 0x200 if SOC_K3_J721E
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default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
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help
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Describes the size of MCU Scratchpad RAM.
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@@ -56,6 +59,7 @@ config SYS_K3_BOOT_PARAM_TABLE_INDEX
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hex
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default 0x41c7fbfc if SOC_K3_AM6
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default 0x41cffbfc if SOC_K3_J721E
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default 0x41cfdbfc if SOC_K3_J721S2
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default 0x701bebfc if SOC_K3_AM642
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help
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Address at which ROM stores the value which determines if SPL
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@@ -156,7 +160,7 @@ config K3_ATF_LOAD_ADDR
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config K3_DM_FW
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bool "Separate DM firmware image"
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depends on SPL && CPU_V7R && SOC_K3_J721E && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
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depends on SPL && CPU_V7R && (SOC_K3_J721E || SOC_K3_J721S2) && !CLK_TI_SCI && !TI_SCI_POWER_DOMAIN
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default y
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help
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Enabling this will indicate that the system has separate DM
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@@ -169,4 +173,5 @@ source "board/ti/am65x/Kconfig"
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source "board/ti/am64x/Kconfig"
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source "board/ti/j721e/Kconfig"
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source "board/siemens/iot2050/Kconfig"
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source "board/ti/j721s2/Kconfig"
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endif
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@@ -5,6 +5,7 @@
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obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
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obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
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obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
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obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
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obj-$(CONFIG_ARM64) += arm64-mmu.o
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obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
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@@ -181,6 +181,47 @@ struct mm_region *mem_map = j7200_mem_map;
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#endif /* CONFIG_SOC_K3_J721E */
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#ifdef CONFIG_SOC_K3_J721S2
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
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/* ToDo: Add 64bit IO */
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struct mm_region j721s2_mem_map[NR_MMU_REGIONS] = {
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{
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.virt = 0x0UL,
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.phys = 0x0UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x880000000UL,
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.phys = 0x880000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0x500000000UL,
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.phys = 0x500000000UL,
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.size = 0x400000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = j721s2_mem_map;
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#endif /* CONFIG_SOC_K3_J721S2 */
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#ifdef CONFIG_SOC_K3_AM642
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/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
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#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3)
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@@ -14,6 +14,10 @@
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#include "j721e_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721S2
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#include "j721s2_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_AM642
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#include "am64_hardware.h"
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#endif
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60
arch/arm/mach-k3/include/mach/j721s2_hardware.h
Normal file
60
arch/arm/mach-k3/include/mach/j721s2_hardware.h
Normal file
@@ -0,0 +1,60 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* K3: J721S2 SoC definitions, structures etc.
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*
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* (C) Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#ifndef __ASM_ARCH_J721S2_HARDWARE_H
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#define __ASM_ARCH_J721S2_HARDWARE_H
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#include <config.h>
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#ifndef __ASSEMBLY__
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#include <linux/bitops.h>
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#endif
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#define CTRL_MMR0_BASE 0x00100000
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#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
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#define MAIN_DEVSTAT_BOOT_MODE_B_MASK BIT(0)
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#define MAIN_DEVSTAT_BOOT_MODE_B_SHIFT 0
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(3, 1)
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#define MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 1
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK BIT(6)
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#define MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT 6
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_MASK BIT(7)
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#define MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT 7
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#define WKUP_CTRL_MMR0_BASE 0x43000000
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#define MCU_CTRL_MMR0_BASE 0x40f00000
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#define CTRLMMR_WKUP_DEVSTAT (WKUP_CTRL_MMR0_BASE + 0x30)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK GENMASK(5, 3)
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#define WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
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#define WKUP_DEVSTAT_MCU_OMLY_MASK BIT(6)
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#define WKUP_DEVSTAT_MCU_ONLY_SHIFT 6
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism
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* shared register definitions.
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*/
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#define CTRLMMR_LOCK_KICK0 0x01008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
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#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
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#define CTRLMMR_LOCK_KICK1 0x0100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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/* ROM HANDOFF Structure location */
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#define ROM_ENTENDED_BOOT_DATA_INFO 0x41cfdb00
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/* MCU SCRATCHPAD usage */
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#define TI_SRAM_SCRATCH_BOARD_EEPROM_START CONFIG_SYS_K3_MCU_SCRATCHPAD_BASE
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#endif /* __ASM_ARCH_J721S2_HARDWARE_H */
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46
arch/arm/mach-k3/include/mach/j721s2_spl.h
Normal file
46
arch/arm/mach-k3/include/mach/j721s2_spl.h
Normal file
@@ -0,0 +1,46 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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* David Huang <d-huang@ti.com>
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*/
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#ifndef _ASM_ARCH_J721S2_SPL_H_
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#define _ASM_ARCH_J721S2_SPL_H_
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/* With BootMode B = 0 */
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#include <linux/bitops.h>
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#define BOOT_DEVICE_HYPERFLASH 0x00
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#define BOOT_DEVICE_OSPI 0x01
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#define BOOT_DEVICE_QSPI 0x02
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#define BOOT_DEVICE_SPI 0x03
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#define BOOT_DEVICE_ETHERNET 0x04
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#define BOOT_DEVICE_I2C 0x06
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#define BOOT_DEVICE_UART 0x07
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#define BOOT_DEVICE_NOR BOOT_DEVICE_HYPERFLASH
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/* With BootMode B = 1 */
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#define BOOT_DEVICE_MMC2 0x10
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#define BOOT_DEVICE_MMC1 0x11
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#define BOOT_DEVICE_DFU 0x12
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#define BOOT_DEVICE_UFS 0x13
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#define BOOT_DEVIE_GPMC 0x14
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#define BOOT_DEVICE_PCIE 0x15
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#define BOOT_DEVICE_XSPI 0x16
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#define BOOT_DEVICE_RAM 0x17
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#define BOOT_DEVICE_MMC2_2 0xFF /* Invalid value */
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/* Backup boot modes with MCU Only = 0 */
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#define BACKUP_BOOT_DEVICE_RAM 0x0
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#define BACKUP_BOOT_DEVICE_USB 0x1
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#define BACKUP_BOOT_DEVICE_UART 0x3
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#define BACKUP_BOOT_DEVICE_ETHERNET 0x4
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#define BACKUP_BOOT_DEVICE_MMC2 0x5
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#define BACKUP_BOOT_DEVICE_SPI 0x6
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#define BACKUP_BOOT_DEVICE_I2C 0x7
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#define BOOT_MODE_B_SHIFT 4
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#define BOOT_MODE_B_MASK BIT(4)
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#define K3_PRIMARY_BOOTMODE 0x0
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#define K3_BACKUP_BOOTMODE 0x1
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#endif
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@@ -14,6 +14,10 @@
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#include "j721e_spl.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721S2
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#include "j721s2_spl.h"
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#endif
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#ifdef CONFIG_SOC_K3_AM642
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#include "am64_spl.h"
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#endif
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5
arch/arm/mach-k3/j721s2/Makefile
Normal file
5
arch/arm/mach-k3/j721s2/Makefile
Normal file
@@ -0,0 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
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obj-y += clk-data.o
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obj-y += dev-data.o
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403
arch/arm/mach-k3/j721s2/clk-data.c
Normal file
403
arch/arm/mach-k3/j721s2/clk-data.c
Normal file
@@ -0,0 +1,403 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* J721S2 specific clock platform data
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*
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* This file is auto generated. Please do not hand edit and report any issues
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* to Dave Gerlach <d-gerlach@ti.com>.
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*
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* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#include <linux/clk-provider.h>
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#include "k3-clk.h"
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static const char * const gluelogic_hfosc0_clkout_parents[] = {
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"osc_19_2_mhz",
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"osc_20_mhz",
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"osc_24_mhz",
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"osc_25_mhz",
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"osc_26_mhz",
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"osc_27_mhz",
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};
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static const char * const mcu_ospi0_iclk_sel_out0_parents[] = {
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"board_0_mcu_ospi0_dqs_out",
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"fss_mcu_0_ospi_0_ospi_oclk_clk",
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};
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static const char * const mcu_ospi1_iclk_sel_out0_parents[] = {
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"board_0_mcu_ospi1_dqs_out",
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"fss_mcu_0_ospi_1_ospi_oclk_clk",
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};
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static const char * const wkup_fref_clksel_out0_parents[] = {
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"gluelogic_hfosc0_clkout",
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NULL,
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};
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static const char * const main_pll_hfosc_sel_out1_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents[] = {
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"wkup_fref_clksel_out0",
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"hsdiv1_16fft_mcu_0_hsdivout0_clk",
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};
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static const char * const mcu_ospi_ref_clk_sel_out0_parents[] = {
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"hsdiv4_16fft_mcu_1_hsdivout4_clk",
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"hsdiv4_16fft_mcu_2_hsdivout4_clk",
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};
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static const char * const mcu_ospi_ref_clk_sel_out1_parents[] = {
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"hsdiv4_16fft_mcu_1_hsdivout4_clk",
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"hsdiv4_16fft_mcu_2_hsdivout4_clk",
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};
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static const char * const mcu_usart_clksel_out0_parents[] = {
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"hsdiv4_16fft_mcu_1_hsdivout3_clk",
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"postdiv3_16fft_main_1_hsdivout5_clk",
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};
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static const char * const wkup_i2c_mcupll_bypass_out0_parents[] = {
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"hsdiv4_16fft_mcu_1_hsdivout3_clk",
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"gluelogic_hfosc0_clkout",
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};
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static const char * const main_pll_hfosc_sel_out0_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out12_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out19_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out2_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out26_0_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out3_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out7_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const main_pll_hfosc_sel_out8_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const usb0_refclk_sel_out0_parents[] = {
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"gluelogic_hfosc0_clkout",
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"board_0_hfosc1_clk_out",
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};
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static const char * const emmcsd1_lb_clksel_out0_parents[] = {
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"board_0_mmc1_clklb_out",
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"board_0_mmc1_clk_out",
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};
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static const char * const mcu_clkout_mux_out0_parents[] = {
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"hsdiv4_16fft_mcu_2_hsdivout0_clk",
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"hsdiv4_16fft_mcu_2_hsdivout0_clk",
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};
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static const char * const k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
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"main_pll_hfosc_sel_out0",
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"hsdiv4_16fft_main_0_hsdivout0_clk",
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};
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static const char * const dpi0_ext_clksel_out0_parents[] = {
|
||||
"hsdiv1_16fft_main_19_hsdivout0_clk",
|
||||
"board_0_vout0_extpclkin_out",
|
||||
};
|
||||
|
||||
static const char * const emmcsd_refclk_sel_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_0_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_1_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_3_hsdivout2_clk",
|
||||
};
|
||||
|
||||
static const char * const emmcsd_refclk_sel_out1_parents[] = {
|
||||
"hsdiv4_16fft_main_0_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_1_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_2_hsdivout2_clk",
|
||||
"hsdiv4_16fft_main_3_hsdivout2_clk",
|
||||
};
|
||||
|
||||
static const char * const gtc_clk_mux_out0_parents[] = {
|
||||
"hsdiv4_16fft_main_3_hsdivout1_clk",
|
||||
"postdiv3_16fft_main_0_hsdivout6_clk",
|
||||
"board_0_mcu_cpts0_rft_clk_out",
|
||||
"board_0_cpts0_rft_clk_out",
|
||||
"board_0_mcu_ext_refclk0_out",
|
||||
"board_0_ext_refclk1_out",
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
NULL,
|
||||
"hsdiv4_16fft_mcu_2_hsdivout1_clk",
|
||||
"k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
|
||||
};
|
||||
|
||||
static const struct clk_data clk_list[] = {
|
||||
CLK_FIXED_RATE("osc_27_mhz", 27000000, 0),
|
||||
CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
|
||||
CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
|
||||
CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
|
||||
CLK_FIXED_RATE("osc_20_mhz", 20000000, 0),
|
||||
CLK_FIXED_RATE("osc_19_2_mhz", 19200000, 0),
|
||||
CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
|
||||
CLK_FIXED_RATE("board_0_hfosc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi0_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ospi1_dqs_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_wkup_i2c0_scl_out", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_ospi_0_ospi_oclk_clk", 0, 0),
|
||||
CLK_FIXED_RATE("fss_mcu_0_ospi_1_ospi_oclk_clk", 0, 0),
|
||||
CLK_MUX("mcu_ospi0_iclk_sel_out0", mcu_ospi0_iclk_sel_out0_parents, 2, 0x40f08030, 4, 1, 0),
|
||||
CLK_MUX("mcu_ospi1_iclk_sel_out0", mcu_ospi1_iclk_sel_out0_parents, 2, 0x40f08034, 4, 1, 0),
|
||||
CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
|
||||
CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
|
||||
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
|
||||
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_DIV("pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
|
||||
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
|
||||
CLK_PLL_DEFFREQ("pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
|
||||
CLK_DIV("postdiv3_16fft_main_1_hsdivout5_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv1_16fft_mcu_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_0_foutvcop_clk", 0x40d00080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout3_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d0108c, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_1_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_1_foutvcop_clk", 0x40d01090, 0, 7, 0, 0),
|
||||
CLK_DIV_DEFFREQ("hsdiv4_16fft_mcu_2_hsdivout4_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02090, 0, 7, 0, 0, 166666666),
|
||||
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", k3_pll_ctrl_wrap_wkup_0_sysclkout_clk_parents, 2, 0x42010000, 0),
|
||||
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x42010118, 0, 5, 0, 0),
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out0", mcu_ospi_ref_clk_sel_out0_parents, 2, 0x40f08030, 0, 1, 0),
|
||||
CLK_MUX("mcu_ospi_ref_clk_sel_out1", mcu_ospi_ref_clk_sel_out1_parents, 2, 0x40f08034, 0, 1, 0),
|
||||
CLK_MUX("mcu_usart_clksel_out0", mcu_usart_clksel_out0_parents, 2, 0x40f081c0, 0, 1, 0),
|
||||
CLK_MUX("wkup_i2c_mcupll_bypass_out0", wkup_i2c_mcupll_bypass_out0_parents, 2, 0x43008060, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out0", main_pll_hfosc_sel_out0_parents, 2, 0x43008080, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out12", main_pll_hfosc_sel_out12_parents, 2, 0x430080b0, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out19", main_pll_hfosc_sel_out19_parents, 2, 0x430080cc, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out2", main_pll_hfosc_sel_out2_parents, 2, 0x43008088, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out26_0", main_pll_hfosc_sel_out26_0_parents, 2, 0x430080e8, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out3", main_pll_hfosc_sel_out3_parents, 2, 0x4300808c, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out7", main_pll_hfosc_sel_out7_parents, 2, 0x4300809c, 0, 1, 0),
|
||||
CLK_MUX("main_pll_hfosc_sel_out8", main_pll_hfosc_sel_out8_parents, 2, 0x430080a0, 0, 1, 0),
|
||||
CLK_MUX("usb0_refclk_sel_out0", usb0_refclk_sel_out0_parents, 2, 0x1080e0, 0, 1, 0),
|
||||
CLK_FIXED_RATE("board_0_cpts0_rft_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ddr0_ckn_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ddr0_ckp_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ddr1_ckn_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ddr1_ckp_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_cpts0_rft_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
|
||||
CLK_FIXED_RATE("board_0_vout0_extpclkin_out", 0, 0),
|
||||
CLK_FIXED_RATE("emmc8ss_16ffc_main_0_emmcss_io_clk", 0, 0),
|
||||
CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
|
||||
CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
|
||||
CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout0_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout1_clk", "pllfracf2_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02084, 0, 7, 0, 0),
|
||||
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck", 0, 0),
|
||||
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n", 0, 0),
|
||||
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck", 0, 0),
|
||||
CLK_FIXED_RATE("j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n", 0, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
|
||||
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_DIV("pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_19_foutvcop_clk", "main_pll_hfosc_sel_out19", 0x693000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_26_foutvcop_clk", "main_pll_hfosc_sel_out26_0", 0x69a000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_3_foutvcop_clk", "main_pll_hfosc_sel_out3", 0x683000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_7_foutvcop_clk", "main_pll_hfosc_sel_out7", 0x687000, 0),
|
||||
CLK_PLL("pllfracf2_ssmod_16fft_main_8_foutvcop_clk", "main_pll_hfosc_sel_out8", 0x688000, 0),
|
||||
CLK_DIV("postdiv3_16fft_main_0_hsdivout6_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv3_16fft_main_0_hsdivout8_clk", "pllfracf2_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
|
||||
CLK_DIV("postdiv3_16fft_main_1_hsdivout7_clk", "pllfracf2_ssmod_16fft_main_1_foutpostdiv_clk", 0x68109c, 0, 7, 0, 0),
|
||||
CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0),
|
||||
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0),
|
||||
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000),
|
||||
CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv1_16fft_main_19_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_19_foutvcop_clk", 0x693080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf2_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_3_hsdivout1_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683084, 0, 7, 0, 0),
|
||||
CLK_DIV("hsdiv4_16fft_main_3_hsdivout2_clk", "pllfracf2_ssmod_16fft_main_3_foutvcop_clk", 0x683088, 0, 7, 0, 0),
|
||||
CLK_MUX_PLLCTRL("k3_pll_ctrl_wrap_main_0_sysclkout_clk", k3_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
|
||||
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
|
||||
CLK_MUX("dpi0_ext_clksel_out0", dpi0_ext_clksel_out0_parents, 2, 0x108300, 0, 1, 0),
|
||||
CLK_MUX("emmcsd_refclk_sel_out0", emmcsd_refclk_sel_out0_parents, 4, 0x1080b0, 0, 2, 0),
|
||||
CLK_MUX("emmcsd_refclk_sel_out1", emmcsd_refclk_sel_out1_parents, 4, 0x1080b4, 0, 2, 0),
|
||||
CLK_MUX("gtc_clk_mux_out0", gtc_clk_mux_out0_parents, 16, 0x108030, 0, 4, 0),
|
||||
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
|
||||
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
|
||||
};
|
||||
|
||||
static const struct dev_clk soc_dev_clk_data[] = {
|
||||
DEV_CLK(4, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(4, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
|
||||
DEV_CLK(4, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(43, 0, "postdiv3_16fft_main_0_hsdivout8_clk"),
|
||||
DEV_CLK(43, 1, "hsdiv4_16fft_main_0_hsdivout3_clk"),
|
||||
DEV_CLK(43, 2, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(43, 3, "board_0_hfosc1_clk_out"),
|
||||
DEV_CLK(43, 5, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(43, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(43, 7, "board_0_hfosc1_clk_out"),
|
||||
DEV_CLK(43, 9, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(43, 10, "hsdiv4_16fft_main_0_hsdivout4_clk"),
|
||||
DEV_CLK(43, 11, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(43, 12, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(61, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(61, 1, "gtc_clk_mux_out0"),
|
||||
DEV_CLK(61, 2, "hsdiv4_16fft_main_3_hsdivout1_clk"),
|
||||
DEV_CLK(61, 3, "postdiv3_16fft_main_0_hsdivout6_clk"),
|
||||
DEV_CLK(61, 4, "board_0_mcu_cpts0_rft_clk_out"),
|
||||
DEV_CLK(61, 5, "board_0_cpts0_rft_clk_out"),
|
||||
DEV_CLK(61, 6, "board_0_mcu_ext_refclk0_out"),
|
||||
DEV_CLK(61, 7, "board_0_ext_refclk1_out"),
|
||||
DEV_CLK(61, 16, "hsdiv4_16fft_mcu_2_hsdivout1_clk"),
|
||||
DEV_CLK(61, 17, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(98, 1, "emmcsd_refclk_sel_out0"),
|
||||
DEV_CLK(98, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(98, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
|
||||
DEV_CLK(98, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||
DEV_CLK(98, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
|
||||
DEV_CLK(98, 6, "emmcsd1_lb_clksel_out0"),
|
||||
DEV_CLK(98, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(99, 1, "emmcsd_refclk_sel_out1"),
|
||||
DEV_CLK(99, 2, "hsdiv4_16fft_main_0_hsdivout2_clk"),
|
||||
DEV_CLK(99, 3, "hsdiv4_16fft_main_1_hsdivout2_clk"),
|
||||
DEV_CLK(99, 4, "hsdiv4_16fft_main_2_hsdivout2_clk"),
|
||||
DEV_CLK(99, 5, "hsdiv4_16fft_main_3_hsdivout2_clk"),
|
||||
DEV_CLK(99, 7, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(99, 8, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(108, 1, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(108, 2, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(108, 3, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(108, 6, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(108, 11, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(109, 0, "mcu_ospi0_iclk_sel_out0"),
|
||||
DEV_CLK(109, 1, "board_0_mcu_ospi0_dqs_out"),
|
||||
DEV_CLK(109, 2, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(109, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(109, 5, "mcu_ospi_ref_clk_sel_out0"),
|
||||
DEV_CLK(109, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
|
||||
DEV_CLK(109, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(109, 8, "board_0_mcu_ospi0_dqs_out"),
|
||||
DEV_CLK(109, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(110, 0, "mcu_ospi1_iclk_sel_out0"),
|
||||
DEV_CLK(110, 1, "board_0_mcu_ospi1_dqs_out"),
|
||||
DEV_CLK(110, 2, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
|
||||
DEV_CLK(110, 3, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(110, 5, "mcu_ospi_ref_clk_sel_out1"),
|
||||
DEV_CLK(110, 6, "hsdiv4_16fft_mcu_1_hsdivout4_clk"),
|
||||
DEV_CLK(110, 7, "hsdiv4_16fft_mcu_2_hsdivout4_clk"),
|
||||
DEV_CLK(110, 8, "board_0_mcu_ospi1_dqs_out"),
|
||||
DEV_CLK(110, 9, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(115, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(126, 0, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(126, 1, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(138, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
|
||||
DEV_CLK(138, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
|
||||
DEV_CLK(138, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(138, 3, "board_0_ddr0_ckn_out"),
|
||||
DEV_CLK(138, 5, "board_0_ddr0_ckp_out"),
|
||||
DEV_CLK(138, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(139, 0, "hsdiv0_16fft_main_26_hsdivout0_clk"),
|
||||
DEV_CLK(139, 1, "hsdiv0_16fft_main_7_hsdivout0_clk"),
|
||||
DEV_CLK(139, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(139, 3, "board_0_ddr1_ckn_out"),
|
||||
DEV_CLK(139, 5, "board_0_ddr1_ckp_out"),
|
||||
DEV_CLK(139, 7, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(143, 0, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(143, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(146, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(146, 3, "usart_programmable_clock_divider_out0"),
|
||||
DEV_CLK(149, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(149, 3, "mcu_usart_clksel_out0"),
|
||||
DEV_CLK(149, 4, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
|
||||
DEV_CLK(149, 5, "postdiv3_16fft_main_1_hsdivout5_clk"),
|
||||
DEV_CLK(157, 9, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 103, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 104, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck"),
|
||||
DEV_CLK(157, 111, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 174, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck"),
|
||||
DEV_CLK(157, 177, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(157, 179, "fss_mcu_0_ospi_0_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 182, "mshsi2c_wkup_0_porscl"),
|
||||
DEV_CLK(157, 187, "fss_mcu_0_ospi_1_ospi_oclk_clk"),
|
||||
DEV_CLK(157, 194, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
|
||||
DEV_CLK(157, 197, "j7am_ddr_ew_wrap_dv_wrap_main_0_ddrss_io_ck_n"),
|
||||
DEV_CLK(157, 208, "j7am_ddr_ew_wrap_dv_wrap_main_1_ddrss_io_ck_n"),
|
||||
DEV_CLK(157, 214, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_p"),
|
||||
DEV_CLK(157, 221, "mcu_clkout_mux_out0"),
|
||||
DEV_CLK(157, 222, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(157, 223, "hsdiv4_16fft_mcu_2_hsdivout0_clk"),
|
||||
DEV_CLK(157, 225, "emmc8ss_16ffc_main_0_emmcss_io_clk"),
|
||||
DEV_CLK(157, 231, "fss_mcu_0_hyperbus1p0_0_hpb_out_clk_n"),
|
||||
DEV_CLK(157, 352, "dpi0_ext_clksel_out0"),
|
||||
DEV_CLK(180, 0, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(180, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(202, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
|
||||
DEV_CLK(223, 1, "wkup_i2c_mcupll_bypass_out0"),
|
||||
DEV_CLK(223, 2, "hsdiv4_16fft_mcu_1_hsdivout3_clk"),
|
||||
DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
|
||||
DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
|
||||
DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(360, 13, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(360, 15, "postdiv3_16fft_main_1_hsdivout7_clk"),
|
||||
DEV_CLK(360, 16, "usb0_refclk_sel_out0"),
|
||||
DEV_CLK(360, 17, "gluelogic_hfosc0_clkout"),
|
||||
DEV_CLK(360, 18, "board_0_hfosc1_clk_out"),
|
||||
DEV_CLK(360, 22, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
DEV_CLK(360, 23, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
|
||||
};
|
||||
|
||||
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
|
||||
.clk_list = clk_list,
|
||||
.clk_list_cnt = 104,
|
||||
.soc_dev_clk_data = soc_dev_clk_data,
|
||||
.soc_dev_clk_data_cnt = 122,
|
||||
};
|
||||
85
arch/arm/mach-k3/j721s2/dev-data.c
Normal file
85
arch/arm/mach-k3/j721s2/dev-data.c
Normal file
@@ -0,0 +1,85 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* J721S2 specific device platform data
|
||||
*
|
||||
* This file is auto generated. Please do not hand edit and report any issues
|
||||
* to Dave Gerlach <d-gerlach@ti.com>.
|
||||
*
|
||||
* Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*/
|
||||
|
||||
#include "k3-dev.h"
|
||||
|
||||
static struct ti_psc soc_psc_list[] = {
|
||||
[0] = PSC(0, 0x42000000),
|
||||
[1] = PSC(1, 0x00400000),
|
||||
};
|
||||
|
||||
static struct ti_pd soc_pd_list[] = {
|
||||
[0] = PSC_PD(0, &soc_psc_list[0], NULL),
|
||||
[1] = PSC_PD(0, &soc_psc_list[1], NULL),
|
||||
[2] = PSC_PD(1, &soc_psc_list[1], &soc_pd_list[1]),
|
||||
[3] = PSC_PD(14, &soc_psc_list[1], NULL),
|
||||
[4] = PSC_PD(15, &soc_psc_list[1], &soc_pd_list[3]),
|
||||
[5] = PSC_PD(16, &soc_psc_list[1], &soc_pd_list[3]),
|
||||
};
|
||||
|
||||
static struct ti_lpsc soc_lpsc_list[] = {
|
||||
[0] = PSC_LPSC(0, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[1] = PSC_LPSC(3, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[2] = PSC_LPSC(10, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[3] = PSC_LPSC(11, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[4] = PSC_LPSC(12, &soc_psc_list[0], &soc_pd_list[0], NULL),
|
||||
[5] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[1], NULL),
|
||||
[6] = PSC_LPSC(9, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[2]),
|
||||
[7] = PSC_LPSC(14, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
|
||||
[8] = PSC_LPSC(15, &soc_psc_list[1], &soc_pd_list[1], NULL),
|
||||
[9] = PSC_LPSC(16, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[10]),
|
||||
[10] = PSC_LPSC(17, &soc_psc_list[1], &soc_pd_list[1], NULL),
|
||||
[11] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
|
||||
[12] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
|
||||
[13] = PSC_LPSC(25, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[4]),
|
||||
[14] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], NULL),
|
||||
[15] = PSC_LPSC(45, &soc_psc_list[1], &soc_pd_list[2], NULL),
|
||||
[16] = PSC_LPSC(78, &soc_psc_list[1], &soc_pd_list[3], NULL),
|
||||
[17] = PSC_LPSC(80, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[16]),
|
||||
[18] = PSC_LPSC(81, &soc_psc_list[1], &soc_pd_list[5], &soc_lpsc_list[16]),
|
||||
};
|
||||
|
||||
static struct ti_dev soc_dev_list[] = {
|
||||
PSC_DEV(108, &soc_lpsc_list[0]),
|
||||
PSC_DEV(109, &soc_lpsc_list[0]),
|
||||
PSC_DEV(110, &soc_lpsc_list[0]),
|
||||
PSC_DEV(180, &soc_lpsc_list[0]),
|
||||
PSC_DEV(149, &soc_lpsc_list[0]),
|
||||
PSC_DEV(115, &soc_lpsc_list[1]),
|
||||
PSC_DEV(223, &soc_lpsc_list[1]),
|
||||
PSC_DEV(109, &soc_lpsc_list[2]),
|
||||
PSC_DEV(110, &soc_lpsc_list[3]),
|
||||
PSC_DEV(108, &soc_lpsc_list[4]),
|
||||
PSC_DEV(43, &soc_lpsc_list[5]),
|
||||
PSC_DEV(61, &soc_lpsc_list[6]),
|
||||
PSC_DEV(96, &soc_lpsc_list[7]),
|
||||
PSC_DEV(138, &soc_lpsc_list[8]),
|
||||
PSC_DEV(97, &soc_lpsc_list[9]),
|
||||
PSC_DEV(139, &soc_lpsc_list[10]),
|
||||
PSC_DEV(360, &soc_lpsc_list[11]),
|
||||
PSC_DEV(99, &soc_lpsc_list[12]),
|
||||
PSC_DEV(98, &soc_lpsc_list[13]),
|
||||
PSC_DEV(146, &soc_lpsc_list[14]),
|
||||
PSC_DEV(357, &soc_lpsc_list[15]),
|
||||
PSC_DEV(4, &soc_lpsc_list[16]),
|
||||
PSC_DEV(202, &soc_lpsc_list[17]),
|
||||
PSC_DEV(203, &soc_lpsc_list[18]),
|
||||
};
|
||||
|
||||
const struct ti_k3_pd_platdata j721s2_pd_platdata = {
|
||||
.psc = soc_psc_list,
|
||||
.pd = soc_pd_list,
|
||||
.lpsc = soc_lpsc_list,
|
||||
.devs = soc_dev_list,
|
||||
.num_psc = 2,
|
||||
.num_pd = 6,
|
||||
.num_lpsc = 19,
|
||||
.num_devs = 24,
|
||||
};
|
||||
312
arch/arm/mach-k3/j721s2_init.c
Normal file
312
arch/arm/mach-k3/j721s2_init.c
Normal file
@@ -0,0 +1,312 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* J721E: SoC specific initialization
|
||||
*
|
||||
* Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
|
||||
* David Huang <d-huang@ti.com>
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <init.h>
|
||||
#include <spl.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/armv7_mpu.h>
|
||||
#include <asm/arch/hardware.h>
|
||||
#include <asm/arch/sysfw-loader.h>
|
||||
#include "common.h"
|
||||
#include <asm/arch/sys_proto.h>
|
||||
#include <linux/soc/ti/ti_sci_protocol.h>
|
||||
#include <dm.h>
|
||||
#include <dm/uclass-internal.h>
|
||||
#include <dm/pinctrl.h>
|
||||
#include <mmc.h>
|
||||
#include <remoteproc.h>
|
||||
|
||||
#ifdef CONFIG_SPL_BUILD
|
||||
|
||||
static void ctrl_mmr_unlock(void)
|
||||
{
|
||||
/* Unlock all WKUP_CTRL_MMR0 module registers */
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 4);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 6);
|
||||
mmr_unlock(WKUP_CTRL_MMR0_BASE, 7);
|
||||
|
||||
/* Unlock all MCU_CTRL_MMR0 module registers */
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(MCU_CTRL_MMR0_BASE, 4);
|
||||
|
||||
/* Unlock all CTRL_MMR0 module registers */
|
||||
mmr_unlock(CTRL_MMR0_BASE, 0);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 1);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 2);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 3);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 5);
|
||||
mmr_unlock(CTRL_MMR0_BASE, 7);
|
||||
}
|
||||
|
||||
void k3_mmc_stop_clock(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
|
||||
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
||||
struct mmc *mmc = find_mmc_device(0);
|
||||
|
||||
if (!mmc)
|
||||
return;
|
||||
|
||||
mmc->saved_clock = mmc->clock;
|
||||
mmc_set_clock(mmc, 0, true);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void k3_mmc_restart_clock(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
|
||||
if (spl_boot_device() == BOOT_DEVICE_MMC1) {
|
||||
struct mmc *mmc = find_mmc_device(0);
|
||||
|
||||
if (!mmc)
|
||||
return;
|
||||
|
||||
mmc_set_clock(mmc, mmc->saved_clock, false);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This uninitialized global variable would normal end up in the .bss section,
|
||||
* but the .bss is cleared between writing and reading this variable, so move
|
||||
* it to the .data section.
|
||||
*/
|
||||
u32 bootindex __attribute__((section(".data")));
|
||||
static struct rom_extended_boot_data bootdata __section(".data");
|
||||
|
||||
static void store_boot_info_from_rom(void)
|
||||
{
|
||||
bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX);
|
||||
memcpy(&bootdata, (uintptr_t *)ROM_ENTENDED_BOOT_DATA_INFO,
|
||||
sizeof(struct rom_extended_boot_data));
|
||||
}
|
||||
|
||||
void board_init_f(ulong dummy)
|
||||
{
|
||||
struct udevice *dev;
|
||||
int ret;
|
||||
/*
|
||||
* Cannot delay this further as there is a chance that
|
||||
* K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section.
|
||||
*/
|
||||
store_boot_info_from_rom();
|
||||
|
||||
/* Make all control module registers accessible */
|
||||
ctrl_mmr_unlock();
|
||||
|
||||
if (IS_ENABLED(CONFIG_CPU_V7R)) {
|
||||
disable_linefill_optimization();
|
||||
setup_k3_mpu_regions();
|
||||
}
|
||||
|
||||
/* Init DM early */
|
||||
spl_early_init();
|
||||
|
||||
/* Prepare console output */
|
||||
preloader_console_init();
|
||||
|
||||
if (IS_ENABLED(CONFIG_K3_LOAD_SYSFW)) {
|
||||
/*
|
||||
* Process pinctrl for the serial0 a.k.a. WKUP_UART0 module and continue
|
||||
* regardless of the result of pinctrl. Do this without probing the
|
||||
* device, but instead by searching the device that would request the
|
||||
* given sequence number if probed. The UART will be used by the system
|
||||
* firmware (SYSFW) image for various purposes and SYSFW depends on us
|
||||
* to initialize its pin settings.
|
||||
*/
|
||||
ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, &dev);
|
||||
if (!ret)
|
||||
pinctrl_select_state(dev, "default");
|
||||
|
||||
/*
|
||||
* Load, start up, and configure system controller firmware. Provide
|
||||
* the U-Boot console init function to the SYSFW post-PM configuration
|
||||
* callback hook, effectively switching on (or over) the console
|
||||
* output.
|
||||
*/
|
||||
k3_sysfw_loader(is_rom_loaded_sysfw(&bootdata),
|
||||
k3_mmc_stop_clock, k3_mmc_restart_clock);
|
||||
|
||||
if (IS_ENABLED(CONFIG_SPL_CLK_K3)) {
|
||||
/*
|
||||
* Force probe of clk_k3 driver here to ensure basic default clock
|
||||
* configuration is always done for enabling PM services.
|
||||
*/
|
||||
ret = uclass_get_device_by_driver(UCLASS_CLK,
|
||||
DM_DRIVER_GET(ti_clk),
|
||||
&dev);
|
||||
if (ret)
|
||||
panic("Failed to initialize clk-k3!\n");
|
||||
}
|
||||
}
|
||||
|
||||
/* Output System Firmware version info */
|
||||
k3_sysfw_print_ver();
|
||||
|
||||
if (IS_ENABLED(CONFIG_TARGET_J721S2_R5_EVM)) {
|
||||
ret = uclass_get_device_by_name(UCLASS_MISC, "msmc", &dev);
|
||||
if (ret)
|
||||
panic("Probe of msmc failed: %d\n", ret);
|
||||
|
||||
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
|
||||
if (ret)
|
||||
panic("DRAM 0 init failed: %d\n", ret);
|
||||
|
||||
ret = uclass_next_device(&dev);
|
||||
if (ret)
|
||||
panic("DRAM 1 init failed: %d\n", ret);
|
||||
}
|
||||
spl_enable_dcache();
|
||||
}
|
||||
|
||||
u32 spl_mmc_boot_mode(const u32 boot_device)
|
||||
{
|
||||
switch (boot_device) {
|
||||
case BOOT_DEVICE_MMC1:
|
||||
return MMCSD_MODE_EMMCBOOT;
|
||||
case BOOT_DEVICE_MMC2:
|
||||
return MMCSD_MODE_FS;
|
||||
default:
|
||||
return MMCSD_MODE_RAW;
|
||||
}
|
||||
}
|
||||
|
||||
static u32 __get_backup_bootmedia(u32 main_devstat)
|
||||
{
|
||||
u32 bkup_boot = (main_devstat & MAIN_DEVSTAT_BKUP_BOOTMODE_MASK) >>
|
||||
MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT;
|
||||
|
||||
switch (bkup_boot) {
|
||||
case BACKUP_BOOT_DEVICE_USB:
|
||||
return BOOT_DEVICE_DFU;
|
||||
case BACKUP_BOOT_DEVICE_UART:
|
||||
return BOOT_DEVICE_UART;
|
||||
case BACKUP_BOOT_DEVICE_ETHERNET:
|
||||
return BOOT_DEVICE_ETHERNET;
|
||||
case BACKUP_BOOT_DEVICE_MMC2:
|
||||
{
|
||||
u32 port = (main_devstat & MAIN_DEVSTAT_BKUP_MMC_PORT_MASK) >>
|
||||
MAIN_DEVSTAT_BKUP_MMC_PORT_SHIFT;
|
||||
if (port == 0x0)
|
||||
return BOOT_DEVICE_MMC1;
|
||||
return BOOT_DEVICE_MMC2;
|
||||
}
|
||||
case BACKUP_BOOT_DEVICE_SPI:
|
||||
return BOOT_DEVICE_SPI;
|
||||
case BACKUP_BOOT_DEVICE_I2C:
|
||||
return BOOT_DEVICE_I2C;
|
||||
}
|
||||
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat)
|
||||
{
|
||||
u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >>
|
||||
WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT;
|
||||
|
||||
bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) <<
|
||||
BOOT_MODE_B_SHIFT;
|
||||
|
||||
if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI ||
|
||||
bootmode == BOOT_DEVICE_XSPI)
|
||||
bootmode = BOOT_DEVICE_SPI;
|
||||
|
||||
if (bootmode == BOOT_DEVICE_MMC2) {
|
||||
u32 port = (main_devstat &
|
||||
MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >>
|
||||
MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT;
|
||||
if (port == 0x0)
|
||||
bootmode = BOOT_DEVICE_MMC1;
|
||||
}
|
||||
|
||||
return bootmode;
|
||||
}
|
||||
|
||||
u32 spl_boot_device(void)
|
||||
{
|
||||
u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT);
|
||||
u32 main_devstat;
|
||||
|
||||
if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) {
|
||||
printf("ERROR: MCU only boot is not yet supported\n");
|
||||
return BOOT_DEVICE_RAM;
|
||||
}
|
||||
|
||||
/* MAIN CTRL MMR can only be read if MCU ONLY is 0 */
|
||||
main_devstat = readl(CTRLMMR_MAIN_DEVSTAT);
|
||||
|
||||
if (bootindex == K3_PRIMARY_BOOTMODE)
|
||||
return __get_primary_bootmedia(main_devstat, wkup_devstat);
|
||||
else
|
||||
return __get_backup_bootmedia(main_devstat);
|
||||
}
|
||||
#endif
|
||||
|
||||
#define J721S2_DEV_MCU_RTI0 295
|
||||
#define J721S2_DEV_MCU_RTI1 296
|
||||
#define J721S2_DEV_MCU_ARMSS0_CPU0 284
|
||||
#define J721S2_DEV_MCU_ARMSS0_CPU1 285
|
||||
|
||||
void release_resources_for_core_shutdown(void)
|
||||
{
|
||||
if (IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)) {
|
||||
struct ti_sci_handle *ti_sci;
|
||||
struct ti_sci_dev_ops *dev_ops;
|
||||
struct ti_sci_proc_ops *proc_ops;
|
||||
int ret;
|
||||
u32 i;
|
||||
|
||||
const u32 put_device_ids[] = {
|
||||
J721S2_DEV_MCU_RTI0,
|
||||
J721S2_DEV_MCU_RTI1,
|
||||
};
|
||||
|
||||
ti_sci = get_ti_sci_handle();
|
||||
dev_ops = &ti_sci->ops.dev_ops;
|
||||
proc_ops = &ti_sci->ops.proc_ops;
|
||||
|
||||
/* Iterate through list of devices to put (shutdown) */
|
||||
for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) {
|
||||
u32 id = put_device_ids[i];
|
||||
|
||||
ret = dev_ops->put_device(ti_sci, id);
|
||||
if (ret)
|
||||
panic("Failed to put device %u (%d)\n", id, ret);
|
||||
}
|
||||
|
||||
const u32 put_core_ids[] = {
|
||||
J721S2_DEV_MCU_ARMSS0_CPU1,
|
||||
J721S2_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */
|
||||
};
|
||||
|
||||
/* Iterate through list of cores to put (shutdown) */
|
||||
for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) {
|
||||
u32 id = put_core_ids[i];
|
||||
|
||||
/*
|
||||
* Queue up the core shutdown request. Note that this call
|
||||
* needs to be followed up by an actual invocation of an WFE
|
||||
* or WFI CPU instruction.
|
||||
*/
|
||||
ret = proc_ops->proc_shutdown_no_wait(ti_sci, id);
|
||||
if (ret)
|
||||
panic("Failed sending core %u shutdown message (%d)\n",
|
||||
id, ret);
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user