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Merge branch '2021-10-01-assorted-removal-and-migration' into next

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- Remove the last non-CONFIG_DM boards, and their related unused code.
- Finish a few partial migrations to Kconfig, and remove some redundant
  serial related code.
This commit is contained in:
Tom Rini 2021-10-02 15:47:28 -04:00
commit 67e6c540a0
143 changed files with 59 additions and 9150 deletions
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5
README
View File

@ -647,11 +647,6 @@ The following options need to be configured:
time on others. This setting #define's the initial time on others. This setting #define's the initial
value of the "loads_echo" environment variable. value of the "loads_echo" environment variable.
- Kgdb Serial Baudrate: (if CONFIG_CMD_KGDB is defined)
CONFIG_KGDB_BAUDRATE
Select one of the baudrates listed in
CONFIG_SYS_BAUDRATE_TABLE, see below.
- Removal of commands - Removal of commands
If no commands are needed to boot, you can disable If no commands are needed to boot, you can disable
CONFIG_CMDLINE to remove them. In this case, the command line CONFIG_CMDLINE to remove them. In this case, the command line

21
arch/arm/Kconfig
View File

@ -551,11 +551,6 @@ config ARCH_AT91
select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
select SPL_SEPARATE_BSS if SPL select SPL_SEPARATE_BSS if SPL
config TARGET_ASPENITE
bool "Support aspenite"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
config ARCH_DAVINCI config ARCH_DAVINCI
bool "TI DaVinci" bool "TI DaVinci"
select CPU_ARM926EJS select CPU_ARM926EJS
@ -605,11 +600,6 @@ config TARGET_STV0991
select SPI_FLASH select SPI_FLASH
imply CMD_DM imply CMD_DM
config TARGET_FLEA3
bool "Support flea3"
select CPU_ARM1136
select GPIO_EXTRA_HEADER
config ARCH_BCM283X config ARCH_BCM283X
bool "Broadcom BCM283X family" bool "Broadcom BCM283X family"
select DM select DM
@ -864,13 +854,6 @@ config ARCH_MX23
select PL011_SERIAL select PL011_SERIAL
select SUPPORT_SPL select SUPPORT_SPL
config ARCH_MX25
bool "NXP MX25"
select CPU_ARM926EJS
select GPIO_EXTRA_HEADER
select MACH_IMX
imply MXC_GPIO
config ARCH_MX28 config ARCH_MX28
bool "NXP i.MX28 family" bool "NXP i.MX28 family"
select CPU_ARM926EJS select CPU_ARM926EJS
@ -2067,8 +2050,6 @@ source "arch/arm/mach-octeontx2/Kconfig"
source "arch/arm/cpu/armv7/ls102xa/Kconfig" source "arch/arm/cpu/armv7/ls102xa/Kconfig"
source "arch/arm/mach-imx/mx2/Kconfig"
source "arch/arm/mach-imx/mx3/Kconfig" source "arch/arm/mach-imx/mx3/Kconfig"
source "arch/arm/mach-imx/mx5/Kconfig" source "arch/arm/mach-imx/mx5/Kconfig"
@ -2149,8 +2130,6 @@ source "board/armltd/total_compute/Kconfig"
source "board/bosch/shc/Kconfig" source "board/bosch/shc/Kconfig"
source "board/bosch/guardian/Kconfig" source "board/bosch/guardian/Kconfig"
source "board/CarMediaLab/flea3/Kconfig"
source "board/Marvell/aspenite/Kconfig"
source "board/Marvell/octeontx/Kconfig" source "board/Marvell/octeontx/Kconfig"
source "board/Marvell/octeontx2/Kconfig" source "board/Marvell/octeontx2/Kconfig"
source "board/armltd/vexpress/Kconfig" source "board/armltd/vexpress/Kconfig"

2
arch/arm/Makefile
View File

@ -111,7 +111,7 @@ libs-y += arch/arm/cpu/
libs-y += arch/arm/lib/ libs-y += arch/arm/lib/
ifeq ($(CONFIG_SPL_BUILD),y) ifeq ($(CONFIG_SPL_BUILD),y)
ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_MX35)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt)) ifneq (,$(CONFIG_MX23)$(CONFIG_MX28)$(filter $(SOC), mx25 mx5 mx6 mx7 mx35 imx8m imx8 imx8ulp imxrt))
libs-y += arch/arm/mach-imx/ libs-y += arch/arm/mach-imx/
endif endif
else else

1
arch/arm/cpu/arm1136/Makefile
View File

@ -7,4 +7,3 @@ extra-y = start.o
obj-y += ../arm11/ obj-y += ../arm11/
obj-$(CONFIG_MX31) += mx31/ obj-$(CONFIG_MX31) += mx31/
obj-$(CONFIG_MX35) += mx35/

11
arch/arm/cpu/arm1136/mx35/Makefile
View File

@ -1,11 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
obj-y += generic.o
obj-y += timer.o
obj-y += mx35_sdram.o
obj-y += relocate.o

530
arch/arm/cpu/arm1136/mx35/generic.c
View File

@ -1,530 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <clock_legacy.h>
#include <command.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
#endif
#include <netdev.h>
#include <spl.h>
#define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
#define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
#define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
#define CLK_CODE_PATH(c) ((c) & 0xFF)
#define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
#ifdef CONFIG_FSL_ESDHC_IMX
DECLARE_GLOBAL_DATA_PTR;
#endif
static int g_clk_mux_auto[8] = {
CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
};
static int g_clk_mux_consumer[16] = {
CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
-1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
-1, -1, CLK_CODE(4, 2, 0), -1,
};
static int hsp_div_table[3][16] = {
{4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
{-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
{3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
};
u32 get_cpu_rev(void)
{
int reg;
struct iim_regs *iim =
(struct iim_regs *)IIM_BASE_ADDR;
reg = readl(&iim->iim_srev);
if (!reg) {
reg = readw(ROMPATCH_REV);
reg <<= 4;
} else {
reg += CHIP_REV_1_0;
}
return 0x35000 + (reg & 0xFF);
}
static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
{
int *pclk_mux;
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
} else {
pclk_mux = g_clk_mux_auto +
((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
}
if ((*pclk_mux) == -1)
return -1;
if (fi && fd) {
if (!CLK_CODE_PATH(*pclk_mux)) {
*fi = *fd = 1;
return CLK_CODE_ARM(*pclk_mux);
}
if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
*fi = 3;
*fd = 4;
} else {
*fi = 2;
*fd = 3;
}
}
return CLK_CODE_ARM(*pclk_mux);
}
static int get_ahb_div(u32 pdr0)
{
int *pclk_mux;
pclk_mux = g_clk_mux_consumer +
((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
if ((*pclk_mux) == -1)
return -1;
return CLK_CODE_AHB(*pclk_mux);
}
static u32 decode_pll(u32 reg, u32 infreq)
{
u32 mfi = (reg >> 10) & 0xf;
s32 mfn = reg & 0x3ff;
u32 mfd = (reg >> 16) & 0x3ff;
u32 pd = (reg >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
mfd * pd);
}
static u32 get_mcu_main_clk(void)
{
u32 arm_div = 0, fi = 0, fd = 0;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
return fi / (arm_div * fd);
}
static u32 get_ipg_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
return freq / (get_ahb_div(pdr0) * 2);
}
static u32 get_ipg_per_clk(void)
{
u32 freq = get_mcu_main_clk();
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr0 = readl(&ccm->pdr0);
u32 pdr4 = readl(&ccm->pdr4);
u32 div;
if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
div = CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_PER0_PODF_MASK,
MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
} else {
div = CCM_GET_DIVIDER(pdr0,
MXC_CCM_PDR0_PER_PODF_MASK,
MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
div *= get_ahb_div(pdr0);
}
return freq / div;
}
u32 imx_get_uartclk(void)
{
u32 freq;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 pdr4 = readl(&ccm->pdr4);
if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
freq = get_mcu_main_clk();
else
freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
freq /= CCM_GET_DIVIDER(pdr4,
MXC_CCM_PDR4_UART_PODF_MASK,
MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
return freq;
}
unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
{
u32 nfc_pdf, hsp_podf;
u32 pll, ret_val = 0, usb_podf;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 reg = readl(&ccm->pdr0);
u32 reg4 = readl(&ccm->pdr4);
reg |= 0x1;
switch (clk) {
case CPU_CLK:
ret_val = get_mcu_main_clk();
break;
case AHB_CLK:
ret_val = get_mcu_main_clk();
break;
case HSP_CLK:
if (reg & CLKMODE_CONSUMER) {
hsp_podf = (reg >> 20) & 0x3;
pll = get_mcu_main_clk();
hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
if (hsp_podf > 0) {
ret_val = pll / hsp_podf;
} else {
puts("mismatch HSP with ARM clock setting\n");
ret_val = 0;
}
} else {
ret_val = get_mcu_main_clk();
}
break;
case IPG_CLK:
ret_val = get_ipg_clk();
break;
case IPG_PER_CLK:
ret_val = get_ipg_per_clk();
break;
case NFC_CLK:
nfc_pdf = (reg4 >> 28) & 0xF;
pll = get_mcu_main_clk();
/* AHB/nfc_pdf */
ret_val = pll / (nfc_pdf + 1);
break;
case USB_CLK:
usb_podf = (reg4 >> 22) & 0x3F;
if (reg4 & 0x200)
pll = get_mcu_main_clk();
else
pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
ret_val = pll / (usb_podf + 1);
break;
default:
printf("Unknown clock: %d\n", clk);
break;
}
return ret_val;
}
unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
{
u32 ret_val = 0, pdf, pre_pdf, clk_sel;
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 mpdr2 = readl(&ccm->pdr2);
u32 mpdr3 = readl(&ccm->pdr3);
u32 mpdr4 = readl(&ccm->pdr4);
switch (clk) {
case UART1_BAUD:
case UART2_BAUD:
case UART3_BAUD:
clk_sel = mpdr3 & (1 << 14);
pdf = (mpdr4 >> 10) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SSI1_BAUD:
pre_pdf = (mpdr2 >> 24) & 0x7;
pdf = mpdr2 & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case SSI2_BAUD:
pre_pdf = (mpdr2 >> 27) & 0x7;
pdf = (mpdr2 >> 8) & 0x3F;
clk_sel = mpdr2 & (1 << 6);
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case CSI_BAUD:
clk_sel = mpdr2 & (1 << 7);
pdf = (mpdr2 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case MSHC_CLK:
pre_pdf = readl(&ccm->pdr1);
clk_sel = (pre_pdf & 0x80);
pdf = (pre_pdf >> 22) & 0x3F;
pre_pdf = (pre_pdf >> 28) & 0x7;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
case ESDHC1_CLK:
clk_sel = mpdr3 & 0x40;
pdf = mpdr3 & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC2_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 8) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case ESDHC3_CLK:
clk_sel = mpdr3 & 0x40;
pdf = (mpdr3 >> 16) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
break;
case SPDIF_CLK:
clk_sel = mpdr3 & 0x400000;
pre_pdf = (mpdr3 >> 29) & 0x7;
pdf = (mpdr3 >> 23) & 0x3F;
ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
((pre_pdf + 1) * (pdf + 1));
break;
default:
printf("%s(): This clock: %d not supported yet\n",
__func__, clk);
break;
}
return ret_val;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
switch (clk) {
case MXC_ARM_CLK:
return get_mcu_main_clk();
case MXC_AHB_CLK:
break;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
case MXC_ESDHC1_CLK:
return mxc_get_peri_clock(ESDHC1_CLK);
case MXC_ESDHC2_CLK:
return mxc_get_peri_clock(ESDHC2_CLK);
case MXC_ESDHC3_CLK:
return mxc_get_peri_clock(ESDHC3_CLK);
case MXC_USB_CLK:
return mxc_get_main_clock(USB_CLK);
case MXC_FEC_CLK:
return get_ipg_clk();
case MXC_CSPI_CLK:
return get_ipg_clk();
}
return -1;
}
#ifdef CONFIG_FEC_MXC
/*
* The MX35 has no fuse for MAC, return a NULL MAC
*/
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
memset(mac, 0, 6);
}
u32 imx_get_fecclk(void)
{
return mxc_get_clock(MXC_IPG_CLK);
}
#endif
int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
u32 cpufreq = get_mcu_main_clk();
printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
printf("ipg clock : %dHz\n", get_ipg_clk());
printf("ipg per clock : %dHz\n", get_ipg_per_clk());
printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
return 0;
}
U_BOOT_CMD(
clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
"display clocks",
""
);
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0F;
switch (cause) {
case 0x0000:
return "POR";
case 0x0002:
return "JTAG";
case 0x0004:
return "RST";
case 0x0008:
return "WDOG";
default:
return "unknown reset";
}
}
int print_cpuinfo(void)
{
u32 srev = get_cpu_rev();
printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
(srev & 0xF0) >> 4, (srev & 0x0F),
get_mcu_main_clk() / 1000000);
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
int rc = -ENODEV;
#if defined(CONFIG_FEC_MXC)
rc = fecmxc_initialize(bis);
#endif
return rc;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#define RCSR_MEM_CTL_WEIM 0
#define RCSR_MEM_CTL_NAND 1
#define RCSR_MEM_CTL_ATA 2
#define RCSR_MEM_CTL_EXPANSION 3
#define RCSR_MEM_TYPE_NOR 0
#define RCSR_MEM_TYPE_ONENAND 2
#define RCSR_MEM_TYPE_SD 0
#define RCSR_MEM_TYPE_I2C 2
#define RCSR_MEM_TYPE_SPI 3
u32 spl_boot_device(void)
{
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 rcsr = readl(&ccm->rcsr);
u32 mem_type, mem_ctl;
/* In external mode, no boot device is returned */
if ((rcsr >> 10) & 0x03)
return BOOT_DEVICE_NONE;
mem_ctl = (rcsr >> 25) & 0x03;
mem_type = (rcsr >> 23) & 0x03;
switch (mem_ctl) {
case RCSR_MEM_CTL_WEIM:
switch (mem_type) {
case RCSR_MEM_TYPE_NOR:
return BOOT_DEVICE_NOR;
case RCSR_MEM_TYPE_ONENAND:
return BOOT_DEVICE_ONENAND;
default:
return BOOT_DEVICE_NONE;
}
case RCSR_MEM_CTL_NAND:
return BOOT_DEVICE_NAND;
case RCSR_MEM_CTL_EXPANSION:
switch (mem_type) {
case RCSR_MEM_TYPE_SD:
return BOOT_DEVICE_MMC1;
case RCSR_MEM_TYPE_I2C:
return BOOT_DEVICE_I2C;
case RCSR_MEM_TYPE_SPI:
return BOOT_DEVICE_SPI;
default:
return BOOT_DEVICE_NONE;
}
}
return BOOT_DEVICE_NONE;
}

120
arch/arm/cpu/arm1136/mx35/mx35_sdram.c
View File

@ -1,120 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2012, Stefano Babic <sbabic@denx.de>
*/
#include <asm/io.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <linux/types.h>
#include <asm/arch/sys_proto.h>
#define ESDCTL_DDR2_EMR2 0x04000000
#define ESDCTL_DDR2_EMR3 0x06000000
#define ESDCTL_PRECHARGE 0x00000400
#define ESDCTL_DDR2_EN_DLL 0x02000400
#define ESDCTL_DDR2_RESET_DLL 0x00000333
#define ESDCTL_DDR2_MR 0x00000233
#define ESDCTL_DDR2_OCD_DEFAULT 0x02000780
enum {
SMODE_NORMAL = 0,
SMODE_PRECHARGE,
SMODE_AUTO_REFRESH,
SMODE_LOAD_REG,
SMODE_MANUAL_REFRESH
};
#define set_mode(x, en, m) (x | (en << 31) | (m << 28))
static inline void dram_wait(unsigned int count)
{
volatile unsigned int wait = count;
while (wait--)
;
}
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config,
u32 row, u32 col, u32 dsize, u32 refresh)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
u32 *cfg_reg, *ctl_reg;
u32 val;
u32 ctlval;
switch (start_address) {
case CSD0_BASE_ADDR:
cfg_reg = &esdc->esdcfg0;
ctl_reg = &esdc->esdctl0;
break;
case CSD1_BASE_ADDR:
cfg_reg = &esdc->esdcfg1;
ctl_reg = &esdc->esdctl1;
break;
default:
return;
}
/* The MX35 supports 11 up to 14 rows */
if (row < 11 || row > 14 || col < 8 || col > 10)
return;
ctlval = (row - 11) << 24 | (col - 8) << 20 | (dsize << 16);
/* Initialize MISC register for DDR2 */
val = ESDC_MISC_RST | ESDC_MISC_MDDR_EN | ESDC_MISC_MDDR_DL_RST |
ESDC_MISC_DDR_EN | ESDC_MISC_DDR2_EN;
writel(val, &esdc->esdmisc);
val &= ~(ESDC_MISC_RST | ESDC_MISC_MDDR_DL_RST);
writel(val, &esdc->esdmisc);
/*
* according to DDR2 specs, wait a while before
* the PRECHARGE_ALL command
*/
dram_wait(0x20000);
/* Load DDR2 config and timing */
writel(ddr2_config, cfg_reg);
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Load mode */
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_EMR2); /* EMRS2 */
writeb(0xda, start_address + ESDCTL_DDR2_EMR3); /* EMRS3 */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
writeb(0xda, start_address + ESDCTL_DDR2_RESET_DLL); /* Reset DLL */
/* Precharge ALL */
writel(set_mode(ctlval, 1, SMODE_PRECHARGE),
ctl_reg);
writel(0xda, start_address + ESDCTL_PRECHARGE);
/* Set mode auto refresh : at least two refresh are required */
writel(set_mode(ctlval, 1, SMODE_AUTO_REFRESH),
ctl_reg);
writel(0xda, start_address);
writel(0xda, start_address);
writel(set_mode(ctlval, 1, SMODE_LOAD_REG),
ctl_reg);
writeb(0xda, start_address + ESDCTL_DDR2_MR);
writeb(0xda, start_address + ESDCTL_DDR2_OCD_DEFAULT);
/* OCD mode exit */
writeb(0xda, start_address + ESDCTL_DDR2_EN_DLL); /* Enable DLL */
/* Set normal mode */
writel(set_mode(ctlval, 1, SMODE_NORMAL) | refresh,
ctl_reg);
dram_wait(0x20000);
/* Do not set delay lines, only for MDDR */
}

22
arch/arm/cpu/arm1136/mx35/relocate.S
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@ -1,22 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX35-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX35 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

46
arch/arm/cpu/arm1136/mx35/timer.c
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@ -1,46 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2007
* Sascha Hauer, Pengutronix
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/ptrace.h>
/* General purpose timers bitfields */
#define GPTCR_SWR (1<<15) /* Software reset */
#define GPTCR_FRR (1<<9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */
#define GPTCR_TEN (1) /* Timer enable */
/*
* nothing really to do with interrupts, just starts up a counter.
* The 32KHz 32-bit timer overruns in 134217 seconds
*/
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)GPT1_BASE_ADDR;
struct ccm_regs *ccm = (struct ccm_regs *)CCM_BASE_ADDR;
/* setup GP Timer 1 */
writel(GPTCR_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | 3 << MXC_CCM_CGR1_GPT_OFFSET, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPTCR_CLKSOURCE_32 | GPTCR_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPTCR_TEN, &gpt->ctrl);
return 0;
}

2
arch/arm/cpu/arm926ejs/Makefile
View File

@ -12,8 +12,6 @@ extra-y :=
endif endif
endif endif
obj-$(CONFIG_ARMADA100) += armada100/
obj-$(CONFIG_MX25) += mx25/
obj-$(CONFIG_MX27) += mx27/ obj-$(CONFIG_MX27) += mx27/
obj-$(if $(filter mxs,$(SOC)),y) += mxs/ obj-$(if $(filter mxs,$(SOC)),y) += mxs/
obj-$(if $(filter spear,$(SOC)),y) += spear/ obj-$(if $(filter spear,$(SOC)),y) += spear/

7
arch/arm/cpu/arm926ejs/armada100/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
obj-y = cpu.o timer.o dram.o

93
arch/arm/cpu/arm926ejs/armada100/cpu.c
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@ -1,93 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#define UARTCLK14745KHZ (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
#define SET_MRVL_ID (1<<8)
#define L2C_RAM_SEL (1<<4)
int arch_cpu_init(void)
{
u32 val;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
/* set SEL_MRVL_ID bit in ARMADA100_CPU_CONF register */
val = readl(&cpuregs->cpu_conf);
val = val | SET_MRVL_ID;
writel(val, &cpuregs->cpu_conf);
/* Enable Clocks for all hardware units */
writel(0xFFFFFFFF, &mpmu->acgr);
/* Turn on AIB and AIB-APB Functional clock */
writel(APBC_APBCLK | APBC_FNCLK, &apb1clkres->aib);
/* ensure L2 cache is not mapped as SRAM */
val = readl(&cpuregs->cpu_conf);
val = val & ~(L2C_RAM_SEL);
writel(val, &cpuregs->cpu_conf);
/* Enable GPIO clock */
writel(APBC_APBCLK, &apb1clkres->gpio);
#ifdef CONFIG_I2C_MV
/* Enable general I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi0);
/* Enable power I2C clock */
writel(APBC_RST | APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
writel(APBC_FNCLK | APBC_APBCLK, &apb1clkres->twsi1);
#endif
/*
* Enable Functional and APB clock at 14.7456MHz
* for configured UART console
*/
#if (CONFIG_SYS_NS16550_COM1 == ARMD1_UART3_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart3);
#elif (CONFIG_SYS_NS16550_COM1 == ARMD1_UART2_BASE)
writel(UARTCLK14745KHZ, &apb1clkres->uart2);
#else
writel(UARTCLK14745KHZ, &apb1clkres->uart1);
#endif
icache_enable();
return 0;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void)
{
u32 id;
struct armd1cpu_registers *cpuregs =
(struct armd1cpu_registers *) ARMD1_CPU_BASE;
id = readl(&cpuregs->chip_id);
printf("SoC: Armada 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
return 0;
}
#endif
#ifdef CONFIG_I2C_MV
void i2c_clk_enable(void)
{
}
#endif

117
arch/arm/cpu/arm926ejs/armada100/dram.c
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@ -1,117 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* ARMADA100 DRAM controller supports upto 8 banks
* for chip select 0 and 1
*/
/*
* DDR Memory Control Registers
* Refer Datasheet Appendix A.17
*/
struct armd1ddr_map_registers {
u32 cs; /* Memory Address Map Register -CS */
u32 pad[3];
};
struct armd1ddr_registers {
u8 pad[0x100 - 0x000];
struct armd1ddr_map_registers mmap[2];
};
/*
* armd1_sdram_base - reads SDRAM Base Address Register
*/
u32 armd1_sdram_base(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
return result;
}
/*
* armd1_sdram_size - reads SDRAM size
*/
u32 armd1_sdram_size(int chip_sel)
{
struct armd1ddr_registers *ddr_regs =
(struct armd1ddr_registers *)ARMD1_DRAM_BASE;
u32 result = 0;
u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
if (!CS_valid)
return 0;
result = readl(&ddr_regs->mmap[chip_sel].cs);
result = (result >> 16) & 0xF;
if (result < 0x7) {
printf("Unknown DRAM Size\n");
return -1;
} else {
return ((0x8 << (result - 0x7)) * 1024 * 1024);
}
}
int dram_init(void)
{
int i;
gd->ram_size = 0;
for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
gd->bd->bi_dram[i].start = armd1_sdram_base(i);
gd->bd->bi_dram[i].size = armd1_sdram_size(i);
/*
* It is assumed that all memory banks are consecutive
* and without gaps.
* If the gap is found, ram_size will be reported for
* consecutive memory only
*/
if (gd->bd->bi_dram[i].start != gd->ram_size)
break;
gd->ram_size += gd->bd->bi_dram[i].size;
}
for (; i < CONFIG_NR_DRAM_BANKS; i++) {
/* If above loop terminated prematurely, we need to set
* remaining banks' start address & size as 0. Otherwise other
* u-boot functions and Linux kernel gets wrong values which
* could result in crash */
gd->bd->bi_dram[i].start = 0;
gd->bd->bi_dram[i].size = 0;
}
return 0;
}
/*
* If this function is not defined here,
* board.c alters dram bank zero configuration defined above.
*/
int dram_init_banksize(void)
{
dram_init();
return 0;
}

198
arch/arm/cpu/arm926ejs/armada100/timer.c
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@ -1,198 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <init.h>
#include <time.h>
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/global_data.h>
#include <linux/delay.h>
/*
* Timer registers
* Refer Section A.6 in Datasheet
*/
struct armd1tmr_registers {
u32 clk_ctrl; /* Timer clk control reg */
u32 match[9]; /* Timer match registers */
u32 count[3]; /* Timer count registers */
u32 status[3];
u32 ie[3];
u32 preload[3]; /* Timer preload value */
u32 preload_ctrl[3];
u32 wdt_match_en;
u32 wdt_match_r;
u32 wdt_val;
u32 wdt_sts;
u32 icr[3];
u32 wdt_icr;
u32 cer; /* Timer count enable reg */
u32 cmr;
u32 ilr[3];
u32 wcr;
u32 wfar;
u32 wsar;
u32 cvwr;
};
#define TIMER 0 /* Use TIMER 0 */
/* Each timer has 3 match registers */
#define MATCH_CMP(x) ((3 * TIMER) + x)
#define TIMER_LOAD_VAL 0xffffffff
#define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR;
/* Using gd->arch.tbu from timestamp and gd->arch.tbl for lastdec */
/* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same
* register after it captures counter value.
*/
ulong read_timer(void)
{
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
volatile int loop=100;
writel(COUNT_RD_REQ, &armd1timers->cvwr);
while (loop--);
return(readl(&armd1timers->cvwr));
}
static ulong get_timer_masked(void)
{
ulong now = read_timer();
if (now >= gd->arch.tbl) {
/* normal mode */
gd->arch.tbu += now - gd->arch.tbl;
} else {
/* we have an overflow ... */
gd->arch.tbu += now + TIMER_LOAD_VAL - gd->arch.tbl;
}
gd->arch.tbl = now;
return gd->arch.tbu;
}
ulong get_timer(ulong base)
{
return ((get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) -
base);
}
void __udelay(unsigned long usec)
{
ulong delayticks;
ulong endtime;
delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
endtime = get_timer_masked() + delayticks;
while (get_timer_masked() < endtime);
}
/*
* init the Timer
*/
int timer_init(void)
{
struct armd1apb1_registers *apb1clkres =
(struct armd1apb1_registers *) ARMD1_APBC1_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
/* Enable Timer clock at 3.25 MHZ */
writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(3), &apb1clkres->timers);
/* load value into timer */
writel(0x0, &armd1timers->clk_ctrl);
/* Use Timer 0 Match Resiger 0 */
writel(TIMER_LOAD_VAL, &armd1timers->match[MATCH_CMP(0)]);
/* Preload value is 0 */
writel(0x0, &armd1timers->preload[TIMER]);
/* Enable match comparator 0 for Timer 0 */
writel(0x1, &armd1timers->preload_ctrl[TIMER]);
/* Enable timer 0 */
writel(0x1, &armd1timers->cer);
/* init the gd->arch.tbu and gd->arch.tbl value */
gd->arch.tbl = read_timer();
gd->arch.tbu = 0;
return 0;
}
#define MPMU_APRR_WDTR (1<<4)
#define TMR_WFAR 0xbaba /* WDT Register First key */
#define TMP_WSAR 0xeb10 /* WDT Register Second key */
/*
* This function uses internal Watchdog Timer
* based reset mechanism.
* Steps to write watchdog registers (protected access)
* 1. Write key value to TMR_WFAR reg.
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
void reset_cpu(void)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
struct armd1tmr_registers *armd1timers =
(struct armd1tmr_registers *) ARMD1_TIMER_BASE;
u32 val;
/* negate hardware reset to the WDT after system reset */
val = readl(&mpmu->aprr);
val = val | MPMU_APRR_WDTR;
writel(val, &mpmu->aprr);
/* reset/enable WDT clock */
writel(APBC_APBCLK | APBC_FNCLK | APBC_RST, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
writel(APBC_APBCLK | APBC_FNCLK, &mpmu->wdtpcr);
readl(&mpmu->wdtpcr);
/* clear previous WDT status */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0, &armd1timers->wdt_sts);
/* set match counter */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0xf, &armd1timers->wdt_match_r);
/* enable WDT reset */
writel(TMR_WFAR, &armd1timers->wfar);
writel(TMP_WSAR, &armd1timers->wsar);
writel(0x3, &armd1timers->wdt_match_en);
while(1);
}
/*
* This function is derived from PowerPC code (read timebase as long long).
* On ARM it just returns the timer value.
*/
unsigned long long get_ticks(void)
{
return get_timer(0);
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return (ulong)CONFIG_SYS_HZ;
}

7
arch/arm/cpu/arm926ejs/mx25/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
obj-y += generic.o timer.o reset.o relocate.o

274
arch/arm/cpu/arm926ejs/mx25/generic.c
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@ -1,274 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on mx27/generic.c:
* Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
* Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
*/
#include <common.h>
#include <clock_legacy.h>
#include <div64.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <vsprintf.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <asm/arch-imx/cpu.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#ifdef CONFIG_FSL_ESDHC_IMX
#include <fsl_esdhc_imx.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
mfn = mfn >= 512 ? mfn - 1024 : mfn;
mfd += 1;
pd += 1;
return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
mfd * pd);
}
static ulong imx_get_mpllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
static ulong imx_get_upllclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = MXC_HCLK;
return imx_decode_pll(readl(&ccm->upctl), fref);
}
static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_mpllclk();
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong fref = imx_get_armclk();
ulong div;
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
return fref / div;
}
static ulong imx_get_ipgclk(void)
{
return imx_get_ahbclk() / 2;
}
static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
imx_get_ahbclk();
ulong div;
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
return fref / div;
}
int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
ulong div = (fref + freq - 1) / freq;
if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
return -EINVAL;
clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
div << CCM_PERCLK_SHIFT(clk));
if (from_upll)
setbits_le32(&ccm->mcr, 1 << clk);
else
clrbits_le32(&ccm->mcr, 1 << clk);
return 0;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
{
if (clk >= MXC_CLK_NUM)
return -1;
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
case MXC_AHB_CLK:
return imx_get_ahbclk();
case MXC_IPG_CLK:
case MXC_CSPI_CLK:
case MXC_FEC_CLK:
return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
}
}
u32 get_cpu_rev(void)
{
u32 srev;
u32 system_rev = 0x25000;
/* read SREV register from IIM module */
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
srev = readl(&iim->iim_srev);
switch (srev) {
case 0x00:
system_rev |= CHIP_REV_1_0;
break;
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
case 0x02:
system_rev |= CHIP_REV_1_2;
break;
default:
system_rev |= 0x8000;
break;
}
return system_rev;
}
#if defined(CONFIG_DISPLAY_CPUINFO)
static char *get_reset_cause(void)
{
/* read RCSR register from CCM module */
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
u32 cause = readl(&ccm->rcsr) & 0x0f;
if (cause == 0)
return "POR";
else if (cause == 1)
return "RST";
else if ((cause & 2) == 2)
return "WDOG";
else if ((cause & 4) == 4)
return "SW RESET";
else if ((cause & 8) == 8)
return "JTAG";
else
return "unknown reset";
}
int print_cpuinfo(void)
{
char buf[32];
u32 cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
((cpurev & 0x8000) ? " unknown" : ""),
strmhz(buf, imx_get_armclk()));
printf("Reset cause: %s\n", get_reset_cause());
return 0;
}
#endif
#if defined(CONFIG_FEC_MXC)
/*
* Initializes on-chip ethernet controllers.
* to override, implement board_eth_init()
*/
int cpu_eth_init(struct bd_info *bis)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val = readl(&ccm->cgr0);
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
}
#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
#endif
#endif
return 0;
}
#ifdef CONFIG_FSL_ESDHC_IMX
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(struct bd_info *bis)
{
return fsl_esdhc_mmc_init(bis);
}
#endif
#ifdef CONFIG_FEC_MXC
void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
{
int i;
struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
struct fuse_bank *bank = &iim->bank[0];
struct fuse_bank0_regs *fuse =
(struct fuse_bank0_regs *)bank->fuse_regs;
for (i = 0; i < 6; i++)
mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
}
#endif /* CONFIG_FEC_MXC */

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arch/arm/cpu/arm926ejs/mx25/relocate.S
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* relocate - i.MX25-specific vector relocation
*
* Copyright (c) 2013 Albert ARIBAUD <albert.u.boot@aribaud.net>
*/
#include <linux/linkage.h>
/*
* The i.MX25 SoC is very specific with respect to exceptions: it
* does not provide RAM at the high vectors address (0xFFFF0000),
* thus only the low address (0x00000000) is useable; but that is
* in ROM, so let's avoid relocating the vectors.
*/
.section .text.relocate_vectors,"ax",%progbits
ENTRY(relocate_vectors)
bx lr
ENDPROC(relocate_vectors)

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arch/arm/cpu/arm926ejs/mx25/reset.c
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// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*/
#include <common.h>
#include <cpu_func.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
writew(0, &regs->wcr);
/* Write Service Sequence */
writew(WSR_UNLOCK1, &regs->wsr);
writew(WSR_UNLOCK2, &regs->wsr);
/* Enable watchdog */
writew(WCR_WDE, &regs->wcr);
while (1) ;
}

50
arch/arm/cpu/arm926ejs/mx25/timer.c
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@ -1,50 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
*
* (C) Copyright 2009
* Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
* Add support for MX25
*/
#include <common.h>
#include <init.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/ptrace.h>
/* nothing really to do with interrupts, just starts up a counter. */
/* The 32KHz 32-bit timer overruns in 134217 seconds */
int timer_init(void)
{
int i;
struct gpt_regs *gpt = (struct gpt_regs *)IMX_GPT1_BASE;
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
/* setup GP Timer 1 */
writel(GPT_CTRL_SWR, &gpt->ctrl);
writel(readl(&ccm->cgr1) | CCM_CGR1_GPT1, &ccm->cgr1);
for (i = 0; i < 100; i++)
writel(0, &gpt->ctrl); /* We have no udelay by now */
writel(0, &gpt->pre); /* prescaler = 1 */
/* Freerun Mode, 32KHz input */
writel(readl(&gpt->ctrl) | GPT_CTRL_CLKSOURCE_32 | GPT_CTRL_FRR,
&gpt->ctrl);
writel(readl(&gpt->ctrl) | GPT_CTRL_TEN, &gpt->ctrl);
return 0;
}

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arch/arm/include/asm/arch-armada100/armada100.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#ifndef _ASM_ARCH_ARMADA100_H
#define _ASM_ARCH_ARMADA100_H
#if defined (CONFIG_ARMADA100)
/* Common APB clock register bit definitions */
#define APBC_APBCLK (1<<0) /* APB Bus Clock Enable */
#define APBC_FNCLK (1<<1) /* Functional Clock Enable */
#define APBC_RST (1<<2) /* Reset Generation */
/* Functional Clock Selection Mask */
#define APBC_FNCLKSEL(x) (((x) & 0xf) << 4)
/* Fast Ethernet Controller Clock register definition */
#define FE_CLK_RST 0x1
#define FE_CLK_ENA 0x8
/* SSP2 Clock Control */
#define SSP2_APBCLK 0x01
#define SSP2_FNCLK 0x02
/* USB Clock/reset control bits */
#define USB_SPH_AXICLK_EN 0x10
#define USB_SPH_AXI_RST 0x02
/* MPMU Clocks */
#define APB2_26M_EN (1 << 20)
#define AP_26M (1 << 4)
/* Register Base Addresses */
#define ARMD1_DRAM_BASE 0xB0000000
#define ARMD1_FEC_BASE 0xC0800000
#define ARMD1_TIMER_BASE 0xD4014000
#define ARMD1_APBC1_BASE 0xD4015000
#define ARMD1_APBC2_BASE 0xD4015800
#define ARMD1_UART1_BASE 0xD4017000
#define ARMD1_UART2_BASE 0xD4018000
#define ARMD1_GPIO_BASE 0xD4019000
#define ARMD1_SSP1_BASE 0xD401B000
#define ARMD1_SSP2_BASE 0xD401C000
#define ARMD1_MFPR_BASE 0xD401E000
#define ARMD1_SSP3_BASE 0xD401F000
#define ARMD1_SSP4_BASE 0xD4020000
#define ARMD1_SSP5_BASE 0xD4021000
#define ARMD1_UART3_BASE 0xD4026000
#define ARMD1_MPMU_BASE 0xD4050000
#define ARMD1_USB_HOST_BASE 0xD4209000
#define ARMD1_APMU_BASE 0xD4282800
#define ARMD1_CPU_BASE 0xD4282C00
#endif /* CONFIG_ARMADA100 */
#endif /* _ASM_ARCH_ARMADA100_H */

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arch/arm/include/asm/arch-armada100/config.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Marvell Semiconductor <www.marvell.com>
* Written-by: Lei Wen <leiwen@marvell.com>
*/
/*
* This file should be included in board config header file.
*
* It supports common definitions for Armada100 platform
*/
#ifndef _ARMD1_CONFIG_H
#define _ARMD1_CONFIG_H
#include <asm/arch/armada100.h>
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */
#define CONFIG_MARVELL_MFP /* Enable mvmfp driver */
#define MV_MFPR_BASE ARMD1_MFPR_BASE
#define MV_UART_CONSOLE_BASE ARMD1_UART1_BASE
#define CONFIG_SYS_NS16550_IER (1 << 6) /* Bit 6 in UART_IER register
represents UART Unit Enable */
#endif /* _ARMD1_CONFIG_H */

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arch/arm/include/asm/arch-armada100/cpu.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>, Contributor: Mahavir Jain <mjain@marvell.com>
*/
#ifndef _ARMADA100CPU_H
#define _ARMADA100CPU_H
#include <asm/io.h>
#include <asm/system.h>
/*
* Main Power Management (MPMU) Registers
* Refer Datasheet Appendix A.8
*/
struct armd1mpmu_registers {
u8 pad0[0x08 - 0x00];
u32 fccr; /*0x0008*/
u32 pocr; /*0x000c*/
u32 posr; /*0x0010*/
u32 succr; /*0x0014*/
u8 pad1[0x030 - 0x014 - 4];
u32 gpcr; /*0x0030*/
u8 pad2[0x200 - 0x030 - 4];
u32 wdtpcr; /*0x0200*/
u8 pad3[0x1000 - 0x200 - 4];
u32 apcr; /*0x1000*/
u32 apsr; /*0x1004*/
u8 pad4[0x1020 - 0x1004 - 4];
u32 aprr; /*0x1020*/
u32 acgr; /*0x1024*/
u32 arsr; /*0x1028*/
};
/*
* Application Subsystem Power Management
* Refer Datasheet Appendix A.9
*/
struct armd1apmu_registers {
u32 pcr; /* 0x000 */
u32 ccr; /* 0x004 */
u32 pad1;
u32 ccsr; /* 0x00C */
u32 fc_timer; /* 0x010 */
u32 pad2;
u32 ideal_cfg; /* 0x018 */
u8 pad3[0x04C - 0x018 - 4];
u32 lcdcrc; /* 0x04C */
u32 cciccrc; /* 0x050 */
u32 sd1crc; /* 0x054 */
u32 sd2crc; /* 0x058 */
u32 usbcrc; /* 0x05C */
u32 nfccrc; /* 0x060 */
u32 dmacrc; /* 0x064 */
u32 pad4;
u32 buscrc; /* 0x06C */
u8 pad5[0x07C - 0x06C - 4];
u32 wake_clr; /* 0x07C */
u8 pad6[0x090 - 0x07C - 4];
u32 core_status; /* 0x090 */
u32 rfsc; /* 0x094 */
u32 imr; /* 0x098 */
u32 irwc; /* 0x09C */
u32 isr; /* 0x0A0 */
u8 pad7[0x0B0 - 0x0A0 - 4];
u32 mhst; /* 0x0B0 */
u32 msr; /* 0x0B4 */
u8 pad8[0x0C0 - 0x0B4 - 4];
u32 msst; /* 0x0C0 */
u32 pllss; /* 0x0C4 */
u32 smb; /* 0x0C8 */
u32 gccrc; /* 0x0CC */
u8 pad9[0x0D4 - 0x0CC - 4];
u32 smccrc; /* 0x0D4 */
u32 pad10;
u32 xdcrc; /* 0x0DC */
u32 sd3crc; /* 0x0E0 */
u32 sd4crc; /* 0x0E4 */
u8 pad11[0x0F0 - 0x0E4 - 4];
u32 cfcrc; /* 0x0F0 */
u32 mspcrc; /* 0x0F4 */
u32 cmucrc; /* 0x0F8 */
u32 fecrc; /* 0x0FC */
u32 pciecrc; /* 0x100 */
u32 epdcrc; /* 0x104 */
};
/*
* APB1 Clock Reset/Control Registers
* Refer Datasheet Appendix A.10
*/
struct armd1apb1_registers {
u32 uart1; /*0x000*/
u32 uart2; /*0x004*/
u32 gpio; /*0x008*/
u32 pwm1; /*0x00c*/
u32 pwm2; /*0x010*/
u32 pwm3; /*0x014*/
u32 pwm4; /*0x018*/
u8 pad0[0x028 - 0x018 - 4];
u32 rtc; /*0x028*/
u32 twsi0; /*0x02c*/
u32 kpc; /*0x030*/
u32 timers; /*0x034*/
u8 pad1[0x03c - 0x034 - 4];
u32 aib; /*0x03c*/
u32 sw_jtag; /*0x040*/
u32 timer1; /*0x044*/
u32 onewire; /*0x048*/
u8 pad2[0x050 - 0x048 - 4];
u32 asfar; /*0x050 AIB Secure First Access Reg*/
u32 assar; /*0x054 AIB Secure Second Access Reg*/
u8 pad3[0x06c - 0x054 - 4];
u32 twsi1; /*0x06c*/
u32 uart3; /*0x070*/
u8 pad4[0x07c - 0x070 - 4];
u32 timer2; /*0x07C*/
u8 pad5[0x084 - 0x07c - 4];
u32 ac97; /*0x084*/
};
/*
* APB2 Clock Reset/Control Registers
* Refer Datasheet Appendix A.11
*/
struct armd1apb2_registers {
u32 pad1[0x01C - 0x000];
u32 ssp1_clkrst; /* 0x01C */
u32 ssp2_clkrst; /* 0x020 */
u32 pad2[0x04C - 0x020 - 4];
u32 ssp3_clkrst; /* 0x04C */
u32 pad3[0x058 - 0x04C - 4];
u32 ssp4_clkrst; /* 0x058 */
u32 ssp5_clkrst; /* 0x05C */
};
/*
* CPU Interface Registers
* Refer Datasheet Appendix A.2
*/
struct armd1cpu_registers {
u32 chip_id; /* Chip Id Reg */
u32 pad;
u32 cpu_conf; /* CPU Conf Reg */
u32 pad1;
u32 cpu_sram_spd; /* CPU SRAM Speed Reg */
u32 pad2;
u32 cpu_l2c_spd; /* CPU L2cache Speed Conf */
u32 mcb_conf; /* MCB Conf Reg */
u32 sys_boot_ctl; /* Sytem Boot Control */
};
/*
* Functions
*/
u32 armd1_sdram_base(int);
u32 armd1_sdram_size(int);
#endif /* _ARMADA100CPU_H */

31
arch/arm/include/asm/arch-armada100/gpio.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
*/
#ifndef _ASM_ARCH_GPIO_H
#define _ASM_ARCH_GPIO_H
#include <asm/types.h>
#include <asm/arch/armada100.h>
#define GPIO_HIGH 1
#define GPIO_LOW 0
#define GPIO_TO_REG(gp) (gp >> 5)
#define GPIO_TO_BIT(gp) (1 << (gp & 0x1F))
#define GPIO_VAL(gp, val) ((val >> (gp & 0x1F)) & 0x01)
static inline void *get_gpio_base(int bank)
{
const unsigned int offset[4] = {0, 4, 8, 0x100};
/* gpio register bank offset - refer Appendix A.36 */
return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
}
#endif /* _ASM_ARCH_GPIO_H */

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arch/arm/include/asm/arch-armada100/mfp.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Based on linux/arch/arm/mach-mpp/include/mfp-pxa168.h
* (C) Copyright 2007
* Marvell Semiconductor <www.marvell.com>
* 2007-08-21: eric miao <eric.miao@marvell.com>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#ifndef __ARMADA100_MFP_H
#define __ARMADA100_MFP_H
/*
* Frequently used MFP Configuration macros for all ARMADA100 family of SoCs
*
* offset, pull,pF, drv,dF, edge,eF ,afn,aF
*/
/* UART1 */
#define MFP107_UART1_TXD (MFP_REG(0x01ac) | MFP_AF1 | MFP_DRIVE_FAST)
#define MFP107_UART1_RXD (MFP_REG(0x01ac) | MFP_AF2 | MFP_DRIVE_FAST)
#define MFP108_UART1_RXD (MFP_REG(0x01b0) | MFP_AF1 | MFP_DRIVE_FAST)
#define MFP108_UART1_TXD (MFP_REG(0x01b0) | MFP_AF2 | MFP_DRIVE_FAST)
#define MFP109_UART1_CTS (MFP_REG(0x01b4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
#define MFP109_UART1_RTS (MFP_REG(0x01b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
#define MFP110_UART1_RTS (MFP_REG(0x01b8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
#define MFP110_UART1_CTS (MFP_REG(0x01b8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
#define MFP111_UART1_RI (MFP_REG(0x01bc) | MFP_AF1 | MFP_DRIVE_MEDIUM)
#define MFP111_UART1_DSR (MFP_REG(0x01bc) | MFP_AF2 | MFP_DRIVE_MEDIUM)
#define MFP112_UART1_DTR (MFP_REG(0x01c0) | MFP_AF1 | MFP_DRIVE_MEDIUM)
#define MFP112_UART1_DCD (MFP_REG(0x01c0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* UART2 */
#define MFP47_UART2_RXD (MFP_REG(0x0028) | MFP_AF6 | MFP_DRIVE_MEDIUM)
#define MFP48_UART2_TXD (MFP_REG(0x002c) | MFP_AF6 | MFP_DRIVE_MEDIUM)
#define MFP88_UART2_RXD (MFP_REG(0x0160) | MFP_AF2 | MFP_DRIVE_MEDIUM)
#define MFP89_UART2_TXD (MFP_REG(0x0164) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* UART3 */
#define MFPO8_UART3_TXD (MFP_REG(0x06c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
#define MFPO9_UART3_RXD (MFP_REG(0x070) | MFP_AF2 | MFP_DRIVE_MEDIUM)
/* I2c */
#define MFP105_CI2C_SDA (MFP_REG(0x1a4) | MFP_AF1 | MFP_DRIVE_MEDIUM)
#define MFP106_CI2C_SCL (MFP_REG(0x1a8) | MFP_AF1 | MFP_DRIVE_MEDIUM)
/* Fast Ethernet */
#define MFP086_ETH_TXCLK (MFP_REG(0x158) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP087_ETH_TXEN (MFP_REG(0x15C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP088_ETH_TXDQ3 (MFP_REG(0x160) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP089_ETH_TXDQ2 (MFP_REG(0x164) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP090_ETH_TXDQ1 (MFP_REG(0x168) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP091_ETH_TXDQ0 (MFP_REG(0x16C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP092_ETH_CRS (MFP_REG(0x170) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP093_ETH_COL (MFP_REG(0x174) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP094_ETH_RXCLK (MFP_REG(0x178) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP095_ETH_RXER (MFP_REG(0x17C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP096_ETH_RXDQ3 (MFP_REG(0x180) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP097_ETH_RXDQ2 (MFP_REG(0x184) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP098_ETH_RXDQ1 (MFP_REG(0x188) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP099_ETH_RXDQ0 (MFP_REG(0x18C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP100_ETH_MDC (MFP_REG(0x190) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP101_ETH_MDIO (MFP_REG(0x194) | MFP_AF5 | MFP_DRIVE_MEDIUM)
#define MFP103_ETH_RXDV (MFP_REG(0x19C) | MFP_AF5 | MFP_DRIVE_MEDIUM)
/* SPI */
#define MFP107_SSP2_RXD (MFP_REG(0x1AC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
#define MFP108_SSP2_TXD (MFP_REG(0x1B0) | MFP_AF4 | MFP_DRIVE_MEDIUM)
#define MFP110_SSP2_CS (MFP_REG(0x1B8) | MFP_AF0 | MFP_DRIVE_MEDIUM)
#define MFP111_SSP2_CLK (MFP_REG(0x1BC) | MFP_AF4 | MFP_DRIVE_MEDIUM)
/* More macros can be defined here... */
#define MFP_PIN_MAX 117
#endif /* __ARMADA100_MFP_H */

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arch/arm/include/asm/arch-armada100/spi.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
*/
#ifndef __ARMADA100_SPI_H_
#define __ARMADA100_SPI_H_
#include <asm/arch/armada100.h>
#define CAT_BASE_ADDR(x) ARMD1_SSP ## x ## _BASE
#define SSP_REG_BASE(x) CAT_BASE_ADDR(x)
/*
* SSP Serial Port Registers
* refer Appendix A.26
*/
struct ssp_reg {
u32 sscr0; /* SSP Control Register 0 - 0x000 */
u32 sscr1; /* SSP Control Register 1 - 0x004 */
u32 sssr; /* SSP Status Register - 0x008 */
u32 ssitr; /* SSP Interrupt Test Register - 0x00C */
u32 ssdr; /* SSP Data Register - 0x010 */
u32 pad1[5];
u32 ssto; /* SSP Timeout Register - 0x028 */
u32 sspsp; /* SSP Programmable Serial Protocol Register - 0x02C */
u32 sstsa; /* SSP TX Timeslot Active Register - 0x030 */
u32 ssrsa; /* SSP RX Timeslot Active Register - 0x034 */
u32 sstss; /* SSP Timeslot Status Register - 0x038 */
};
#define DEFAULT_WORD_LEN 8
#define SSP_FLUSH_NUM 0x2000
#define RX_THRESH_DEF 8
#define TX_THRESH_DEF 8
#define TIMEOUT_DEF 1000
#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity
setting */
#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
#define SSCR1_TFT 0x03c0 /* Transmit FIFO Threshold (mask) */
#define SSCR1_RFT 0x3c00 /* Receive FIFO Threshold (mask) */
#define SSCR1_TXTRESH(x) ((x - 1) << 6) /* level [1..16] */
#define SSCR1_RXTRESH(x) ((x - 1) << 10) /* level [1..16] */
#define SSCR1_TINTE (1 << 19) /* Receiver Time-out
Interrupt enable */
#define SSCR0_DSS 0x0f /* Data Size Select (mask) */
#define SSCR0_DATASIZE(x) (x - 1) /* Data Size Select [4..16] */
#define SSCR0_FRF 0x30 /* FRame Format (mask) */
#define SSCR0_MOTO (0x0 << 4) /* Motorola's Serial
Peripheral Interface */
#define SSCR0_TI (0x1 << 4) /* TI's Synchronous
Serial Protocol (SSP) */
#define SSCR0_NATIONAL (0x2 << 4) /* National Microwire */
#define SSCR0_ECS (1 << 6) /* External clock select */
#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port
Enable */
#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
#define SSSR_BSY (1 << 4) /* SSP Busy */
#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
#endif /* __ARMADA100_SPI_H_ */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2012
* eInfochips Ltd. <www.einfochips.com>
* Written-by: Ajay Bhargav <contact@8051projects.net>
*
* (C) Copyright 2009
* Marvell Semiconductor <www.marvell.com>
*/
#ifndef __UTMI_ARMADA100__
#define __UTMI_ARMADA100__
#define UTMI_PHY_BASE 0xD4206000
/* utmi_ctrl - bits */
#define INPKT_DELAY_SOF (1 << 28)
#define PLL_PWR_UP 2
#define PHY_PWR_UP 1
/* utmi_pll - bits */
#define PLL_FBDIV_MASK 0x00000FF0
#define PLL_FBDIV 4
#define PLL_REFDIV_MASK 0x0000000F
#define PLL_REFDIV 0
#define PLL_READY 0x800000
#define VCOCAL_START (1 << 21)
#define N_DIVIDER 0xEE
#define M_DIVIDER 0x0B
/* utmi_tx - bits */
#define CK60_PHSEL 17
#define PHSEL_VAL 0x4
#define RCAL_START (1 << 12)
/*
* USB PHY registers
* Refer Datasheet Appendix A.21
*/
struct armd1usb_phy_reg {
u32 utmi_rev; /* USB PHY Revision */
u32 utmi_ctrl; /* USB PHY Control register */
u32 utmi_pll; /* PLL register */
u32 utmi_tx; /* Tx register */
u32 utmi_rx; /* Rx register */
u32 utmi_ivref; /* IVREF register */
u32 utmi_tst_g0; /* Test group 0 register */
u32 utmi_tst_g1; /* Test group 1 register */
u32 utmi_tst_g2; /* Test group 2 register */
u32 utmi_tst_g3; /* Test group 3 register */
u32 utmi_tst_g4; /* Test group 4 register */
u32 utmi_tst_g5; /* Test group 5 register */
u32 utmi_reserve; /* Reserve Register */
u32 utmi_usb_int; /* USB interuppt register */
u32 utmi_dbg_ctl; /* Debug control register */
u32 utmi_otg_addon; /* OTG addon register */
};
int utmi_init(void);
#endif /* __UTMI_ARMADA100__ */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
*
* (c) 2009 Ilya Yanok, Emcraft Systems <yanok@emcraft.com>
*
* Modified for mx25 by John Rigby <jrigby@gmail.com>
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#ifdef CONFIG_MX25_HCLK_FREQ
#define MXC_HCLK CONFIG_MX25_HCLK_FREQ
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_MX25_CLK32
#define MXC_CLK32 CONFIG_MX25_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
/* PER clocks (do not change order) */
MXC_CSI_CLK,
MXC_EPIT_CLK,
MXC_ESAI_CLK,
MXC_ESDHC1_CLK,
MXC_ESDHC2_CLK,
MXC_GPT_CLK,
MXC_I2C_CLK,
MXC_LCDC_CLK,
MXC_NFC_CLK,
MXC_OWIRE_CLK,
MXC_PWM_CLK,
MXC_SIM1_CLK,
MXC_SIM2_CLK,
MXC_SSI1_CLK,
MXC_SSI2_CLK,
MXC_UART_CLK,
/* Other clocks */
MXC_ARM_CLK,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_CSPI_CLK,
MXC_FEC_CLK,
MXC_CLK_NUM
};
int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq);
unsigned int mxc_get_clock(enum mxc_clock clk);
#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
#endif /* __ASM_ARCH_CLOCK_H */

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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_MX25_GPIO_H
#define __ASM_ARCH_MX25_GPIO_H
#include <asm/mach-imx/gpio.h>
#endif

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arch/arm/include/asm/arch-mx25/imx-regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2009, DENX Software Engineering
* Author: John Rigby <jcrigby@gmail.com
*
* Based on arch-mx31/imx-regs.h
* Copyright (C) 2009 Ilya Yanok,
* Emcraft Systems <yanok@emcraft.com>
* and arch-mx27/imx-regs.h
* Copyright (C) 2007 Pengutronix,
* Sascha Hauer <s.hauer@pengutronix.de>
* Copyright (C) 2009 Ilya Yanok,
* Emcraft Systems <yanok@emcraft.com>
*/
#ifndef _IMX_REGS_H
#define _IMX_REGS_H
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/* Clock Control Module (CCM) registers */
struct ccm_regs {
u32 mpctl; /* Core PLL Control */
u32 upctl; /* USB PLL Control */
u32 cctl; /* Clock Control */
u32 cgr0; /* Clock Gating Control 0 */
u32 cgr1; /* Clock Gating Control 1 */
u32 cgr2; /* Clock Gating Control 2 */
u32 pcdr[4]; /* PER Clock Dividers */
u32 rcsr; /* CCM Status */
u32 crdr; /* CCM Reset and Debug */
u32 dcvr0; /* DPTC Comparator Value 0 */
u32 dcvr1; /* DPTC Comparator Value 1 */
u32 dcvr2; /* DPTC Comparator Value 2 */
u32 dcvr3; /* DPTC Comparator Value 3 */
u32 ltr0; /* Load Tracking 0 */
u32 ltr1; /* Load Tracking 1 */
u32 ltr2; /* Load Tracking 2 */
u32 ltr3; /* Load Tracking 3 */
u32 ltbr0; /* Load Tracking Buffer 0 */
u32 ltbr1; /* Load Tracking Buffer 1 */
u32 pcmr0; /* Power Management Control 0 */
u32 pcmr1; /* Power Management Control 1 */
u32 pcmr2; /* Power Management Control 2 */
u32 mcr; /* Miscellaneous Control */
u32 lpimr0; /* Low Power Interrupt Mask 0 */
u32 lpimr1; /* Low Power Interrupt Mask 1 */
};
/* Enhanced SDRAM Controller (ESDRAMC) registers */
struct esdramc_regs {
u32 ctl0; /* control 0 */
u32 cfg0; /* configuration 0 */
u32 ctl1; /* control 1 */
u32 cfg1; /* configuration 1 */
u32 misc; /* miscellaneous */
u32 pad[3];
u32 cdly1; /* Delay Line 1 configuration debug */
u32 cdly2; /* delay line 2 configuration debug */
u32 cdly3; /* delay line 3 configuration debug */
u32 cdly4; /* delay line 4 configuration debug */
u32 cdly5; /* delay line 5 configuration debug */
u32 cdlyl; /* delay line cycle length debug */
};
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
u32 ctrl; /* control */
u32 pre; /* prescaler */
u32 stat; /* status */
u32 intr; /* interrupt */
u32 cmp[3]; /* output compare 1-3 */
u32 capt[2]; /* input capture 1-2 */
u32 counter; /* counter */
};
/* Watchdog Timer (WDOG) registers */
struct wdog_regs {
u16 wcr; /* Control */
u16 wsr; /* Service */
u16 wrsr; /* Reset Status */
u16 wicr; /* Interrupt Control */
u16 wmcr; /* Misc Control */
};
/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
u32 iim_err;
u32 iim_emask;
u32 iim_fctl;
u32 iim_ua;
u32 iim_la;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
} bank[3];
};
struct fuse_bank0_regs {
u32 fuse0_7[8];
u32 uid[8];
u32 fuse16_25[0xa];
u32 mac_addr[6];
};
struct fuse_bank1_regs {
u32 fuse0_21[0x16];
u32 usr5;
u32 fuse23_29[7];
u32 usr6[2];
};
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
struct max_regs {
u32 mpr0;
u32 pad00[3];
u32 sgpcr0;
u32 pad01[59];
u32 mpr1;
u32 pad02[3];
u32 sgpcr1;
u32 pad03[59];
u32 mpr2;
u32 pad04[3];
u32 sgpcr2;
u32 pad05[59];
u32 mpr3;
u32 pad06[3];
u32 sgpcr3;
u32 pad07[59];
u32 mpr4;
u32 pad08[3];
u32 sgpcr4;
u32 pad09[251];
u32 mgpcr0;
u32 pad10[63];
u32 mgpcr1;
u32 pad11[63];
u32 mgpcr2;
u32 pad12[63];
u32 mgpcr3;
u32 pad13[63];
u32 mgpcr4;
};
/* AHB <-> IP-Bus Interface (AIPS) */
struct aips_regs {
u32 mpr_0_7;
u32 mpr_8_15;
};
/* LCD controller registers */
struct lcdc_regs {
u32 lssar; /* Screen Start Address */
u32 lsr; /* Size */
u32 lvpwr; /* Virtual Page Width */
u32 lcpr; /* Cursor Position */
u32 lcwhb; /* Cursor Width Height and Blink */
u32 lccmr; /* Color Cursor Mapping */
u32 lpcr; /* Panel Configuration */
u32 lhcr; /* Horizontal Configuration */
u32 lvcr; /* Vertical Configuration */
u32 lpor; /* Panning Offset */
u32 lscr; /* Sharp Configuration */
u32 lpccr; /* PWM Contrast Control */
u32 ldcr; /* DMA Control */
u32 lrmcr; /* Refresh Mode Control */
u32 licr; /* Interrupt Configuration */
u32 lier; /* Interrupt Enable */
u32 lisr; /* Interrupt Status */
u32 res0[3];
u32 lgwsar; /* Graphic Window Start Address */
u32 lgwsr; /* Graphic Window Size */
u32 lgwvpwr; /* Graphic Window Virtual Page Width Regist */
u32 lgwpor; /* Graphic Window Panning Offset */
u32 lgwpr; /* Graphic Window Position */
u32 lgwcr; /* Graphic Window Control */
u32 lgwdcr; /* Graphic Window DMA Control */
u32 res1[5];
u32 lauscr; /* AUS Mode Control */
u32 lausccr; /* AUS mode Cursor Control */
u32 res2[31 + 64*7];
u32 bglut; /* Background Lookup Table */
u32 gwlut; /* Graphic Window Lookup Table */
};
/* Wireless External Interface Module Registers */
struct weim_regs {
u32 cscr0u; /* Chip Select 0 Upper Register */
u32 cscr0l; /* Chip Select 0 Lower Register */
u32 cscr0a; /* Chip Select 0 Addition Register */
u32 pad0;
u32 cscr1u; /* Chip Select 1 Upper Register */
u32 cscr1l; /* Chip Select 1 Lower Register */
u32 cscr1a; /* Chip Select 1 Addition Register */
u32 pad1;
u32 cscr2u; /* Chip Select 2 Upper Register */
u32 cscr2l; /* Chip Select 2 Lower Register */
u32 cscr2a; /* Chip Select 2 Addition Register */
u32 pad2;
u32 cscr3u; /* Chip Select 3 Upper Register */
u32 cscr3l; /* Chip Select 3 Lower Register */
u32 cscr3a; /* Chip Select 3 Addition Register */
u32 pad3;
u32 cscr4u; /* Chip Select 4 Upper Register */
u32 cscr4l; /* Chip Select 4 Lower Register */
u32 cscr4a; /* Chip Select 4 Addition Register */
u32 pad4;
u32 cscr5u; /* Chip Select 5 Upper Register */
u32 cscr5l; /* Chip Select 5 Lower Register */
u32 cscr5a; /* Chip Select 5 Addition Register */
u32 pad5;
u32 wcr; /* WEIM Configuration Register */
};
/* Multi-Master Memory Interface */
struct m3if_regs {
u32 ctl; /* Control Register */
u32 wcfg0; /* Watermark Configuration Register 0 */
u32 wcfg1; /* Watermark Configuration Register1 */
u32 wcfg2; /* Watermark Configuration Register2 */
u32 wcfg3; /* Watermark Configuration Register 3 */
u32 wcfg4; /* Watermark Configuration Register 4 */
u32 wcfg5; /* Watermark Configuration Register 5 */
u32 wcfg6; /* Watermark Configuration Register 6 */
u32 wcfg7; /* Watermark Configuration Register 7 */
u32 wcsr; /* Watermark Control and Status Register */
u32 scfg0; /* Snooping Configuration Register 0 */
u32 scfg1; /* Snooping Configuration Register 1 */
u32 scfg2; /* Snooping Configuration Register 2 */
u32 ssr0; /* Snooping Status Register 0 */
u32 ssr1; /* Snooping Status Register 1 */
u32 res0;
u32 mlwe0; /* Master Lock WEIM CS0 Register */
u32 mlwe1; /* Master Lock WEIM CS1 Register */
u32 mlwe2; /* Master Lock WEIM CS2 Register */
u32 mlwe3; /* Master Lock WEIM CS3 Register */
u32 mlwe4; /* Master Lock WEIM CS4 Register */
u32 mlwe5; /* Master Lock WEIM CS5 Register */
};
/* Pulse width modulation */
struct pwm_regs {
u32 cr; /* Control Register */
u32 sr; /* Status Register */
u32 ir; /* Interrupt Register */
u32 sar; /* Sample Register */
u32 pr; /* Period Register */
u32 cnr; /* Counter Register */
};
/* Enhanced Periodic Interrupt Timer */
struct epit_regs {
u32 cr; /* Control register */
u32 sr; /* Status register */
u32 lr; /* Load register */
u32 cmpr; /* Compare register */
u32 cnr; /* Counter register */
};
#endif
#define ARCH_MXC
/* AIPS 1 */
#define IMX_AIPS1_BASE (0x43F00000)
#define IMX_MAX_BASE (0x43F04000)
#define IMX_CLKCTL_BASE (0x43F08000)
#define IMX_ETB_SLOT4_BASE (0x43F0C000)
#define IMX_ETB_SLOT5_BASE (0x43F10000)
#define IMX_ECT_CTIO_BASE (0x43F18000)
#define I2C1_BASE_ADDR (0x43F80000)
#define I2C3_BASE_ADDR (0x43F84000)
#define IMX_CAN1_BASE (0x43F88000)
#define IMX_CAN2_BASE (0x43F8C000)
#define UART1_BASE (0x43F90000)
#define UART2_BASE (0x43F94000)
#define I2C2_BASE_ADDR (0x43F98000)
#define IMX_OWIRE_BASE (0x43F9C000)
#define IMX_CSPI1_BASE (0x43FA4000)
#define IMX_KPP_BASE (0x43FA8000)
#define IMX_IOPADMUX_BASE (0x43FAC000)
#define IOMUXC_BASE_ADDR IMX_IOPADMUX_BASE
#define IMX_IOPADCTL_BASE (0x43FAC22C)
#define IMX_IOPADGRPCTL_BASE (0x43FAC418)
#define IMX_IOPADINPUTSEL_BASE (0x43FAC460)
#define IMX_AUDMUX_BASE (0x43FB0000)
#define IMX_ECT_IP1_BASE (0x43FB8000)
#define IMX_ECT_IP2_BASE (0x43FBC000)
/* SPBA */
#define IMX_SPBA_BASE (0x50000000)
#define IMX_CSPI3_BASE (0x50004000)
#define UART4_BASE (0x50008000)
#define UART3_BASE (0x5000C000)
#define IMX_CSPI2_BASE (0x50010000)
#define IMX_SSI2_BASE (0x50014000)
#define IMX_ESAI_BASE (0x50018000)
#define IMX_ATA_DMA_BASE (0x50020000)
#define IMX_SIM1_BASE (0x50024000)
#define IMX_SIM2_BASE (0x50028000)
#define UART5_BASE (0x5002C000)
#define IMX_TSC_BASE (0x50030000)
#define IMX_SSI1_BASE (0x50034000)
#define IMX_FEC_BASE (0x50038000)
#define IMX_SPBA_CTRL_BASE (0x5003C000)
/* AIPS 2 */
#define IMX_AIPS2_BASE (0x53F00000)
#define IMX_CCM_BASE (0x53F80000)
#define IMX_GPT4_BASE (0x53F84000)
#define IMX_GPT3_BASE (0x53F88000)
#define IMX_GPT2_BASE (0x53F8C000)
#define IMX_GPT1_BASE (0x53F90000)
#define IMX_EPIT1_BASE (0x53F94000)
#define IMX_EPIT2_BASE (0x53F98000)
#define IMX_GPIO4_BASE (0x53F9C000)
#define IMX_PWM2_BASE (0x53FA0000)
#define IMX_GPIO3_BASE (0x53FA4000)
#define IMX_PWM3_BASE (0x53FA8000)
#define IMX_SCC_BASE (0x53FAC000)
#define IMX_SCM_BASE (0x53FAE000)
#define IMX_SMN_BASE (0x53FAF000)
#define IMX_RNGD_BASE (0x53FB0000)
#define IMX_MMC_SDHC1_BASE (0x53FB4000)
#define IMX_MMC_SDHC2_BASE (0x53FB8000)
#define IMX_LCDC_BASE (0x53FBC000)
#define IMX_SLCDC_BASE (0x53FC0000)
#define IMX_PWM4_BASE (0x53FC8000)
#define IMX_GPIO1_BASE (0x53FCC000)
#define IMX_GPIO2_BASE (0x53FD0000)
#define IMX_SDMA_BASE (0x53FD4000)
#define IMX_WDT_BASE (0x53FDC000)
#define WDOG1_BASE_ADDR IMX_WDT_BASE
#define IMX_PWM1_BASE (0x53FE0000)
#define IMX_RTIC_BASE (0x53FEC000)
#define IMX_IIM_BASE (0x53FF0000)
#define IIM_BASE_ADDR IMX_IIM_BASE
#define IMX_USB_BASE (0x53FF4000)
/*
* This is in contradiction to the imx25 reference manual, which says that
* port 1's registers start at 0x53FF4200. The correct base address for
* port 1 is 0x53FF4400. The kernel uses 0x53FF4400 as well.
*/
#define IMX_USB_PORT_OFFSET 0x400
#define IMX_CSI_BASE (0x53FF8000)
#define IMX_DRYICE_BASE (0x53FFC000)
#define IMX_ARM926_ROMPATCH (0x60000000)
#define IMX_ARM926_ASIC (0x68000000)
/* 128K Internal Static RAM */
#define IMX_RAM_BASE (0x78000000)
#define IMX_RAM_SIZE (128 * 1024)
/* SDRAM BANKS */
#define IMX_SDRAM_BANK0_BASE (0x80000000)
#define IMX_SDRAM_BANK1_BASE (0x90000000)
#define IMX_WEIM_CS0 (0xA0000000)
#define IMX_WEIM_CS1 (0xA8000000)
#define IMX_WEIM_CS2 (0xB0000000)
#define IMX_WEIM_CS3 (0xB2000000)
#define IMX_WEIM_CS4 (0xB4000000)
#define IMX_ESDRAMC_BASE (0xB8001000)
#define IMX_WEIM_CTRL_BASE (0xB8002000)
#define IMX_M3IF_CTRL_BASE (0xB8003000)
#define IMX_EMI_CTRL_BASE (0xB8004000)
/* NAND Flash Controller */
#define IMX_NFC_BASE (0xBB000000)
#define NFC_BASE_ADDR IMX_NFC_BASE
/* CCM bitfields */
#define CCM_PLL_MFI_SHIFT 10
#define CCM_PLL_MFI_MASK 0xf
#define CCM_PLL_MFN_SHIFT 0
#define CCM_PLL_MFN_MASK 0x3ff
#define CCM_PLL_MFD_SHIFT 16
#define CCM_PLL_MFD_MASK 0x3ff
#define CCM_PLL_PD_SHIFT 26
#define CCM_PLL_PD_MASK 0xf
#define CCM_CCTL_ARM_DIV_SHIFT 30
#define CCM_CCTL_ARM_DIV_MASK 3
#define CCM_CCTL_AHB_DIV_SHIFT 28
#define CCM_CCTL_AHB_DIV_MASK 3
#define CCM_CCTL_ARM_SRC (1 << 14)
#define CCM_CGR1_GPT1 (1 << 19)
#define CCM_PERCLK_REG(clk) (clk / 4)
#define CCM_PERCLK_SHIFT(clk) (8 * (clk % 4))
#define CCM_PERCLK_MASK 0x3f
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
#define CCM_RCSR_NF_PS(v) ((v >> 26) & 3)
#define CCM_CRDR_BT_UART_SRC_SHIFT 29
#define CCM_CRDR_BT_UART_SRC_MASK 7
/* ESDRAM Controller register bitfields */
#define ESDCTL_PRCT(x) (((x) & 0x3f) << 0)
#define ESDCTL_BL (1 << 7)
#define ESDCTL_FP (1 << 8)
#define ESDCTL_PWDT(x) (((x) & 3) << 10)
#define ESDCTL_SREFR(x) (((x) & 7) << 13)
#define ESDCTL_DSIZ_16_UPPER (0 << 16)
#define ESDCTL_DSIZ_16_LOWER (1 << 16)
#define ESDCTL_DSIZ_32 (2 << 16)
#define ESDCTL_COL8 (0 << 20)
#define ESDCTL_COL9 (1 << 20)
#define ESDCTL_COL10 (2 << 20)
#define ESDCTL_ROW11 (0 << 24)
#define ESDCTL_ROW12 (1 << 24)
#define ESDCTL_ROW13 (2 << 24)
#define ESDCTL_ROW14 (3 << 24)
#define ESDCTL_ROW15 (4 << 24)
#define ESDCTL_SP (1 << 27)
#define ESDCTL_SMODE_NORMAL (0 << 28)
#define ESDCTL_SMODE_PRECHARGE (1 << 28)
#define ESDCTL_SMODE_AUTO_REF (2 << 28)
#define ESDCTL_SMODE_LOAD_MODE (3 << 28)
#define ESDCTL_SMODE_MAN_REF (4 << 28)
#define ESDCTL_SDE (1 << 31)
#define ESDCFG_TRC(x) (((x) & 0xf) << 0)
#define ESDCFG_TRCD(x) (((x) & 0x7) << 4)
#define ESDCFG_TCAS(x) (((x) & 0x3) << 8)
#define ESDCFG_TRRD(x) (((x) & 0x3) << 10)
#define ESDCFG_TRAS(x) (((x) & 0x7) << 12)
#define ESDCFG_TWR (1 << 15)
#define ESDCFG_TMRD(x) (((x) & 0x3) << 16)
#define ESDCFG_TRP(x) (((x) & 0x3) << 18)
#define ESDCFG_TWTR (1 << 20)
#define ESDCFG_TXP(x) (((x) & 0x3) << 21)
#define ESDMISC_RST (1 << 1)
#define ESDMISC_MDDREN (1 << 2)
#define ESDMISC_MDDR_DL_RST (1 << 3)
#define ESDMISC_MDDR_MDIS (1 << 4)
#define ESDMISC_LHD (1 << 5)
#define ESDMISC_MA10_SHARE (1 << 6)
#define ESDMISC_SDRAM_RDY (1 << 31)
/* GPT bits */
#define GPT_CTRL_SWR (1 << 15) /* Software reset */
#define GPT_CTRL_FRR (1 << 9) /* Freerun / restart */
#define GPT_CTRL_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPT_CTRL_TEN 1 /* Timer enable */
/* WDOG enable */
#define WCR_WDE 0x04
#define WSR_UNLOCK1 0x5555
#define WSR_UNLOCK2 0xAAAA
/* MAX bits */
#define MAX_MGPCR_AULB(x) (((x) & 0x7) << 0)
/* M3IF bits */
#define M3IF_CTL_MRRP(x) (((x) & 0xff) << 0)
/* WEIM bits */
/* 13 fields of the upper CS control register */
#define WEIM_CSCR_U(sp, wp, bcd, bcs, psz, pme, sync, dol, \
cnc, wsc, ew, wws, edc) \
((sp) << 31 | (wp) << 30 | (bcd) << 28 | (bcs) << 24 | \
(psz) << 22 | (pme) << 21 | (sync) << 20 | (dol) << 16 | \
(cnc) << 14 | (wsc) << 8 | (ew) << 7 | (wws) << 4 | (edc) << 0)
/* 12 fields of the lower CS control register */
#define WEIM_CSCR_L(oea, oen, ebwa, ebwn, \
csa, ebc, dsz, csn, psr, cre, wrap, csen) \
((oea) << 28 | (oen) << 24 | (ebwa) << 20 | (ebwn) << 16 |\
(csa) << 12 | (ebc) << 11 | (dsz) << 8 | (csn) << 4 |\
(psr) << 3 | (cre) << 2 | (wrap) << 1 | (csen) << 0)
/* 14 fields of the additional CS control register */
#define WEIM_CSCR_A(ebra, ebrn, rwa, rwn, mum, lah, lbn, lba, dww, dct, \
wwu, age, cnc2, fce) \
((ebra) << 28 | (ebrn) << 24 | (rwa) << 20 | (rwn) << 16 |\
(mum) << 15 | (lah) << 13 | (lbn) << 10 | (lba) << 8 |\
(dww) << 6 | (dct) << 4 | (wwu) << 3 |\
(age) << 2 | (cnc2) << 1 | (fce) << 0)
/* Names used in GPIO driver */
#define GPIO1_BASE_ADDR IMX_GPIO1_BASE
#define GPIO2_BASE_ADDR IMX_GPIO2_BASE
#define GPIO3_BASE_ADDR IMX_GPIO3_BASE
#define GPIO4_BASE_ADDR IMX_GPIO4_BASE
/*
* CSPI register definitions
*/
#define MXC_SPI_BASE_ADDRESSES \
IMX_CSPI1_BASE, \
IMX_CSPI2_BASE, \
IMX_CSPI3_BASE
#endif /* _IMX_REGS_H */

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arch/arm/include/asm/arch-mx25/iomux-mx25.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2013 ADVANSEE
* Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
*
* Based on mainline Linux i.MX iomux-mx25.h file:
* Copyright (C) 2009 by Lothar Wassmann <LW@KARO-electronics.de>
*
* Based on Linux arch/arm/mach-mx25/mx25_pins.h:
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
* and Linux arch/arm/plat-mxc/include/mach/iomux-mx35.h:
* Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH <armlinux@phytec.de>
*/
#ifndef __IOMUX_MX25_H__
#define __IOMUX_MX25_H__
#include <asm/mach-imx/iomux-v3.h>
/* Pad control groupings */
#define MX25_KPP_ROW_PAD_CTRL PAD_CTL_PUS_100K_UP
#define MX25_KPP_COL_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
/*
* The naming convention for the pad modes is MX25_PAD_<padname>__<padmode>
* If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
* See also iomux-v3.h
*/
/* PAD MUX ALT INPSE PATH PADCTRL */
enum {
MX25_PAD_A10__A10 = IOMUX_PAD(0x000, 0x008, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A10__GPIO_4_0 = IOMUX_PAD(0x000, 0x008, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A13__A13 = IOMUX_PAD(0x22C, 0x00c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A13__GPIO_4_1 = IOMUX_PAD(0x22C, 0x00c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A14__A14 = IOMUX_PAD(0x230, 0x010, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A14__GPIO_2_0 = IOMUX_PAD(0x230, 0x010, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A15__A15 = IOMUX_PAD(0x234, 0x014, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A15__GPIO_2_1 = IOMUX_PAD(0x234, 0x014, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A16__A16 = IOMUX_PAD(0x000, 0x018, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A16__GPIO_2_2 = IOMUX_PAD(0x000, 0x018, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A17__A17 = IOMUX_PAD(0x238, 0x01c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A17__GPIO_2_3 = IOMUX_PAD(0x238, 0x01c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A18__A18 = IOMUX_PAD(0x23c, 0x020, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A18__GPIO_2_4 = IOMUX_PAD(0x23c, 0x020, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A18__FEC_COL = IOMUX_PAD(0x23c, 0x020, 0x07, 0x504, 0, NO_PAD_CTRL),
MX25_PAD_A19__A19 = IOMUX_PAD(0x240, 0x024, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A19__FEC_RX_ER = IOMUX_PAD(0x240, 0x024, 0x07, 0x518, 0, NO_PAD_CTRL),
MX25_PAD_A19__GPIO_2_5 = IOMUX_PAD(0x240, 0x024, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A20__A20 = IOMUX_PAD(0x244, 0x028, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A20__GPIO_2_6 = IOMUX_PAD(0x244, 0x028, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A20__FEC_RDATA2 = IOMUX_PAD(0x244, 0x028, 0x07, 0x50c, 0, NO_PAD_CTRL),
MX25_PAD_A21__A21 = IOMUX_PAD(0x248, 0x02c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A21__GPIO_2_7 = IOMUX_PAD(0x248, 0x02c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A21__FEC_RDATA3 = IOMUX_PAD(0x248, 0x02c, 0x07, 0x510, 0, NO_PAD_CTRL),
MX25_PAD_A22__A22 = IOMUX_PAD(0x000, 0x030, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A22__GPIO_2_8 = IOMUX_PAD(0x000, 0x030, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A23__A23 = IOMUX_PAD(0x24c, 0x034, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A23__GPIO_2_9 = IOMUX_PAD(0x24c, 0x034, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A24__A24 = IOMUX_PAD(0x250, 0x038, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A24__GPIO_2_10 = IOMUX_PAD(0x250, 0x038, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A24__FEC_RX_CLK = IOMUX_PAD(0x250, 0x038, 0x07, 0x514, 0, NO_PAD_CTRL),
MX25_PAD_A25__A25 = IOMUX_PAD(0x254, 0x03c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_A25__GPIO_2_11 = IOMUX_PAD(0x254, 0x03c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_A25__FEC_CRS = IOMUX_PAD(0x254, 0x03c, 0x07, 0x508, 0, NO_PAD_CTRL),
MX25_PAD_EB0__EB0 = IOMUX_PAD(0x258, 0x040, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_EB0__AUD4_TXD = IOMUX_PAD(0x258, 0x040, 0x04, 0x464, 0, NO_PAD_CTRL),
MX25_PAD_EB0__GPIO_2_12 = IOMUX_PAD(0x258, 0x040, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_EB1__EB1 = IOMUX_PAD(0x25c, 0x044, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_EB1__AUD4_RXD = IOMUX_PAD(0x25c, 0x044, 0x04, 0x460, 0, NO_PAD_CTRL),
MX25_PAD_EB1__GPIO_2_13 = IOMUX_PAD(0x25c, 0x044, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_OE__OE = IOMUX_PAD(0x260, 0x048, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_OE__AUD4_TXC = IOMUX_PAD(0x260, 0x048, 0x04, 0, 0, NO_PAD_CTRL),
MX25_PAD_OE__GPIO_2_14 = IOMUX_PAD(0x260, 0x048, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS0__CS0 = IOMUX_PAD(0x000, 0x04c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS0__GPIO_4_2 = IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS1__CS1 = IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS1__NF_CE3 = IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS1__GPIO_4_3 = IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS4__CS4 = IOMUX_PAD(0x264, 0x054, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS4__NF_CE1 = IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS4__UART5_CTS = IOMUX_PAD(0x264, 0x054, 0x03, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS4__GPIO_3_20 = IOMUX_PAD(0x264, 0x054, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS5__CS5 = IOMUX_PAD(0x268, 0x058, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS5__NF_CE2 = IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_CS5__UART5_RTS = IOMUX_PAD(0x268, 0x058, 0x03, 0x574, 0, NO_PAD_CTRL),
MX25_PAD_CS5__GPIO_3_21 = IOMUX_PAD(0x268, 0x058, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NF_CE0__NF_CE0 = IOMUX_PAD(0x26c, 0x05c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NF_CE0__GPIO_3_22 = IOMUX_PAD(0x26c, 0x05c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_ECB__ECB = IOMUX_PAD(0x270, 0x060, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_ECB__UART5_TXD_MUX = IOMUX_PAD(0x270, 0x060, 0x03, 0, 0, NO_PAD_CTRL),
MX25_PAD_ECB__GPIO_3_23 = IOMUX_PAD(0x270, 0x060, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LBA__LBA = IOMUX_PAD(0x274, 0x064, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_LBA__UART5_RXD_MUX = IOMUX_PAD(0x274, 0x064, 0x03, 0x578, 0, NO_PAD_CTRL),
MX25_PAD_LBA__GPIO_3_24 = IOMUX_PAD(0x274, 0x064, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_BCLK__BCLK = IOMUX_PAD(0x000, 0x068, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_BCLK__GPIO_4_4 = IOMUX_PAD(0x000, 0x068, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_RW__RW = IOMUX_PAD(0x278, 0x06c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_RW__AUD4_TXFS = IOMUX_PAD(0x278, 0x06c, 0x04, 0x474, 0, NO_PAD_CTRL),
MX25_PAD_RW__GPIO_3_25 = IOMUX_PAD(0x278, 0x06c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFWE_B__NFWE_B = IOMUX_PAD(0x000, 0x070, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFWE_B__GPIO_3_26 = IOMUX_PAD(0x000, 0x070, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFRE_B__NFRE_B = IOMUX_PAD(0x000, 0x074, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFRE_B__GPIO_3_27 = IOMUX_PAD(0x000, 0x074, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFALE__NFALE = IOMUX_PAD(0x000, 0x078, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFALE__GPIO_3_28 = IOMUX_PAD(0x000, 0x078, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFCLE__NFCLE = IOMUX_PAD(0x000, 0x07c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFCLE__GPIO_3_29 = IOMUX_PAD(0x000, 0x07c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFWP_B__NFWP_B = IOMUX_PAD(0x000, 0x080, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFWP_B__GPIO_3_30 = IOMUX_PAD(0x000, 0x080, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
MX25_PAD_NFRB__GPIO_3_31 = IOMUX_PAD(0x27c, 0x084, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D15__D15 = IOMUX_PAD(0x280, 0x088, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D15__LD16 = IOMUX_PAD(0x280, 0x088, 0x01, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_D15__GPIO_4_5 = IOMUX_PAD(0x280, 0x088, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D14__D14 = IOMUX_PAD(0x284, 0x08c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D14__LD17 = IOMUX_PAD(0x284, 0x08c, 0x01, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_D14__GPIO_4_6 = IOMUX_PAD(0x284, 0x08c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D13__D13 = IOMUX_PAD(0x288, 0x090, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D13__LD18 = IOMUX_PAD(0x288, 0x090, 0x01, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_D13__GPIO_4_7 = IOMUX_PAD(0x288, 0x090, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D12__D12 = IOMUX_PAD(0x28c, 0x094, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D12__GPIO_4_8 = IOMUX_PAD(0x28c, 0x094, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D11__D11 = IOMUX_PAD(0x290, 0x098, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D11__GPIO_4_9 = IOMUX_PAD(0x290, 0x098, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D10__D10 = IOMUX_PAD(0x294, 0x09c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D10__GPIO_4_10 = IOMUX_PAD(0x294, 0x09c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D10__USBOTG_OC = IOMUX_PAD(0x294, 0x09c, 0x06, 0x57c, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_D9__D9 = IOMUX_PAD(0x298, 0x0a0, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D9__GPIO_4_11 = IOMUX_PAD(0x298, 0x0a0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
MX25_PAD_D8__D8 = IOMUX_PAD(0x29c, 0x0a4, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D8__GPIO_4_12 = IOMUX_PAD(0x29c, 0x0a4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D8__USBH2_OC = IOMUX_PAD(0x29c, 0x0a4, 0x06, 0x580, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_D7__D7 = IOMUX_PAD(0x2a0, 0x0a8, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D7__GPIO_4_13 = IOMUX_PAD(0x2a0, 0x0a8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D6__D6 = IOMUX_PAD(0x2a4, 0x0ac, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D6__GPIO_4_14 = IOMUX_PAD(0x2a4, 0x0ac, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D5__D5 = IOMUX_PAD(0x2a8, 0x0b0, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D5__GPIO_4_15 = IOMUX_PAD(0x2a8, 0x0b0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D4__D4 = IOMUX_PAD(0x2ac, 0x0b4, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D4__GPIO_4_16 = IOMUX_PAD(0x2ac, 0x0b4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D3__D3 = IOMUX_PAD(0x2b0, 0x0b8, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D3__GPIO_4_17 = IOMUX_PAD(0x2b0, 0x0b8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D2__D2 = IOMUX_PAD(0x2b4, 0x0bc, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D2__GPIO_4_18 = IOMUX_PAD(0x2b4, 0x0bc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D1__D1 = IOMUX_PAD(0x2b8, 0x0c0, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D1__GPIO_4_19 = IOMUX_PAD(0x2b8, 0x0c0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_D0__D0 = IOMUX_PAD(0x2bc, 0x0c4, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_D0__GPIO_4_20 = IOMUX_PAD(0x2bc, 0x0c4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD0__LD0 = IOMUX_PAD(0x2c0, 0x0c8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD0__CSI_D0 = IOMUX_PAD(0x2c0, 0x0c8, 0x02, 0x488, 0, NO_PAD_CTRL),
MX25_PAD_LD0__GPIO_2_15 = IOMUX_PAD(0x2c0, 0x0c8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD1__LD1 = IOMUX_PAD(0x2c4, 0x0cc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD1__CSI_D1 = IOMUX_PAD(0x2c4, 0x0cc, 0x02, 0x48c, 0, NO_PAD_CTRL),
MX25_PAD_LD1__GPIO_2_16 = IOMUX_PAD(0x2c4, 0x0cc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD2__LD2 = IOMUX_PAD(0x2c8, 0x0d0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD2__GPIO_2_17 = IOMUX_PAD(0x2c8, 0x0d0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD3__LD3 = IOMUX_PAD(0x2cc, 0x0d4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD3__GPIO_2_18 = IOMUX_PAD(0x2cc, 0x0d4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD4__LD4 = IOMUX_PAD(0x2d0, 0x0d8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD4__GPIO_2_19 = IOMUX_PAD(0x2d0, 0x0d8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD5__LD5 = IOMUX_PAD(0x2d4, 0x0dc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD5__GPIO_1_19 = IOMUX_PAD(0x2d4, 0x0dc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD6__LD6 = IOMUX_PAD(0x2d8, 0x0e0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD6__GPIO_1_20 = IOMUX_PAD(0x2d8, 0x0e0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD7__LD7 = IOMUX_PAD(0x2dc, 0x0e4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD7__GPIO_1_21 = IOMUX_PAD(0x2dc, 0x0e4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD8__LD8 = IOMUX_PAD(0x2e0, 0x0e8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD8__FEC_TX_ERR = IOMUX_PAD(0x2e0, 0x0e8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD9__LD9 = IOMUX_PAD(0x2e4, 0x0ec, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD9__FEC_COL = IOMUX_PAD(0x2e4, 0x0ec, 0x05, 0x504, 1, NO_PAD_CTRL),
MX25_PAD_LD10__LD10 = IOMUX_PAD(0x2e8, 0x0f0, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD10__FEC_RX_ER = IOMUX_PAD(0x2e8, 0x0f0, 0x05, 0x518, 1, NO_PAD_CTRL),
MX25_PAD_LD11__LD11 = IOMUX_PAD(0x2ec, 0x0f4, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD11__FEC_RDATA2 = IOMUX_PAD(0x2ec, 0x0f4, 0x05, 0x50c, 1, NO_PAD_CTRL),
MX25_PAD_LD12__LD12 = IOMUX_PAD(0x2f0, 0x0f8, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD12__FEC_RDATA3 = IOMUX_PAD(0x2f0, 0x0f8, 0x05, 0x510, 1, NO_PAD_CTRL),
MX25_PAD_LD13__LD13 = IOMUX_PAD(0x2f4, 0x0fc, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD13__FEC_TDATA2 = IOMUX_PAD(0x2f4, 0x0fc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD14__LD14 = IOMUX_PAD(0x2f8, 0x100, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD14__FEC_TDATA3 = IOMUX_PAD(0x2f8, 0x100, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LD15__LD15 = IOMUX_PAD(0x2fc, 0x104, 0x00, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_LD15__FEC_RX_CLK = IOMUX_PAD(0x2fc, 0x104, 0x05, 0x514, 1, NO_PAD_CTRL),
MX25_PAD_HSYNC__HSYNC = IOMUX_PAD(0x300, 0x108, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_HSYNC__GPIO_1_22 = IOMUX_PAD(0x300, 0x108, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSYNC__VSYNC = IOMUX_PAD(0x304, 0x10c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSYNC__GPIO_1_23 = IOMUX_PAD(0x304, 0x10c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_LSCLK__LSCLK = IOMUX_PAD(0x308, 0x110, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_LSCLK__GPIO_1_24 = IOMUX_PAD(0x308, 0x110, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_OE_ACD__OE_ACD = IOMUX_PAD(0x30c, 0x114, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_OE_ACD__GPIO_1_25 = IOMUX_PAD(0x30c, 0x114, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CONTRAST__CONTRAST = IOMUX_PAD(0x310, 0x118, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CONTRAST__PWM4_PWMO = IOMUX_PAD(0x310, 0x118, 0x04, 0, 0, NO_PAD_CTRL),
MX25_PAD_CONTRAST__FEC_CRS = IOMUX_PAD(0x310, 0x118, 0x05, 0x508, 1, NO_PAD_CTRL),
MX25_PAD_PWM__PWM = IOMUX_PAD(0x314, 0x11c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_PWM__GPIO_1_26 = IOMUX_PAD(0x314, 0x11c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_PWM__USBH2_OC = IOMUX_PAD(0x314, 0x11c, 0x06, 0x580, 1, PAD_CTL_PUS_100K_UP),
MX25_PAD_CSI_D2__CSI_D2 = IOMUX_PAD(0x318, 0x120, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D2__UART5_RXD_MUX = IOMUX_PAD(0x318, 0x120, 0x01, 0x578, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D2__GPIO_1_27 = IOMUX_PAD(0x318, 0x120, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D2__CSPI3_MOSI = IOMUX_PAD(0x318, 0x120, 0x07, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D3__CSI_D3 = IOMUX_PAD(0x31c, 0x124, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D3__GPIO_1_28 = IOMUX_PAD(0x31c, 0x124, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D3__CSPI3_MISO = IOMUX_PAD(0x31c, 0x124, 0x07, 0x4b4, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D4__CSI_D4 = IOMUX_PAD(0x320, 0x128, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D4__UART5_RTS = IOMUX_PAD(0x320, 0x128, 0x01, 0x574, 1, NO_PAD_CTRL),
MX25_PAD_CSI_D4__GPIO_1_29 = IOMUX_PAD(0x320, 0x128, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D4__CSPI3_SCLK = IOMUX_PAD(0x320, 0x128, 0x07, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D5__CSI_D5 = IOMUX_PAD(0x324, 0x12c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D5__GPIO_1_30 = IOMUX_PAD(0x324, 0x12c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D5__CSPI3_RDY = IOMUX_PAD(0x324, 0x12c, 0x07, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D6__CSI_D6 = IOMUX_PAD(0x328, 0x130, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D6__GPIO_1_31 = IOMUX_PAD(0x328, 0x130, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D7__CSI_D7 = IOMUX_PAD(0x32c, 0x134, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D7__GPIO_1_6 = IOMUX_PAD(0x32c, 0x134, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D8__CSI_D8 = IOMUX_PAD(0x330, 0x138, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D8__GPIO_1_7 = IOMUX_PAD(0x330, 0x138, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D9__CSI_D9 = IOMUX_PAD(0x334, 0x13c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_D9__GPIO_4_21 = IOMUX_PAD(0x334, 0x13c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_MCLK__CSI_MCLK = IOMUX_PAD(0x338, 0x140, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_MCLK__GPIO_1_8 = IOMUX_PAD(0x338, 0x140, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_VSYNC__CSI_VSYNC = IOMUX_PAD(0x33c, 0x144, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_VSYNC__GPIO_1_9 = IOMUX_PAD(0x33c, 0x144, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_HSYNC__CSI_HSYNC = IOMUX_PAD(0x340, 0x148, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_HSYNC__GPIO_1_10 = IOMUX_PAD(0x340, 0x148, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_PIXCLK__CSI_PIXCLK = IOMUX_PAD(0x344, 0x14c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSI_PIXCLK__GPIO_1_11 = IOMUX_PAD(0x344, 0x14c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x348, 0x150, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_I2C1_CLK__GPIO_1_12 = IOMUX_PAD(0x348, 0x150, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x34c, 0x154, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_I2C1_DAT__GPIO_1_13 = IOMUX_PAD(0x34c, 0x154, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MOSI__CSPI1_MOSI = IOMUX_PAD(0x350, 0x158, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MOSI__GPIO_1_14 = IOMUX_PAD(0x350, 0x158, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MISO__CSPI1_MISO = IOMUX_PAD(0x354, 0x15c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_MISO__GPIO_1_15 = IOMUX_PAD(0x354, 0x15c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS0__CSPI1_SS0 = IOMUX_PAD(0x358, 0x160, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS0__GPIO_1_16 = IOMUX_PAD(0x358, 0x160, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS1__CSPI1_SS1 = IOMUX_PAD(0x35c, 0x164, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS1__I2C3_DAT = IOMUX_PAD(0x35c, 0x164, 0x01, 0x528, 1, NO_PAD_CTRL),
MX25_PAD_CSPI1_SS1__GPIO_1_17 = IOMUX_PAD(0x35c, 0x164, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SCLK__CSPI1_SCLK = IOMUX_PAD(0x360, 0x168, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_SCLK__GPIO_1_18 = IOMUX_PAD(0x360, 0x168, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
MX25_PAD_CSPI1_RDY__GPIO_2_22 = IOMUX_PAD(0x364, 0x16c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_RXD__UART1_RXD = IOMUX_PAD(0x368, 0x170, 0x00, 0, 0, PAD_CTL_PUS_100K_DOWN),
MX25_PAD_UART1_RXD__GPIO_4_22 = IOMUX_PAD(0x368, 0x170, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x36c, 0x174, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_TXD__GPIO_4_23 = IOMUX_PAD(0x36c, 0x174, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x370, 0x178, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_UART1_RTS__CSI_D0 = IOMUX_PAD(0x370, 0x178, 0x01, 0x488, 1, NO_PAD_CTRL),
MX25_PAD_UART1_RTS__GPIO_4_24 = IOMUX_PAD(0x370, 0x178, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x374, 0x17c, 0x00, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_UART1_CTS__CSI_D1 = IOMUX_PAD(0x374, 0x17c, 0x01, 0x48c, 1, NO_PAD_CTRL),
MX25_PAD_UART1_CTS__GPIO_4_25 = IOMUX_PAD(0x374, 0x17c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_RXD__UART2_RXD = IOMUX_PAD(0x378, 0x180, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_RXD__GPIO_4_26 = IOMUX_PAD(0x378, 0x180, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_TXD__UART2_TXD = IOMUX_PAD(0x37c, 0x184, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_TXD__GPIO_4_27 = IOMUX_PAD(0x37c, 0x184, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_RTS__UART2_RTS = IOMUX_PAD(0x380, 0x188, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_RTS__FEC_COL = IOMUX_PAD(0x380, 0x188, 0x02, 0x504, 2, NO_PAD_CTRL),
MX25_PAD_UART2_RTS__GPIO_4_28 = IOMUX_PAD(0x380, 0x188, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_CTS__FEC_RX_ER = IOMUX_PAD(0x384, 0x18c, 0x02, 0x518, 2, NO_PAD_CTRL),
MX25_PAD_UART2_CTS__UART2_CTS = IOMUX_PAD(0x384, 0x18c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UART2_CTS__GPIO_4_29 = IOMUX_PAD(0x384, 0x18c, 0x05, 0, 0, NO_PAD_CTRL),
/*
* Removing the SION bit from MX25_PAD_SD1_CMD__SD1_CMD breaks detecting an SD
* card. According to the i.MX25 reference manual (e.g. Figure 23-2 in IMX25RM
* Rev. 2 from 01/2011) this pin is bidirectional. So it seems to be a silicon
* bug that configuring the SD1_CMD function doesn't enable the input path for
* this pin.
* This might have side effects for other hardware units that are connected to
* that pin and use the respective function as input.
*/
MX25_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x388, 0x190, 0x10, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_CMD__FEC_RDATA2 = IOMUX_PAD(0x388, 0x190, 0x02, 0x50c, 2, NO_PAD_CTRL),
MX25_PAD_SD1_CMD__GPIO_2_23 = IOMUX_PAD(0x388, 0x190, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x38c, 0x194, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_CLK__FEC_RDATA3 = IOMUX_PAD(0x38c, 0x194, 0x02, 0x510, 2, NO_PAD_CTRL),
MX25_PAD_SD1_CLK__GPIO_2_24 = IOMUX_PAD(0x38c, 0x194, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x390, 0x198, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_DATA0__GPIO_2_25 = IOMUX_PAD(0x390, 0x198, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_SD1_DATA1__SD1_DATA1 = IOMUX_PAD(0x394, 0x19c, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_DATA1__AUD7_RXD = IOMUX_PAD(0x394, 0x19c, 0x03, 0x478, 0, NO_PAD_CTRL),
MX25_PAD_SD1_DATA1__GPIO_2_26 = IOMUX_PAD(0x394, 0x19c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_SD1_DATA2__SD1_DATA2 = IOMUX_PAD(0x398, 0x1a0, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_DATA2__FEC_RX_CLK = IOMUX_PAD(0x398, 0x1a0, 0x05, 0x514, 2, NO_PAD_CTRL),
MX25_PAD_SD1_DATA2__GPIO_2_27 = IOMUX_PAD(0x398, 0x1a0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_SD1_DATA3__SD1_DATA3 = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0, 0, PAD_CTL_PUS_47K_UP),
MX25_PAD_SD1_DATA3__FEC_CRS = IOMUX_PAD(0x39c, 0x1a4, 0x00, 0x508, 2, NO_PAD_CTRL),
MX25_PAD_SD1_DATA3__GPIO_2_28 = IOMUX_PAD(0x39c, 0x1a4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW0__KPP_ROW0 = IOMUX_PAD(0x3a0, 0x1a8, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
MX25_PAD_KPP_ROW0__GPIO_2_29 = IOMUX_PAD(0x3a0, 0x1a8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW1__KPP_ROW1 = IOMUX_PAD(0x3a4, 0x1ac, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
MX25_PAD_KPP_ROW1__GPIO_2_30 = IOMUX_PAD(0x3a4, 0x1ac, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW2__KPP_ROW2 = IOMUX_PAD(0x3a8, 0x1b0, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
MX25_PAD_KPP_ROW2__CSI_D0 = IOMUX_PAD(0x3a8, 0x1b0, 0x03, 0x488, 2, NO_PAD_CTRL),
MX25_PAD_KPP_ROW2__GPIO_2_31 = IOMUX_PAD(0x3a8, 0x1b0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_ROW3__KPP_ROW3 = IOMUX_PAD(0x3ac, 0x1b4, 0x00, 0, 0, MX25_KPP_ROW_PAD_CTRL),
MX25_PAD_KPP_ROW3__CSI_LD1 = IOMUX_PAD(0x3ac, 0x1b4, 0x03, 0x48c, 2, NO_PAD_CTRL),
MX25_PAD_KPP_ROW3__GPIO_3_0 = IOMUX_PAD(0x3ac, 0x1b4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL0__KPP_COL0 = IOMUX_PAD(0x3b0, 0x1b8, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
MX25_PAD_KPP_COL0__UART4_RXD_MUX = IOMUX_PAD(0x3b0, 0x1b8, 0x01, 0x570, 1, NO_PAD_CTRL),
MX25_PAD_KPP_COL0__AUD5_TXD = IOMUX_PAD(0x3b0, 0x1b8, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_KPP_COL0__GPIO_3_1 = IOMUX_PAD(0x3b0, 0x1b8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL1__KPP_COL1 = IOMUX_PAD(0x3b4, 0x1bc, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
MX25_PAD_KPP_COL1__UART4_TXD_MUX = IOMUX_PAD(0x3b4, 0x1bc, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL1__AUD5_RXD = IOMUX_PAD(0x3b4, 0x1bc, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_KPP_COL1__GPIO_3_2 = IOMUX_PAD(0x3b4, 0x1bc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL2__KPP_COL2 = IOMUX_PAD(0x3b8, 0x1c0, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
MX25_PAD_KPP_COL2__UART4_RTS = IOMUX_PAD(0x3b8, 0x1c0, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL2__AUD5_TXC = IOMUX_PAD(0x3b8, 0x1c0, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_KPP_COL2__GPIO_3_3 = IOMUX_PAD(0x3b8, 0x1c0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL3__KPP_COL3 = IOMUX_PAD(0x3bc, 0x1c4, 0x00, 0, 0, MX25_KPP_COL_PAD_CTRL),
MX25_PAD_KPP_COL3__UART4_CTS = IOMUX_PAD(0x3bc, 0x1c4, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_KPP_COL3__AUD5_TXFS = IOMUX_PAD(0x3bc, 0x1c4, 0x02, 0, 0, PAD_CTL_PUS_100K_UP),
MX25_PAD_KPP_COL3__GPIO_3_4 = IOMUX_PAD(0x3bc, 0x1c4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_MDC__FEC_MDC = IOMUX_PAD(0x3c0, 0x1c8, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_MDC__AUD4_TXD = IOMUX_PAD(0x3c0, 0x1c8, 0x02, 0x464, 1, NO_PAD_CTRL),
MX25_PAD_FEC_MDC__GPIO_3_5 = IOMUX_PAD(0x3c0, 0x1c8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_MDIO__FEC_MDIO = IOMUX_PAD(0x3c4, 0x1cc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_22K_UP),
MX25_PAD_FEC_MDIO__AUD4_RXD = IOMUX_PAD(0x3c4, 0x1cc, 0x02, 0x460, 1, NO_PAD_CTRL),
MX25_PAD_FEC_MDIO__GPIO_3_6 = IOMUX_PAD(0x3c4, 0x1cc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TDATA0__FEC_TDATA0 = IOMUX_PAD(0x3c8, 0x1d0, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TDATA0__GPIO_3_7 = IOMUX_PAD(0x3c8, 0x1d0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TDATA1__FEC_TDATA1 = IOMUX_PAD(0x3cc, 0x1d4, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TDATA1__AUD4_TXFS = IOMUX_PAD(0x3cc, 0x1d4, 0x02, 0x474, 1, NO_PAD_CTRL),
MX25_PAD_FEC_TDATA1__GPIO_3_8 = IOMUX_PAD(0x3cc, 0x1d4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TX_EN__FEC_TX_EN = IOMUX_PAD(0x3d0, 0x1d8, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TX_EN__GPIO_3_9 = IOMUX_PAD(0x3d0, 0x1d8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_RDATA0__FEC_RDATA0 = IOMUX_PAD(0x3d4, 0x1dc, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
MX25_PAD_FEC_RDATA0__GPIO_3_10 = IOMUX_PAD(0x3d4, 0x1dc, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_RDATA1__FEC_RDATA1 = IOMUX_PAD(0x3d8, 0x1e0, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
MX25_PAD_FEC_RDATA1__GPIO_3_11 = IOMUX_PAD(0x3d8, 0x1e0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_RX_DV__FEC_RX_DV = IOMUX_PAD(0x3dc, 0x1e4, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
MX25_PAD_FEC_RX_DV__CAN2_RX = IOMUX_PAD(0x3dc, 0x1e4, 0x04, 0x484, 0, PAD_CTL_PUS_22K_UP),
MX25_PAD_FEC_RX_DV__GPIO_3_12 = IOMUX_PAD(0x3dc, 0x1e4, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK = IOMUX_PAD(0x3e0, 0x1e8, 0x00, 0, 0, PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN),
MX25_PAD_FEC_TX_CLK__GPIO_3_13 = IOMUX_PAD(0x3e0, 0x1e8, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_RTCK__RTCK = IOMUX_PAD(0x3e4, 0x1ec, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_RTCK__OWIRE = IOMUX_PAD(0x3e4, 0x1ec, 0x01, 0, 0, NO_PAD_CTRL),
MX25_PAD_RTCK__GPIO_3_14 = IOMUX_PAD(0x3e4, 0x1ec, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_DE_B__DE_B = IOMUX_PAD(0x3ec, 0x1f0, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_DE_B__GPIO_2_20 = IOMUX_PAD(0x3ec, 0x1f0, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_TDO__TDO = IOMUX_PAD(0x3e8, 0x000, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_A__GPIO_A = IOMUX_PAD(0x3f0, 0x1f4, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_A__CAN1_TX = IOMUX_PAD(0x3f0, 0x1f4, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
MX25_PAD_GPIO_B__GPIO_B = IOMUX_PAD(0x3f4, 0x1f8, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_B__CAN1_RX = IOMUX_PAD(0x3f4, 0x1f8, 0x06, 0x480, 1, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_B__USBOTG_OC = IOMUX_PAD(0x3f4, 0x1f8, 0x02, 0x57c, 1, PAD_CTL_PUS_100K_UP),
MX25_PAD_GPIO_C__GPIO_C = IOMUX_PAD(0x3f8, 0x1fc, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_C__CAN2_TX = IOMUX_PAD(0x3f8, 0x1fc, 0x06, 0, 0, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_D__GPIO_D = IOMUX_PAD(0x3fc, 0x200, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_E__LD16 = IOMUX_PAD(0x400, 0x204, 0x02, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_GPIO_D__CAN2_RX = IOMUX_PAD(0x3fc, 0x200, 0x06, 0x484, 1, PAD_CTL_PUS_22K_UP),
MX25_PAD_GPIO_E__GPIO_E = IOMUX_PAD(0x400, 0x204, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_F__LD17 = IOMUX_PAD(0x404, 0x208, 0x02, 0, 0, PAD_CTL_SRE_FAST),
MX25_PAD_GPIO_E__I2C3_CLK = IOMUX_PAD(0x400, 0x204, 0x01, 0x524, 2, NO_PAD_CTRL),
MX25_PAD_GPIO_E__AUD7_TXD = IOMUX_PAD(0x400, 0x204, 0x04, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_F__GPIO_F = IOMUX_PAD(0x404, 0x208, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_GPIO_F__AUD7_TXC = IOMUX_PAD(0x404, 0x208, 0x04, 0, 0, NO_PAD_CTRL),
MX25_PAD_EXT_ARMCLK__EXT_ARMCLK = IOMUX_PAD(0x000, 0x20c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_EXT_ARMCLK__GPIO_3_15 = IOMUX_PAD(0x000, 0x20c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_UPLL_BYPCLK__UPLL_BYPCLK = IOMUX_PAD(0x000, 0x210, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_UPLL_BYPCLK__GPIO_3_16 = IOMUX_PAD(0x000, 0x210, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSTBY_REQ__VSTBY_REQ = IOMUX_PAD(0x408, 0x214, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSTBY_REQ__AUD7_TXFS = IOMUX_PAD(0x408, 0x214, 0x04, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSTBY_REQ__GPIO_3_17 = IOMUX_PAD(0x408, 0x214, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSTBY_ACK__VSTBY_ACK = IOMUX_PAD(0x40c, 0x218, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_VSTBY_ACK__GPIO_3_18 = IOMUX_PAD(0x40c, 0x218, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_POWER_FAIL__POWER_FAIL = IOMUX_PAD(0x410, 0x21c, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_POWER_FAIL__AUD7_RXD = IOMUX_PAD(0x410, 0x21c, 0x04, 0x478, 1, NO_PAD_CTRL),
MX25_PAD_POWER_FAIL__GPIO_3_19 = IOMUX_PAD(0x410, 0x21c, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CLKO__CLKO = IOMUX_PAD(0x414, 0x220, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_CLKO__GPIO_2_21 = IOMUX_PAD(0x414, 0x220, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_BOOT_MODE0__BOOT_MODE0 = IOMUX_PAD(0x000, 0x224, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_BOOT_MODE0__GPIO_4_30 = IOMUX_PAD(0x000, 0x224, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_BOOT_MODE1__BOOT_MODE1 = IOMUX_PAD(0x000, 0x228, 0x00, 0, 0, NO_PAD_CTRL),
MX25_PAD_BOOT_MODE1__GPIO_4_31 = IOMUX_PAD(0x000, 0x228, 0x05, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_MISC = IOMUX_PAD(0x418, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_FEC = IOMUX_PAD(0x41c, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_JTAG = IOMUX_PAD(0x420, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_NFC = IOMUX_PAD(0x424, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_CSI = IOMUX_PAD(0x428, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_WEIM = IOMUX_PAD(0x42c, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_DDR = IOMUX_PAD(0x430, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_CRM = IOMUX_PAD(0x434, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_KPP = IOMUX_PAD(0x438, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_SDHC1 = IOMUX_PAD(0x43c, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_LCD = IOMUX_PAD(0x440, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_UART = IOMUX_PAD(0x444, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_NFC = IOMUX_PAD(0x448, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_CSI = IOMUX_PAD(0x44c, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DSE_CSPI1 = IOMUX_PAD(0x450, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DDRTYPE = IOMUX_PAD(0x454, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_SDHC1 = IOMUX_PAD(0x458, 0x000, 0, 0, 0, NO_PAD_CTRL),
MX25_PAD_CTL_GRP_DVS_LCD = IOMUX_PAD(0x45c, 0x000, 0, 0, 0, NO_PAD_CTRL),
};
#endif /* __IOMUX_MX25_H__ */

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arch/arm/include/asm/arch-mx25/macro.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Matthias Weisser <weisserm@arcor.de>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Common asm macros for imx25
*/
#ifndef __ASM_ARM_ARCH_MACRO_H__
#define __ASM_ARM_ARCH_MACRO_H__
#ifdef __ASSEMBLY__
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <asm/macro.h>
/*
* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.
*
* Default argument values:
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
* user-mode.
*/
.macro init_aips mpr=0x77777777
ldr r0, =IMX_AIPS1_BASE
ldr r1, =\mpr
str r1, [r0, #AIPS_MPR_0_7]
str r1, [r0, #AIPS_MPR_8_15]
ldr r2, =IMX_AIPS2_BASE
str r1, [r2, #AIPS_MPR_0_7]
str r1, [r2, #AIPS_MPR_8_15]
.endm
/*
* MAX (Multi-Layer AHB Crossbar Switch) setup
*
* Default argument values:
* - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
* - SGPCR: always park on last master
* - MGPCR: restore default values
*/
.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
ldr r0, =IMX_MAX_BASE
ldr r1, =\mpr
str r1, [r0, #MAX_MPR0] /* for S0 */
str r1, [r0, #MAX_MPR1] /* for S1 */
str r1, [r0, #MAX_MPR2] /* for S2 */
str r1, [r0, #MAX_MPR3] /* for S3 */
str r1, [r0, #MAX_MPR4] /* for S4 */
ldr r1, =\sgpcr
str r1, [r0, #MAX_SGPCR0] /* for S0 */
str r1, [r0, #MAX_SGPCR1] /* for S1 */
str r1, [r0, #MAX_SGPCR2] /* for S2 */
str r1, [r0, #MAX_SGPCR3] /* for S3 */
str r1, [r0, #MAX_SGPCR4] /* for S4 */
ldr r1, =\mgpcr
str r1, [r0, #MAX_MGPCR0] /* for M0 */
str r1, [r0, #MAX_MGPCR1] /* for M1 */
str r1, [r0, #MAX_MGPCR2] /* for M2 */
str r1, [r0, #MAX_MGPCR3] /* for M3 */
str r1, [r0, #MAX_MGPCR4] /* for M4 */
.endm
/*
* M3IF setup
*
* Default argument values:
* - CTL:
* MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
* MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
* MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
* MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
* MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
* MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
* MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
* ------------
* 0x00000001
*/
.macro init_m3if ctl=0x00000001
/* M3IF Control Register (M3IFCTL) */
write32 IMX_M3IF_CTRL_BASE, \ctl
.endm
#endif /* __ASSEMBLY__ */
#endif /* __ASM_ARM_ARCH_MACRO_H__ */

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arch/arm/include/asm/arch-mx35/clock.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
#ifdef CONFIG_MX35_HCLK_FREQ
#define MXC_HCLK CONFIG_MX35_HCLK_FREQ
#else
#define MXC_HCLK 24000000
#endif
#ifdef CONFIG_MX35_CLK32
#define MXC_CLK32 CONFIG_MX35_CLK32
#else
#define MXC_CLK32 32768
#endif
enum mxc_clock {
MXC_ARM_CLK,
MXC_AHB_CLK,
MXC_IPG_CLK,
MXC_IPG_PERCLK,
MXC_UART_CLK,
MXC_ESDHC1_CLK,
MXC_ESDHC2_CLK,
MXC_ESDHC3_CLK,
MXC_USB_CLK,
MXC_CSPI_CLK,
MXC_FEC_CLK,
MXC_I2C_CLK,
};
enum mxc_main_clock {
CPU_CLK,
AHB_CLK,
IPG_CLK,
IPG_PER_CLK,
NFC_CLK,
USB_CLK,
HSP_CLK,
};
enum mxc_peri_clock {
UART1_BAUD,
UART2_BAUD,
UART3_BAUD,
SSI1_BAUD,
SSI2_BAUD,
CSI_BAUD,
MSHC_CLK,
ESDHC1_CLK,
ESDHC2_CLK,
ESDHC3_CLK,
SPDIF_CLK,
SPI1_CLK,
SPI2_CLK,
};
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
#endif /* __ASM_ARCH_CLOCK_H */

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arch/arm/include/asm/arch-mx35/crm_regs.h
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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2004-2009 Freescale Semiconductor, Inc.
*/
#ifndef __CPU_ARM1136_MX35_CRM_REGS_H__
#define __CPU_ARM1136_MX35_CRM_REGS_H__
/* Register bit definitions */
#define MXC_CCM_CCMR_WFI (1 << 30)
#define MXC_CCM_CCMR_STBY_EXIT_SRC (1 << 29)
#define MXC_CCM_CCMR_VSTBY (1 << 28)
#define MXC_CCM_CCMR_WBEN (1 << 27)
#define MXC_CCM_CCMR_VOL_RDY_CNT_OFFSET 20
#define MXC_CCM_CCMR_VOL_RDY_CNT_MASK (0xF << 20)
#define MXC_CCM_CCMR_ROMW_OFFSET 18
#define MXC_CCM_CCMR_ROMW_MASK (0x3 << 18)
#define MXC_CCM_CCMR_RAMW_OFFSET 16
#define MXC_CCM_CCMR_RAMW_MASK (0x3 << 16)
#define MXC_CCM_CCMR_LPM_OFFSET 14
#define MXC_CCM_CCMR_LPM_MASK (0x3 << 14)
#define MXC_CCM_CCMR_UPE (1 << 9)
#define MXC_CCM_CCMR_MPE (1 << 3)
#define MXC_CCM_PDR0_PER_SEL (1 << 26)
#define MXC_CCM_PDR0_IPU_HND_BYP (1 << 23)
#define MXC_CCM_PDR0_HSP_PODF_OFFSET 20
#define MXC_CCM_PDR0_HSP_PODF_MASK (0x3 << 20)
#define MXC_CCM_PDR0_CON_MUX_DIV_OFFSET 16
#define MXC_CCM_PDR0_CON_MUX_DIV_MASK (0xF << 16)
#define MXC_CCM_PDR0_CKIL_SEL (1 << 15)
#define MXC_CCM_PDR0_PER_PODF_OFFSET 12
#define MXC_CCM_PDR0_PER_PODF_MASK (0x7 << 12)
#define MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET 9
#define MXC_CCM_PDR0_AUTO_MUX_DIV_MASK (0x7 << 9)
#define MXC_CCM_PDR0_AUTO_CON 0x1
#define MXC_CCM_PDR1_MSHC_PRDF_OFFSET 28
#define MXC_CCM_PDR1_MSHC_PRDF_MASK (0x7 << 28)
#define MXC_CCM_PDR1_MSHC_PODF_OFFSET 22
#define MXC_CCM_PDR1_MSHC_PODF_MASK (0x3F << 22)
#define MXC_CCM_PDR1_MSHC_M_U (1 << 7)
#define MXC_CCM_PDR2_SSI2_PRDF_OFFSET 27
#define MXC_CCM_PDR2_SSI2_PRDF_MASK (0x7 << 27)
#define MXC_CCM_PDR2_SSI1_PRDF_OFFSET 24
#define MXC_CCM_PDR2_SSI1_PRDF_MASK (0x7 << 24)
#define MXC_CCM_PDR2_CSI_PODF_OFFSET 16
#define MXC_CCM_PDR2_CSI_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR2_SSI2_PODF_OFFSET 8
#define MXC_CCM_PDR2_SSI2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR2_CSI_M_U (1 << 7)
#define MXC_CCM_PDR2_SSI_M_U (1 << 6)
#define MXC_CCM_PDR2_SSI1_PODF_OFFSET 0
#define MXC_CCM_PDR2_SSI1_PODF_MASK (0x3F)
#define MXC_CCM_PDR3_SPDIF_PRDF_OFFSET 29
#define MXC_CCM_PDR3_SPDIF_PRDF_MASK (0x7 << 29)
#define MXC_CCM_PDR3_SPDIF_PODF_OFFSET 23
#define MXC_CCM_PDR3_SPDIF_PODF_MASK (0x3F << 23)
#define MXC_CCM_PDR3_SPDIF_M_U (1 << 22)
#define MXC_CCM_PDR3_ESDHC3_PODF_OFFSET 16
#define MXC_CCM_PDR3_ESDHC3_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR3_UART_M_U (1 << 14)
#define MXC_CCM_PDR3_ESDHC2_PODF_OFFSET 8
#define MXC_CCM_PDR3_ESDHC2_PODF_MASK (0x3F << 8)
#define MXC_CCM_PDR3_ESDHC_M_U (1 << 6)
#define MXC_CCM_PDR3_ESDHC1_PODF_OFFSET 0
#define MXC_CCM_PDR3_ESDHC1_PODF_MASK (0x3F)
#define MXC_CCM_PDR4_NFC_PODF_OFFSET 28
#define MXC_CCM_PDR4_NFC_PODF_MASK (0xF << 28)
#define MXC_CCM_PDR4_USB_PODF_OFFSET 22
#define MXC_CCM_PDR4_USB_PODF_MASK (0x3F << 22)
#define MXC_CCM_PDR4_PER0_PODF_OFFSET 16
#define MXC_CCM_PDR4_PER0_PODF_MASK (0x3F << 16)
#define MXC_CCM_PDR4_UART_PODF_OFFSET 10
#define MXC_CCM_PDR4_UART_PODF_MASK (0x3F << 10)
#define MXC_CCM_PDR4_USB_M_U (1 << 9)
/* Bit definitions for RCSR */
#define MXC_CCM_RCSR_BUS_WIDTH (1 << 29)
#define MXC_CCM_RCSR_BUS_16BIT (1 << 29)
#define MXC_CCM_RCSR_PAGE_SIZE (3 << 27)
#define MXC_CCM_RCSR_PAGE_512 (0 << 27)
#define MXC_CCM_RCSR_PAGE_2K (1 << 27)
#define MXC_CCM_RCSR_PAGE_4K1 (2 << 27)
#define MXC_CCM_RCSR_PAGE_4K2 (3 << 27)
#define MXC_CCM_RCSR_SOFT_RESET (1 << 15)
#define MXC_CCM_RCSR_NF16B (1 << 14)
#define MXC_CCM_RCSR_NFC_4K (1 << 9)
#define MXC_CCM_RCSR_NFC_FMS (1 << 8)
/* Bit definitions for both MCU, PERIPHERAL PLL control registers */
#define MXC_CCM_PCTL_BRM 0x80000000
#define MXC_CCM_PCTL_PD_OFFSET 26
#define MXC_CCM_PCTL_PD_MASK (0xF << 26)
#define MXC_CCM_PCTL_MFD_OFFSET 16
#define MXC_CCM_PCTL_MFD_MASK (0x3FF << 16)
#define MXC_CCM_PCTL_MFI_OFFSET 10
#define MXC_CCM_PCTL_MFI_MASK (0xF << 10)
#define MXC_CCM_PCTL_MFN_OFFSET 0
#define MXC_CCM_PCTL_MFN_MASK 0x3FF
/* Bit definitions for Audio clock mux register*/
#define MXC_CCM_ACMR_ESAI_CLK_SEL_OFFSET 12
#define MXC_CCM_ACMR_ESAI_CLK_SEL_MASK (0xF << 12)
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_OFFSET 8
#define MXC_CCM_ACMR_SPDIF_CLK_SEL_MASK (0xF << 8)
#define MXC_CCM_ACMR_SSI1_CLK_SEL_OFFSET 4
#define MXC_CCM_ACMR_SSI1_CLK_SEL_MASK (0xF << 4)
#define MXC_CCM_ACMR_SSI2_CLK_SEL_OFFSET 0
#define MXC_CCM_ACMR_SSI2_CLK_SEL_MASK (0xF << 0)
/* Bit definitions for Clock gating Register*/
#define MXC_CCM_CGR_CG_MASK 0x3
#define MXC_CCM_CGR_CG_OFF 0x0
#define MXC_CCM_CGR_CG_RUN_ON 0x1
#define MXC_CCM_CGR_CG_RUN_WAIT_ON 0x2
#define MXC_CCM_CGR_CG_ON 0x3
#define MXC_CCM_CGR0_ASRC_OFFSET 0
#define MXC_CCM_CGR0_ASRC_MASK (0x3 << 0)
#define MXC_CCM_CGR0_ATA_OFFSET 2
#define MXC_CCM_CGR0_ATA_MASK (0x3 << 2)
#define MXC_CCM_CGR0_CAN1_OFFSET 6
#define MXC_CCM_CGR0_CAN1_MASK (0x3 << 6)
#define MXC_CCM_CGR0_CAN2_OFFSET 8
#define MXC_CCM_CGR0_CAN2_MASK (0x3 << 8)
#define MXC_CCM_CGR0_CSPI1_OFFSET 10
#define MXC_CCM_CGR0_CSPI1_MASK (0x3 << 10)
#define MXC_CCM_CGR0_CSPI2_OFFSET 12
#define MXC_CCM_CGR0_CSPI2_MASK (0x3 << 12)
#define MXC_CCM_CGR0_ECT_OFFSET 14
#define MXC_CCM_CGR0_ECT_MASK (0x3 << 14)
#define MXC_CCM_CGR0_EDIO_OFFSET 16
#define MXC_CCM_CGR0_EDIO_MASK (0x3 << 16)
#define MXC_CCM_CGR0_EMI_OFFSET 18
#define MXC_CCM_CGR0_EMI_MASK (0x3 << 18)
#define MXC_CCM_CGR0_EPIT1_OFFSET 20
#define MXC_CCM_CGR0_EPIT1_MASK (0x3 << 20)
#define MXC_CCM_CGR0_EPIT2_OFFSET 22
#define MXC_CCM_CGR0_EPIT2_MASK (0x3 << 22)
#define MXC_CCM_CGR0_ESAI_OFFSET 24
#define MXC_CCM_CGR0_ESAI_MASK (0x3 << 24)
#define MXC_CCM_CGR0_ESDHC1_OFFSET 26
#define MXC_CCM_CGR0_ESDHC1_MASK (0x3 << 26)
#define MXC_CCM_CGR0_ESDHC2_OFFSET 28
#define MXC_CCM_CGR0_ESDHC2_MASK (0x3 << 28)
#define MXC_CCM_CGR0_ESDHC3_OFFSET 30
#define MXC_CCM_CGR0_ESDHC3_MASK (0x3 << 30)
#define MXC_CCM_CGR1_FEC_OFFSET 0
#define MXC_CCM_CGR1_FEC_MASK (0x3 << 0)
#define MXC_CCM_CGR1_GPIO1_OFFSET 2
#define MXC_CCM_CGR1_GPIO1_MASK (0x3 << 2)
#define MXC_CCM_CGR1_GPIO2_OFFSET 4
#define MXC_CCM_CGR1_GPIO2_MASK (0x3 << 4)
#define MXC_CCM_CGR1_GPIO3_OFFSET 6
#define MXC_CCM_CGR1_GPIO3_MASK (0x3 << 6)
#define MXC_CCM_CGR1_GPT_OFFSET 8
#define MXC_CCM_CGR1_GPT_MASK (0x3 << 8)
#define MXC_CCM_CGR1_I2C1_OFFSET 10
#define MXC_CCM_CGR1_I2C1_MASK (0x3 << 10)
#define MXC_CCM_CGR1_I2C2_OFFSET 12
#define MXC_CCM_CGR1_I2C2_MASK (0x3 << 12)
#define MXC_CCM_CGR1_I2C3_OFFSET 14
#define MXC_CCM_CGR1_I2C3_MASK (0x3 << 14)
#define MXC_CCM_CGR1_IOMUXC_OFFSET 16
#define MXC_CCM_CGR1_IOMUXC_MASK (0x3 << 16)
#define MXC_CCM_CGR1_IPU_OFFSET 18
#define MXC_CCM_CGR1_IPU_MASK (0x3 << 18)
#define MXC_CCM_CGR1_KPP_OFFSET 20
#define MXC_CCM_CGR1_KPP_MASK (0x3 << 20)
#define MXC_CCM_CGR1_MLB_OFFSET 22
#define MXC_CCM_CGR1_MLB_MASK (0x3 << 22)
#define MXC_CCM_CGR1_MSHC_OFFSET 24
#define MXC_CCM_CGR1_MSHC_MASK (0x3 << 24)
#define MXC_CCM_CGR1_OWIRE_OFFSET 26
#define MXC_CCM_CGR1_OWIRE_MASK (0x3 << 26)
#define MXC_CCM_CGR1_PWM_OFFSET 28
#define MXC_CCM_CGR1_PWM_MASK (0x3 << 28)
#define MXC_CCM_CGR1_RNGC_OFFSET 30
#define MXC_CCM_CGR1_RNGC_MASK (0x3 << 30)
#define MXC_CCM_CGR2_RTC_OFFSET 0
#define MXC_CCM_CGR2_RTC_MASK (0x3 << 0)
#define MXC_CCM_CGR2_RTIC_OFFSET 2
#define MXC_CCM_CGR2_RTIC_MASK (0x3 << 2)
#define MXC_CCM_CGR2_SCC_OFFSET 4
#define MXC_CCM_CGR2_SCC_MASK (0x3 << 4)
#define MXC_CCM_CGR2_SDMA_OFFSET 6
#define MXC_CCM_CGR2_SDMA_MASK (0x3 << 6)
#define MXC_CCM_CGR2_SPBA_OFFSET 8
#define MXC_CCM_CGR2_SPBA_MASK (0x3 << 8)
#define MXC_CCM_CGR2_SPDIF_OFFSET 10
#define MXC_CCM_CGR2_SPDIF_MASK (0x3 << 10)
#define MXC_CCM_CGR2_SSI1_OFFSET 12
#define MXC_CCM_CGR2_SSI1_MASK (0x3 << 12)
#define MXC_CCM_CGR2_SSI2_OFFSET 14
#define MXC_CCM_CGR2_SSI2_MASK (0x3 << 14)
#define MXC_CCM_CGR2_UART1_OFFSET 16
#define MXC_CCM_CGR2_UART1_MASK (0x3 << 16)
#define MXC_CCM_CGR2_UART2_OFFSET 18
#define MXC_CCM_CGR2_UART2_MASK (0x3 << 18)
#define MXC_CCM_CGR2_UART3_OFFSET 20
#define MXC_CCM_CGR2_UART3_MASK (0x3 << 20)
#define MXC_CCM_CGR2_USBOTG_OFFSET 22
#define MXC_CCM_CGR2_USBOTG_MASK (0x3 << 22)
#define MXC_CCM_CGR2_WDOG_OFFSET 24
#define MXC_CCM_CGR2_WDOG_MASK (0x3 << 24)
#define MXC_CCM_CGR2_MAX_OFFSET 26
#define MXC_CCM_CGR2_MAX_MASK (0x3 << 26)
#define MXC_CCM_CGR2_MAX_ENABLE (0x2 << 26)
#define MXC_CCM_CGR2_AUDMUX_OFFSET 30
#define MXC_CCM_CGR2_AUDMUX_MASK (0x3 << 30)
#define MXC_CCM_CGR3_CSI_OFFSET 0
#define MXC_CCM_CGR3_CSI_MASK (0x3 << 0)
#define MXC_CCM_CGR3_IIM_OFFSET 2
#define MXC_CCM_CGR3_IIM_MASK (0x3 << 2)
#define MXC_CCM_CGR3_GPU2D_OFFSET 4
#define MXC_CCM_CGR3_GPU2D_MASK (0x3 << 4)
#define MXC_CCM_COSR_CLKOSEL_MASK 0x1F
#define MXC_CCM_COSR_CLKOSEL_OFFSET 0
#define MXC_CCM_COSR_CLKOEN (1 << 5)
#define MXC_CCM_COSR_CLKOUTDIV_1 (1 << 6)
#define MXC_CCM_COSR_CLKOUT_DIV_MASK (0x3F << 10)
#define MXC_CCM_COSR_CLKOUT_DIV_OFFSET 10
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_MASK (0x3 << 16)
#define MXC_CCM_COSR_SSI1_RX_SRC_SEL_OFFSET 16
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_MASK (0x3 << 18)
#define MXC_CCM_COSR_SSI1_TX_SRC_SEL_OFFSET 18
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_MASK (0x3 << 20)
#define MXC_CCM_COSR_SSI2_RX_SRC_SEL_OFFSET 20
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_MASK (0x3 << 22)
#define MXC_CCM_COSR_SSI2_TX_SRC_SEL_OFFSET 22
#define MXC_CCM_COSR_ASRC_AUDIO_EN (1 << 24)
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_MASK (0x3F << 26)
#define MXC_CCM_COSR_ASRC_AUDIO_PODF_OFFSET 26
#endif

13
arch/arm/include/asm/arch-mx35/gpio.h
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@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2011
* Stefano Babic, DENX Software Engineering, <sbabic@denx.de>
*/
#ifndef __ASM_ARCH_MX35_GPIO_H
#define __ASM_ARCH_MX35_GPIO_H
#include <asm/mach-imx/gpio.h>
#endif

356
arch/arm/include/asm/arch-mx35/imx-regs.h
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@ -1,356 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
*
* (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
*/
#ifndef __ASM_ARCH_MX35_H
#define __ASM_ARCH_MX35_H
#define ARCH_MXC
/*
* IRAM
*/
#define IRAM_BASE_ADDR 0x10000000 /* internal ram */
#define IRAM_SIZE 0x00020000 /* 128 KB */
#define LOW_LEVEL_SRAM_STACK 0x1001E000
/*
* AIPS 1
*/
#define AIPS1_BASE_ADDR 0x43F00000
#define AIPS1_CTRL_BASE_ADDR AIPS1_BASE_ADDR
#define MAX_BASE_ADDR 0x43F04000
#define EVTMON_BASE_ADDR 0x43F08000
#define CLKCTL_BASE_ADDR 0x43F0C000
#define I2C1_BASE_ADDR 0x43F80000
#define I2C3_BASE_ADDR 0x43F84000
#define ATA_BASE_ADDR 0x43F8C000
#define UART1_BASE 0x43F90000
#define UART2_BASE 0x43F94000
#define I2C2_BASE_ADDR 0x43F98000
#define CSPI1_BASE_ADDR 0x43FA4000
#define IOMUXC_BASE_ADDR 0x43FAC000
/*
* SPBA
*/
#define SPBA_BASE_ADDR 0x50000000
#define UART3_BASE 0x5000C000
#define CSPI2_BASE_ADDR 0x50010000
#define ATA_DMA_BASE_ADDR 0x50020000
#define FEC_BASE_ADDR 0x50038000
#define SPBA_CTRL_BASE_ADDR 0x5003C000
/*
* AIPS 2
*/
#define AIPS2_BASE_ADDR 0x53F00000
#define AIPS2_CTRL_BASE_ADDR AIPS2_BASE_ADDR
#define CCM_BASE_ADDR 0x53F80000
#define GPT1_BASE_ADDR 0x53F90000
#define EPIT1_BASE_ADDR 0x53F94000
#define EPIT2_BASE_ADDR 0x53F98000
#define GPIO3_BASE_ADDR 0x53FA4000
#define MMC_SDHC1_BASE_ADDR 0x53FB4000
#define MMC_SDHC2_BASE_ADDR 0x53FB8000
#define MMC_SDHC3_BASE_ADDR 0x53FBC000
#define IPU_CTRL_BASE_ADDR 0x53FC0000
#define GPIO1_BASE_ADDR 0x53FCC000
#define GPIO2_BASE_ADDR 0x53FD0000
#define SDMA_BASE_ADDR 0x53FD4000
#define RTC_BASE_ADDR 0x53FD8000
#define WDOG1_BASE_ADDR 0x53FDC000
#define PWM_BASE_ADDR 0x53FE0000
#define RTIC_BASE_ADDR 0x53FEC000
#define IIM_BASE_ADDR 0x53FF0000
#define IMX_USB_BASE 0x53FF4000
#define IMX_USB_PORT_OFFSET 0x400
#define IMX_CCM_BASE CCM_BASE_ADDR
/*
* ROMPATCH and AVIC
*/
#define ROMPATCH_BASE_ADDR 0x60000000
#define AVIC_BASE_ADDR 0x68000000
/*
* NAND, SDRAM, WEIM, M3IF, EMI controllers
*/
#define EXT_MEM_CTRL_BASE 0xB8000000
#define ESDCTL_BASE_ADDR 0xB8001000
#define WEIM_BASE_ADDR 0xB8002000
#define WEIM_CTRL_CS0 WEIM_BASE_ADDR
#define WEIM_CTRL_CS1 (WEIM_BASE_ADDR + 0x10)
#define WEIM_CTRL_CS2 (WEIM_BASE_ADDR + 0x20)
#define WEIM_CTRL_CS3 (WEIM_BASE_ADDR + 0x30)
#define WEIM_CTRL_CS4 (WEIM_BASE_ADDR + 0x40)
#define WEIM_CTRL_CS5 (WEIM_BASE_ADDR + 0x50)
#define M3IF_BASE_ADDR 0xB8003000
#define EMI_BASE_ADDR 0xB8004000
#define NFC_BASE_ADDR 0xBB000000
/*
* Memory regions and CS
*/
#define IPU_MEM_BASE_ADDR 0x70000000
#define CSD0_BASE_ADDR 0x80000000
#define CSD1_BASE_ADDR 0x90000000
#define CS0_BASE_ADDR 0xA0000000
#define CS1_BASE_ADDR 0xA8000000
#define CS2_BASE_ADDR 0xB0000000
#define CS3_BASE_ADDR 0xB2000000
#define CS4_BASE_ADDR 0xB4000000
#define CS5_BASE_ADDR 0xB6000000
/*
* IRQ Controller Register Definitions.
*/
#define AVIC_NIMASK 0x04
#define AVIC_INTTYPEH 0x18
#define AVIC_INTTYPEL 0x1C
/* L210 */
#define L2CC_BASE_ADDR 0x30000000
#define L2_CACHE_LINE_SIZE 32
#define L2_CACHE_CTL_REG 0x100
#define L2_CACHE_AUX_CTL_REG 0x104
#define L2_CACHE_SYNC_REG 0x730
#define L2_CACHE_INV_LINE_REG 0x770
#define L2_CACHE_INV_WAY_REG 0x77C
#define L2_CACHE_CLEAN_LINE_REG 0x7B0
#define L2_CACHE_CLEAN_INV_LINE_REG 0x7F0
#define L2_CACHE_DBG_CTL_REG 0xF40
#define CLKMODE_AUTO 0
#define CLKMODE_CONSUMER 1
#define PLL_PD(x) (((x) & 0xf) << 26)
#define PLL_MFD(x) (((x) & 0x3ff) << 16)
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
#define _PLL_BRM(x) ((x) << 31)
#define _PLL_PD(x) (((x) - 1) << 26)
#define _PLL_MFD(x) (((x) - 1) << 16)
#define _PLL_MFI(x) ((x) << 10)
#define _PLL_MFN(x) (x)
#define _PLL_SETTING(brm, pd, mfd, mfi, mfn) \
(_PLL_BRM(brm) | _PLL_PD(pd) | _PLL_MFD(mfd) | _PLL_MFI(mfi) |\
_PLL_MFN(mfn))
#define CCM_MPLL_532_HZ _PLL_SETTING(1, 1, 12, 11, 1)
#define CCM_MPLL_399_HZ _PLL_SETTING(0, 1, 16, 8, 5)
#define CCM_PPLL_300_HZ _PLL_SETTING(0, 1, 4, 6, 1)
#define CSCR_U(x) (WEIM_CTRL_CS#x + 0)
#define CSCR_L(x) (WEIM_CTRL_CS#x + 4)
#define CSCR_A(x) (WEIM_CTRL_CS#x + 8)
#define IIM_SREV 0x24
#define ROMPATCH_REV 0x40
#define IPU_CONF IPU_CTRL_BASE_ADDR
#define IPU_CONF_PXL_ENDIAN (1<<8)
#define IPU_CONF_DU_EN (1<<7)
#define IPU_CONF_DI_EN (1<<6)
#define IPU_CONF_ADC_EN (1<<5)
#define IPU_CONF_SDC_EN (1<<4)
#define IPU_CONF_PF_EN (1<<3)
#define IPU_CONF_ROT_EN (1<<2)
#define IPU_CONF_IC_EN (1<<1)
#define IPU_CONF_CSI_EN (1<<0)
/*
* CSPI register definitions
*/
#define MXC_SPI_BASE_ADDRESSES \
0x43fa4000, \
0x50010000,
#define GPIO_PORT_NUM 3
#define GPIO_NUM_PIN 32
#define CHIP_REV_1_0 0x10
#define CHIP_REV_2_0 0x20
#define BOARD_REV_1_0 0x0
#define BOARD_REV_2_0 0x1
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/types.h>
/* Clock Control Module (CCM) registers */
struct ccm_regs {
u32 ccmr; /* Control */
u32 pdr0; /* Post divider 0 */
u32 pdr1; /* Post divider 1 */
u32 pdr2; /* Post divider 2 */
u32 pdr3; /* Post divider 3 */
u32 pdr4; /* Post divider 4 */
u32 rcsr; /* CCM Status */
u32 mpctl; /* Core PLL Control */
u32 ppctl; /* Peripheral PLL Control */
u32 acmr; /* Audio clock mux */
u32 cosr; /* Clock out source */
u32 cgr0; /* Clock Gating Control 0 */
u32 cgr1; /* Clock Gating Control 1 */
u32 cgr2; /* Clock Gating Control 2 */
u32 cgr3; /* Clock Gating Control 3 */
u32 reserved;
u32 dcvr0; /* DPTC Comparator 0 */
u32 dcvr1; /* DPTC Comparator 0 */
u32 dcvr2; /* DPTC Comparator 0 */
u32 dcvr3; /* DPTC Comparator 0 */
u32 ltr0; /* Load Tracking 0 */
u32 ltr1; /* Load Tracking 1 */
u32 ltr2; /* Load Tracking 2 */
u32 ltr3; /* Load Tracking 3 */
u32 ltbr0; /* Load Tracking Buffer 0 */
};
/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
u32 iim_err;
u32 iim_emask;
u32 iim_fctl;
u32 iim_ua;
u32 iim_la;
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
} bank[3];
};
struct fuse_bank0_regs {
u32 fuse0_7[8];
u32 uid[8];
u32 fuse16_31[0x10];
};
struct fuse_bank1_regs {
u32 fuse0_21[0x16];
u32 usr;
u32 fuse23_31[9];
};
/* General Purpose Timer (GPT) registers */
struct gpt_regs {
u32 ctrl; /* control */
u32 pre; /* prescaler */
u32 stat; /* status */
u32 intr; /* interrupt */
u32 cmp[3]; /* output compare 1-3 */
u32 capt[2]; /* input capture 1-2 */
u32 counter; /* counter */
};
struct esdc_regs {
u32 esdctl0;
u32 esdcfg0;
u32 esdctl1;
u32 esdcfg1;
u32 esdmisc;
u32 reserved[4];
u32 esdcdly[5];
u32 esdcdlyl;
};
#define ESDC_MISC_RST (1 << 1)
#define ESDC_MISC_MDDR_EN (1 << 2)
#define ESDC_MISC_MDDR_DL_RST (1 << 3)
#define ESDC_MISC_DDR_EN (1 << 8)
#define ESDC_MISC_DDR2_EN (1 << 9)
/* Multi-Layer AHB Crossbar Switch (MAX) registers */
struct max_regs {
u32 mpr0;
u32 pad00[3];
u32 sgpcr0;
u32 pad01[59];
u32 mpr1;
u32 pad02[3];
u32 sgpcr1;
u32 pad03[59];
u32 mpr2;
u32 pad04[3];
u32 sgpcr2;
u32 pad05[59];
u32 mpr3;
u32 pad06[3];
u32 sgpcr3;
u32 pad07[59];
u32 mpr4;
u32 pad08[3];
u32 sgpcr4;
u32 pad09[251];
u32 mgpcr0;
u32 pad10[63];
u32 mgpcr1;
u32 pad11[63];
u32 mgpcr2;
u32 pad12[63];
u32 mgpcr3;
u32 pad13[63];
u32 mgpcr4;
u32 pad14[63];
u32 mgpcr5;
};
/* AHB <-> IP-Bus Interface (AIPS) */
struct aips_regs {
u32 mpr_0_7;
u32 mpr_8_15;
u32 pad0[6];
u32 pacr_0_7;
u32 pacr_8_15;
u32 pacr_16_23;
u32 pacr_24_31;
u32 pad1[4];
u32 opacr_0_7;
u32 opacr_8_15;
u32 opacr_16_23;
u32 opacr_24_31;
u32 opacr_32_39;
};
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/
#define NFMS_BIT 8
#define NFMS_NF_DWIDTH 14
#define NFMS_NF_PG_SZ 8
#define CCM_RCSR_NF_16BIT_SEL (1 << 14)
#endif
/*
* Generic timer support
*/
#ifdef CONFIG_MX35_CLK32
#define CONFIG_SYS_TIMER_RATE CONFIG_MX35_CLK32
#else
#define CONFIG_SYS_TIMER_RATE 32768
#endif
#define CONFIG_SYS_TIMER_COUNTER (GPT1_BASE_ADDR+36)
#endif /* __ASM_ARCH_MX35_H */

1259
arch/arm/include/asm/arch-mx35/iomux-mx35.h
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125
arch/arm/include/asm/arch-mx35/lowlevel_macro.S
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@ -1,125 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*/
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
#include <asm/macro.h>
/*
* AIPS setup - Only setup MPROTx registers.
* The PACR default values are good.
*
* Default argument values:
* - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
* user-mode.
* - OPACR: Clear the on and off peripheral modules Supervisor Protect bit for
* SDMA to access them.
*/
.macro init_aips mpr=0x77777777, opacr=0x00000000
ldr r0, =AIPS1_BASE_ADDR
ldr r1, =\mpr
str r1, [r0, #AIPS_MPR_0_7]
str r1, [r0, #AIPS_MPR_8_15]
ldr r2, =AIPS2_BASE_ADDR
str r1, [r2, #AIPS_MPR_0_7]
str r1, [r2, #AIPS_MPR_8_15]
/* Did not change the AIPS control registers access type. */
ldr r1, =\opacr
str r1, [r0, #AIPS_OPACR_0_7]
str r1, [r0, #AIPS_OPACR_8_15]
str r1, [r0, #AIPS_OPACR_16_23]
str r1, [r0, #AIPS_OPACR_24_31]
str r1, [r0, #AIPS_OPACR_32_39]
str r1, [r2, #AIPS_OPACR_0_7]
str r1, [r2, #AIPS_OPACR_8_15]
str r1, [r2, #AIPS_OPACR_16_23]
str r1, [r2, #AIPS_OPACR_24_31]
str r1, [r2, #AIPS_OPACR_32_39]
.endm
/*
* MAX (Multi-Layer AHB Crossbar Switch) setup
*
* Default argument values:
* - MPR: priority is M4 > M2 > M3 > M5 > M0 > M1
* - SGPCR: always park on last master
* - MGPCR: restore default values
*/
.macro init_max mpr=0x00302154, sgpcr=0x00000010, mgpcr=0x00000000
ldr r0, =MAX_BASE_ADDR
ldr r1, =\mpr
str r1, [r0, #MAX_MPR0] /* for S0 */
str r1, [r0, #MAX_MPR1] /* for S1 */
str r1, [r0, #MAX_MPR2] /* for S2 */
str r1, [r0, #MAX_MPR3] /* for S3 */
str r1, [r0, #MAX_MPR4] /* for S4 */
ldr r1, =\sgpcr
str r1, [r0, #MAX_SGPCR0] /* for S0 */
str r1, [r0, #MAX_SGPCR1] /* for S1 */
str r1, [r0, #MAX_SGPCR2] /* for S2 */
str r1, [r0, #MAX_SGPCR3] /* for S3 */
str r1, [r0, #MAX_SGPCR4] /* for S4 */
ldr r1, =\mgpcr
str r1, [r0, #MAX_MGPCR0] /* for M0 */
str r1, [r0, #MAX_MGPCR1] /* for M1 */
str r1, [r0, #MAX_MGPCR2] /* for M2 */
str r1, [r0, #MAX_MGPCR3] /* for M3 */
str r1, [r0, #MAX_MGPCR4] /* for M4 */
str r1, [r0, #MAX_MGPCR5] /* for M5 */
.endm
/*
* M3IF setup
*
* Default argument values:
* - CTL:
* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
* MRRP[1] = L2CC1 not on priority list (0 << 1) = 0x00000000
* MRRP[2] = MBX not on priority list (0 << 2) = 0x00000000
* MRRP[3] = MAX1 not on priority list (0 << 3) = 0x00000000
* MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
* MRRP[5] = MPEG4 not on priority list (0 << 5) = 0x00000000
* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
* MRRP[7] = IPU2 not on priority list (0 << 7) = 0x00000000
* ------------
* 0x00000040
*/
.macro init_m3if ctl=0x00000040
/* M3IF Control Register (M3IFCTL) */
write32 M3IF_BASE_ADDR, \ctl
.endm
.macro core_init
mrc p15, 0, r1, c1, c0, 0
/* Set branch prediction enable */
mrc p15, 0, r0, c1, c0, 1
orr r0, r0, #7
mcr p15, 0, r0, c1, c0, 1
orr r1, r1, #1 << 11
/* Set unaligned access enable */
orr r1, r1, #1 << 22
/* Set low int latency enable */
orr r1, r1, #1 << 21
mcr p15, 0, r1, c1, c0, 0
mov r0, #0
mcr p15, 0, r0, c15, c2, 4
mcr p15, 0, r0, c7, c7, 0 /* Invalidate I cache and D cache */
mcr p15, 0, r0, c8, c7, 0 /* Invalidate TLBs */
mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
/* Setup the Peripheral Port Memory Remap Register */
ldr r0, =0x40000015 /* Start from AIPS 2-GB region */
mcr p15, 0, r0, c15, c2, 4
.endm

14
arch/arm/include/asm/arch-mx35/mmc_host_def.h
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@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* (C) Copyright 2008
* Texas Instruments, <www.ti.com>
* Syed Mohammed Khasim <khasim@ti.com>
*/
#ifndef MMC_HOST_DEF_H
#define MMC_HOST_DEF_H
/* Driver definitions */
#define MMCSD_SECTOR_SIZE 512
#endif /* MMC_HOST_DEF_H */

15
arch/arm/include/asm/arch-mx35/sys_proto.h
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@ -1,15 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
*/
#ifndef _MX35_SYS_PROTO_H_
#define _MX35_SYS_PROTO_H_
#include <asm/mach-imx/sys_proto.h>
void mx3_setup_sdram_bank(u32 start_address, u32 ddr2_config, u32 row,
u32 col, u32 dsize, u32 refresh);
#endif

88
arch/arm/lib/asm-offsets.c
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@ -15,7 +15,7 @@
#include <linux/kbuild.h> #include <linux/kbuild.h>
#include <linux/arm-smccc.h> #include <linux/arm-smccc.h>
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \ #if defined(CONFIG_MX27) \
|| defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>
#endif #endif
@ -35,42 +35,6 @@ int main(void)
* code. Is it better to define the macros directly in headers? * code. Is it better to define the macros directly in headers?
*/ */
#if defined(CONFIG_MX25)
/* Clock Control Module */
DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CCM_CGCR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CCM_CGCR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CCM_PCDR2, offsetof(struct ccm_regs, pcdr[2]));
DEFINE(CCM_MCR, offsetof(struct ccm_regs, mcr));
/* Enhanced SDRAM Controller */
DEFINE(ESDRAMC_ESDCTL0, offsetof(struct esdramc_regs, ctl0));
DEFINE(ESDRAMC_ESDCFG0, offsetof(struct esdramc_regs, cfg0));
DEFINE(ESDRAMC_ESDMISC, offsetof(struct esdramc_regs, misc));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
#endif
#if defined(CONFIG_MX27) #if defined(CONFIG_MX27)
DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0)); DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1)); DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
@ -97,56 +61,6 @@ int main(void)
offsetof(struct system_control_regs, fmcr)); offsetof(struct system_control_regs, fmcr));
#endif #endif
#if defined(CONFIG_MX35)
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
DEFINE(CLKCTL_PDR1, offsetof(struct ccm_regs, pdr1));
DEFINE(CLKCTL_PDR2, offsetof(struct ccm_regs, pdr2));
DEFINE(CLKCTL_PDR3, offsetof(struct ccm_regs, pdr3));
DEFINE(CLKCTL_PDR4, offsetof(struct ccm_regs, pdr4));
DEFINE(CLKCTL_RCSR, offsetof(struct ccm_regs, rcsr));
DEFINE(CLKCTL_MPCTL, offsetof(struct ccm_regs, mpctl));
DEFINE(CLKCTL_PPCTL, offsetof(struct ccm_regs, ppctl));
DEFINE(CLKCTL_ACMR, offsetof(struct ccm_regs, acmr));
DEFINE(CLKCTL_COSR, offsetof(struct ccm_regs, cosr));
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
/* Multi-Layer AHB Crossbar Switch */
DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
/* AHB <-> IP-Bus Interface */
DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
#endif
#if defined(CONFIG_MX51) || defined(CONFIG_MX53) #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Round up to make sure size gives nice stack alignment */ /* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr)); DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));

23
arch/arm/mach-imx/mx2/Kconfig
View File

@ -1,23 +0,0 @@
if ARCH_MX25
config MX25
bool
default y
select SYS_FSL_ERRATUM_ESDHC_A001
choice
prompt "MX25 board select"
optional
config TARGET_ZMX25
bool "Support zmx25"
select BOARD_LATE_INIT
select CPU_ARM926EJS
endchoice
config SYS_SOC
default "mx25"
source "board/syteco/zmx25/Kconfig"
endif

4
arch/arm/mach-imx/mxs/Kconfig
View File

@ -39,9 +39,6 @@ choice
prompt "MX28 board select" prompt "MX28 board select"
optional optional
config TARGET_BG0900
bool "Support bg0900"
config TARGET_MX28EVK config TARGET_MX28EVK
bool "Support mx28evk" bool "Support mx28evk"
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F
@ -56,6 +53,5 @@ config SYS_SOC
source "board/freescale/mx28evk/Kconfig" source "board/freescale/mx28evk/Kconfig"
source "board/liebherr/xea/Kconfig" source "board/liebherr/xea/Kconfig"
source "board/ppcag/bg0900/Kconfig"
endif endif

52
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -8,22 +8,6 @@ choice
prompt "Target select" prompt "Target select"
optional optional
config TARGET_MPC8349EMDS
bool "Support MPC8349EMDS"
select ARCH_MPC8349
select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_HAS_DDR2
config TARGET_MPC8349EMDS_SDRAM
bool "Support MPC8349EMDS_SDRAM"
select ARCH_MPC8349
select BOARD_EARLY_INIT_F
select SYS_FSL_DDR
select SYS_FSL_DDR_BE
select SYS_FSL_HAS_DDR2
config TARGET_MPC837XERDB config TARGET_MPC837XERDB
bool "Support MPC837XERDB" bool "Support MPC837XERDB"
select ARCH_MPC837X select ARCH_MPC837X
@ -173,15 +157,6 @@ config ARCH_MPC834X
bool bool
select SYS_CACHE_SHIFT_5 select SYS_CACHE_SHIFT_5
config ARCH_MPC8349
bool
select ARCH_MPC834X
select MPC83XX_PCI_SUPPORT
select MPC83XX_TSEC1_SUPPORT
select MPC83XX_TSEC2_SUPPORT
select MPC83XX_LDP_PIN
select MPC83XX_SECOND_I2C
config ARCH_MPC8360 config ARCH_MPC8360
bool bool
select MPC83XX_QUICC_ENGINE select MPC83XX_QUICC_ENGINE
@ -220,36 +195,9 @@ source "arch/powerpc/cpu/mpc83xx/sysio/Kconfig"
source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig" source "arch/powerpc/cpu/mpc83xx/arbiter/Kconfig"
source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig" source "arch/powerpc/cpu/mpc83xx/initreg/Kconfig"
menu "Legacy options"
if ARCH_MPC8349
#TODO(mario.six@gdsys.cc): Remove when mpc83xx PCI has been converted to DM/DT
choice
prompt "PMC slot configuration"
config PCI_ALL_PCI1
bool "All PMC slots on PCI1"
config PCI_ONE_PCI1
bool "First PMC1 on PCI1"
config PCI_TWO_PCI1
bool "First two PMC1 on PCI1"
endchoice
config PCI_64BIT
bool "PMC2 is 64bit"
endif
endmenu
config FSL_ELBC config FSL_ELBC
bool bool
source "board/freescale/mpc8349emds/Kconfig"
source "board/freescale/mpc837xerdb/Kconfig" source "board/freescale/mpc837xerdb/Kconfig"
source "board/ids/ids8313/Kconfig" source "board/ids/ids8313/Kconfig"
source "board/keymile/Kconfig" source "board/keymile/Kconfig"

6
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc0
View File

@ -22,7 +22,7 @@ config BR0_PORTSIZE_16BIT
config BR0_PORTSIZE_32BIT config BR0_PORTSIZE_32BIT
depends on !BR0_MACHINE_FCM depends on !BR0_MACHINE_FCM
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit" bool "32-bit"
endchoice endchoice
@ -58,11 +58,11 @@ config BR0_MACHINE_GPCM
bool "GPCM" bool "GPCM"
config BR0_MACHINE_FCM config BR0_MACHINE_FCM
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM" bool "FCM"
config BR0_MACHINE_SDRAM config BR0_MACHINE_SDRAM
depends on ARCH_MPC8349 || ARCH_MPC8360 depends on ARCH_MPC8360
bool "SDRAM" bool "SDRAM"
config BR0_MACHINE_UPMA config BR0_MACHINE_UPMA

6
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc1
View File

@ -22,7 +22,7 @@ config BR1_PORTSIZE_16BIT
config BR1_PORTSIZE_32BIT config BR1_PORTSIZE_32BIT
depends on !BR1_MACHINE_FCM depends on !BR1_MACHINE_FCM
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit" bool "32-bit"
endchoice endchoice
@ -58,11 +58,11 @@ config BR1_MACHINE_GPCM
bool "GPCM" bool "GPCM"
config BR1_MACHINE_FCM config BR1_MACHINE_FCM
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM" bool "FCM"
config BR1_MACHINE_SDRAM config BR1_MACHINE_SDRAM
depends on ARCH_MPC8349 || ARCH_MPC8360 depends on ARCH_MPC8360
bool "SDRAM" bool "SDRAM"
config BR1_MACHINE_UPMA config BR1_MACHINE_UPMA

6
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc2
View File

@ -22,7 +22,7 @@ config BR2_PORTSIZE_16BIT
config BR2_PORTSIZE_32BIT config BR2_PORTSIZE_32BIT
depends on !BR2_MACHINE_FCM depends on !BR2_MACHINE_FCM
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit" bool "32-bit"
endchoice endchoice
@ -58,11 +58,11 @@ config BR2_MACHINE_GPCM
bool "GPCM" bool "GPCM"
config BR2_MACHINE_FCM config BR2_MACHINE_FCM
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM" bool "FCM"
config BR2_MACHINE_SDRAM config BR2_MACHINE_SDRAM
depends on ARCH_MPC8349 || ARCH_MPC8360 depends on ARCH_MPC8360
bool "SDRAM" bool "SDRAM"
config BR2_MACHINE_UPMA config BR2_MACHINE_UPMA

6
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc3
View File

@ -22,7 +22,7 @@ config BR3_PORTSIZE_16BIT
config BR3_PORTSIZE_32BIT config BR3_PORTSIZE_32BIT
depends on !BR3_MACHINE_FCM depends on !BR3_MACHINE_FCM
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit" bool "32-bit"
endchoice endchoice
@ -58,11 +58,11 @@ config BR3_MACHINE_GPCM
bool "GPCM" bool "GPCM"
config BR3_MACHINE_FCM config BR3_MACHINE_FCM
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM" bool "FCM"
config BR3_MACHINE_SDRAM config BR3_MACHINE_SDRAM
depends on ARCH_MPC8349 || ARCH_MPC8360 depends on ARCH_MPC8360
bool "SDRAM" bool "SDRAM"
config BR3_MACHINE_UPMA config BR3_MACHINE_UPMA

6
arch/powerpc/cpu/mpc83xx/elbc/Kconfig.elbc4
View File

@ -22,7 +22,7 @@ config BR4_PORTSIZE_16BIT
config BR4_PORTSIZE_32BIT config BR4_PORTSIZE_32BIT
depends on !BR4_MACHINE_FCM depends on !BR4_MACHINE_FCM
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 depends on ARCH_MPC8360 || ARCH_MPC8379
bool "32-bit" bool "32-bit"
endchoice endchoice
@ -58,11 +58,11 @@ config BR4_MACHINE_GPCM
bool "GPCM" bool "GPCM"
config BR4_MACHINE_FCM config BR4_MACHINE_FCM
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "FCM" bool "FCM"
config BR4_MACHINE_SDRAM config BR4_MACHINE_SDRAM
depends on ARCH_MPC8349 || ARCH_MPC8360 depends on ARCH_MPC8360
bool "SDRAM" bool "SDRAM"
config BR4_MACHINE_UPMA config BR4_MACHINE_UPMA

4
arch/powerpc/cpu/mpc83xx/hid/Kconfig
View File

@ -434,7 +434,7 @@ config HID2_IWLCK_1
config HID2_IWLCK_2 config HID2_IWLCK_2
bool "Way 0 through 2 locked" bool "Way 0 through 2 locked"
if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 if ARCH_MPC8360 || ARCH_MPC8379
config HID2_IWLCK_3 config HID2_IWLCK_3
bool "Way 0 through 3 locked" bool "Way 0 through 3 locked"
@ -470,7 +470,7 @@ config HID2_DWLCK_1
config HID2_DWLCK_2 config HID2_DWLCK_2
bool "Way 0 through 2 locked" bool "Way 0 through 2 locked"
if ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC8379 if ARCH_MPC8360 || ARCH_MPC8379
config HID2_DWLCK_3 config HID2_DWLCK_3
bool "Way 0 through 3 locked" bool "Way 0 through 3 locked"

117
arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
View File

@ -7,7 +7,7 @@ config LBMC_CLOCK_MODE_1_1
bool "1 : 1" bool "1 : 1"
config LBMC_CLOCK_MODE_1_2 config LBMC_CLOCK_MODE_1_2
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X depends on ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 2" bool "1 : 2"
endchoice endchoice
@ -19,12 +19,12 @@ config DDR_MC_CLOCK_MODE_1_2
bool "1 : 2" bool "1 : 2"
config DDR_MC_CLOCK_MODE_1_1 config DDR_MC_CLOCK_MODE_1_1
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X depends on ARCH_MPC8360 || ARCH_MPC837X
bool "1 : 1" bool "1 : 1"
endchoice endchoice
if !ARCH_MPC8313 && !ARCH_MPC832X && !ARCH_MPC8349 if !ARCH_MPC8313 && !ARCH_MPC832X
choice choice
prompt "System PLL VCO division" prompt "System PLL VCO division"
@ -67,43 +67,43 @@ config SYSTEM_PLL_FACTOR_6_1
bool "6 : 1" bool "6 : 1"
config SYSTEM_PLL_FACTOR_7_1 config SYSTEM_PLL_FACTOR_7_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "7 : 1" bool "7 : 1"
config SYSTEM_PLL_FACTOR_8_1 config SYSTEM_PLL_FACTOR_8_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "8 : 1" bool "8 : 1"
config SYSTEM_PLL_FACTOR_9_1 config SYSTEM_PLL_FACTOR_9_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "9 : 1" bool "9 : 1"
config SYSTEM_PLL_FACTOR_10_1 config SYSTEM_PLL_FACTOR_10_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "10 : 1" bool "10 : 1"
config SYSTEM_PLL_FACTOR_11_1 config SYSTEM_PLL_FACTOR_11_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "11 : 1" bool "11 : 1"
config SYSTEM_PLL_FACTOR_12_1 config SYSTEM_PLL_FACTOR_12_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "12 : 1" bool "12 : 1"
config SYSTEM_PLL_FACTOR_13_1 config SYSTEM_PLL_FACTOR_13_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "13 : 1" bool "13 : 1"
config SYSTEM_PLL_FACTOR_14_1 config SYSTEM_PLL_FACTOR_14_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "14 : 1" bool "14 : 1"
config SYSTEM_PLL_FACTOR_15_1 config SYSTEM_PLL_FACTOR_15_1
depends on ARCH_MPC8349 || ARCH_MPV8360 || ARCH_MPC837X depends on ARCH_MPV8360 || ARCH_MPC837X
bool "15 : 1" bool "15 : 1"
config SYSTEM_PLL_FACTOR_16_1 config SYSTEM_PLL_FACTOR_16_1
depends on ARCH_MPC8349 || ARCH_MPV8360 depends on ARCH_MPV8360
bool "16 : 1" bool "16 : 1"
endchoice endchoice
@ -310,21 +310,6 @@ config PCI_HOST_MODE_ENABLE
endchoice endchoice
if ARCH_MPC8349
choice
prompt "PCI 64-bit mode"
config PCI_64BIT_MODE_DISABLE
bool "Disabled"
config PCI_64BIT_MODE_ENABLE
bool "Enabled"
endchoice
endif
choice choice
prompt "PCI internal arbiter 1 mode" prompt "PCI internal arbiter 1 mode"
@ -336,21 +321,6 @@ config PCI_INT_ARBITER1_ENABLE
endchoice endchoice
if ARCH_MPC8349
choice
prompt "PCI internal arbiter 2 mode"
config PCI_INT_ARBITER2_DISABLE
bool "Disabled"
config PCI_INT_ARBITER2_ENABLE
bool "Enabled"
endchoice
endif
if ARCH_MPC8360 if ARCH_MPC8360
choice choice
@ -425,10 +395,6 @@ config BOOT_ROM_INTERFACE_PCI1
depends on MPC83XX_PCI_SUPPORT depends on MPC83XX_PCI_SUPPORT
bool "PCI1" bool "PCI1"
config BOOT_ROM_INTERFACE_PCI2
depends on MPC83XX_PCI_SUPPORT && ARCH_MPC8349
bool "PCI2"
config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM config BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
depends on ARCH_MPC837X depends on ARCH_MPC837X
bool "PCI2" bool "PCI2"
@ -448,15 +414,15 @@ config BOOT_ROM_INTERFACE_GPCM_16BIT
bool "Local bus GPCM - 16-bit ROM" bool "Local bus GPCM - 16-bit ROM"
config BOOT_ROM_INTERFACE_GPCM_32BIT config BOOT_ROM_INTERFACE_GPCM_32BIT
depends on ARCH_MPC8349 || ARCH_MPC8360 || ARCH_MPC837X depends on ARCH_MPC8360 || ARCH_MPC837X
bool "Local bus GPCM - 32-bit ROM" bool "Local bus GPCM - 32-bit ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_SMALL
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "Local bus NAND Flash- 8-bit small page ROM" bool "Local bus NAND Flash- 8-bit small page ROM"
config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE config BOOT_ROM_INTERFACE_NAND_FLASH_8BIT_LARGE
depends on !ARCH_MPC832X && !ARCH_MPC8349 && !ARCH_MPC8360 depends on !ARCH_MPC832X && !ARCH_MPC8360
bool "Local bus NAND Flash- 8-bit large page ROM" bool "Local bus NAND Flash- 8-bit large page ROM"
endchoice endchoice
@ -467,11 +433,10 @@ choice
prompt "TSEC1 mode" prompt "TSEC1 mode"
config TSEC1_MODE_MII config TSEC1_MODE_MII
depends on !ARCH_MPC8349
bool "MII" bool "MII"
config TSEC1_MODE_RMII config TSEC1_MODE_RMII
depends on ARCH_MPC831X && !ARCH_MPC8349 depends on ARCH_MPC831X
bool "RMII" bool "RMII"
config TSEC1_MODE_RGMII config TSEC1_MODE_RGMII
@ -481,14 +446,6 @@ config TSEC1_MODE_RTBI
depends on ARCH_MPC831X || ARCH_MPC837X depends on ARCH_MPC831X || ARCH_MPC837X
bool "RTBI" bool "RTBI"
config TSEC1_MODE_GMII
depends on ARCH_MPC8349
bool "GMII"
config TSEC1_MODE_TBI
depends on ARCH_MPC8349
bool "TBI"
config TSEC1_MODE_SGMII config TSEC1_MODE_SGMII
depends on ARCH_MPC831X || ARCH_MPC837X depends on ARCH_MPC831X || ARCH_MPC837X
bool "SGMII" bool "SGMII"
@ -503,11 +460,10 @@ choice
prompt "TSEC2 mode" prompt "TSEC2 mode"
config TSEC2_MODE_MII config TSEC2_MODE_MII
depends on !ARCH_MPC8349
bool "MII" bool "MII"
config TSEC2_MODE_RMII config TSEC2_MODE_RMII
depends on ARCH_MPC831X && !ARCH_MPC8349 depends on ARCH_MPC831X
bool "RMII" bool "RMII"
config TSEC2_MODE_RGMII config TSEC2_MODE_RGMII
@ -517,14 +473,6 @@ config TSEC2_MODE_RTBI
depends on ARCH_MPC831X || ARCH_MPC837X depends on ARCH_MPC831X || ARCH_MPC837X
bool "RTBI" bool "RTBI"
config TSEC2_MODE_GMII
depends on ARCH_MPC8349
bool "GMII"
config TSEC2_MODE_TBI
depends on ARCH_MPC8349
bool "TBI"
config TSEC2_MODE_SGMII config TSEC2_MODE_SGMII
depends on ARCH_MPC831X || ARCH_MPC837X depends on ARCH_MPC831X || ARCH_MPC837X
bool "SGMII" bool "SGMII"
@ -559,7 +507,7 @@ endchoice
endif endif
if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8349 || ARCH_MPC8360 if ARCH_MPC831X || ARCH_MPC832X || ARCH_MPC8360
choice choice
prompt "LALE timing" prompt "LALE timing"
@ -603,7 +551,7 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV config SYSTEM_PLL_VCO_DIV
int int
default 0 if ARCH_MPC8349 || ARCH_MPC832X default 0 if ARCH_MPC832X
default 2 if ARCH_MPC8313 default 2 if ARCH_MPC8313
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
@ -675,7 +623,6 @@ config BOOT_ROM_INTERFACE
hex hex
default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM default 0x0 if BOOT_ROM_INTERFACE_DDR_SDRAM
default 0x4 if BOOT_ROM_INTERFACE_PCI1 default 0x4 if BOOT_ROM_INTERFACE_PCI1
default 0x8 if BOOT_ROM_INTERFACE_PCI2
default 0x8 if BOOT_ROM_INTERFACE_ESDHC default 0x8 if BOOT_ROM_INTERFACE_ESDHC
default 0xc if BOOT_ROM_INTERFACE_SPI default 0xc if BOOT_ROM_INTERFACE_SPI
default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM default 0xc if BOOT_ROM_INTERFACE_ON_CHIP_BOOT_ROM
@ -690,26 +637,18 @@ config TSEC1_MODE
default 0x0 if !MPC83XX_TSEC1_SUPPORT default 0x0 if !MPC83XX_TSEC1_SUPPORT
default 0x0 if TSEC1_MODE_MII default 0x0 if TSEC1_MODE_MII
default 0x1 if TSEC1_MODE_RMII default 0x1 if TSEC1_MODE_RMII
default 0x3 if TSEC1_MODE_RGMII && !ARCH_MPC8349 default 0x3 if TSEC1_MODE_RGMII
default 0x5 if TSEC1_MODE_RTBI && !ARCH_MPC8349 default 0x5 if TSEC1_MODE_RTBI
default 0x6 if TSEC1_MODE_SGMII default 0x6 if TSEC1_MODE_SGMII
default 0x0 if TSEC1_MODE_RGMII && ARCH_MPC8349
default 0x1 if TSEC1_MODE_RTBI && ARCH_MPC8349
default 0x2 if TSEC1_MODE_GMII
default 0x3 if TSEC1_MODE_TBI
config TSEC2_MODE config TSEC2_MODE
hex hex
default 0x0 if !MPC83XX_TSEC2_SUPPORT default 0x0 if !MPC83XX_TSEC2_SUPPORT
default 0x0 if TSEC2_MODE_MII default 0x0 if TSEC2_MODE_MII
default 0x1 if TSEC2_MODE_RMII default 0x1 if TSEC2_MODE_RMII
default 0x3 if TSEC2_MODE_RGMII && !ARCH_MPC8349 default 0x3 if TSEC2_MODE_RGMII
default 0x5 if TSEC2_MODE_RTBI && !ARCH_MPC8349 default 0x5 if TSEC2_MODE_RTBI
default 0x6 if TSEC2_MODE_SGMII default 0x6 if TSEC2_MODE_SGMII
default 0x0 if TSEC2_MODE_RGMII && ARCH_MPC8349
default 0x1 if TSEC2_MODE_RTBI && ARCH_MPC8349
default 0x2 if TSEC2_MODE_GMII
default 0x3 if TSEC2_MODE_TBI
config SECONDARY_DDR_IO config SECONDARY_DDR_IO
int int
@ -792,9 +731,7 @@ config PCI_HOST_MODE
config PCI_64BIT_MODE config PCI_64BIT_MODE
int int
default 0 if !ARCH_MPC8349 default 0
default 0 if PCI_64BIT_MODE_DISABLE
default 1 if PCI_64BIT_MODE_ENABLE
config PCI_INT_ARBITER1 config PCI_INT_ARBITER1
int int
@ -804,9 +741,7 @@ config PCI_INT_ARBITER1
config PCI_INT_ARBITER2 config PCI_INT_ARBITER2
int int
default 0 if !ARCH_MPC8349 default 0
default 0 if PCI_INT_ARBITER2_DISABLE
default 1 if PCI_INT_ARBITER2_ENABLE
config PCI_CLOCK_OUTPUT_DRIVE config PCI_CLOCK_OUTPUT_DRIVE
int int

12
arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h
View File

@ -1,11 +1,3 @@
#ifdef CONFIG_ARCH_MPC8349
#define TSEC1_MODE_SHIFT 17
#define TSEC2_MODE_SHIFT 19
#else
#define TSEC1_MODE_SHIFT 18
#define TSEC2_MODE_SHIFT 21
#endif
#define CONFIG_SYS_HRCW_LOW (\ #define CONFIG_SYS_HRCW_LOW (\
(CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\ (CONFIG_LBMC_CLOCK_MODE << (31 - 0)) |\
(CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\ (CONFIG_DDR_MC_CLOCK_MODE << (31 - 1)) |\
@ -28,8 +20,8 @@
(CONFIG_BOOT_SEQUENCER << (31 - 7)) |\ (CONFIG_BOOT_SEQUENCER << (31 - 7)) |\
(CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\ (CONFIG_SOFTWARE_WATCHDOG << (31 - 8)) |\
(CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\ (CONFIG_BOOT_ROM_INTERFACE << (31 - 13)) |\
(CONFIG_TSEC1_MODE << (31 - TSEC1_MODE_SHIFT)) |\ (CONFIG_TSEC1_MODE << (31 - 18)) |\
(CONFIG_TSEC2_MODE << (31 - TSEC2_MODE_SHIFT)) |\ (CONFIG_TSEC2_MODE << (31 - 21)) |\
(CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\ (CONFIG_SECONDARY_DDR_IO << (31 - 27)) |\
(CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\ (CONFIG_TRUE_LITTLE_ENDIAN << (31 - 28)) |\
(CONFIG_LALE_TIMING << (31 - 29)) |\ (CONFIG_LALE_TIMING << (31 - 29)) |\

44
arch/powerpc/cpu/mpc83xx/initreg/Kconfig.spcr
View File

@ -38,50 +38,6 @@ endchoice
endif endif
if ARCH_MPC8349
choice
prompt "TSEC1 emergency priority"
config SPCR_TSEC1EP_UNSET
bool "Don't set value"
config SPCR_TSEC1EP_0
bool "Level 0 (lowest priority)"
config SPCR_TSEC1EP_1
bool "Level 1"
config SPCR_TSEC1EP_2
bool "Level 2"
config SPCR_TSEC1EP_3
bool "Level 3 (highest priority)"
endchoice
choice
prompt "TSEC2 emergency priority"
config SPCR_TSEC2EP_UNSET
bool "Don't set value"
config SPCR_TSEC2EP_0
bool "Level 0 (lowest priority)"
config SPCR_TSEC2EP_1
bool "Level 1"
config SPCR_TSEC2EP_2
bool "Level 2"
config SPCR_TSEC2EP_3
bool "Level 3 (highest priority)"
endchoice
endif
config SPCR_OPT config SPCR_OPT
hex hex
default 0x0 if SPCR_OPT_UNSET default 0x0 if SPCR_OPT_UNSET

15
board/CarMediaLab/flea3/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_FLEA3
config SYS_BOARD
default "flea3"
config SYS_VENDOR
default "CarMediaLab"
config SYS_SOC
default "mx35"
config SYS_CONFIG_NAME
default "flea3"
endif

6
board/CarMediaLab/flea3/MAINTAINERS
View File

@ -1,6 +0,0 @@
FLEA3 BOARD
M: Stefano Babic <sbabic@denx.de>
S: Maintained
F: board/CarMediaLab/flea3/
F: include/configs/flea3.h
F: configs/flea3_defconfig

8
board/CarMediaLab/flea3/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
#
# (C) Copyright 2008-2009 Freescale Semiconductor, Inc.
obj-y := flea3.o
obj-y += lowlevel_init.o

227
board/CarMediaLab/flea3/flea3.c
View File

@ -1,227 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
*/
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <env.h>
#include <linux/delay.h>
#include <linux/errno.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/crm_regs.h>
#include <asm/arch/iomux-mx35.h>
#include <i2c.h>
#include <linux/types.h>
#include <asm/gpio.h>
#include <asm/arch/sys_proto.h>
#include <netdev.h>
#include <fdt_support.h>
#include <mtd_node.h>
#include <jffs2/load_kernel.h>
#ifndef CONFIG_BOARD_EARLY_INIT_F
#error "CONFIG_BOARD_EARLY_INIT_F must be set for this board"
#endif
#define CCM_CCMR_CONFIG 0x003F4208
#define ESDCTL_DDR2_CONFIG 0x007FFC3F
static inline void dram_wait(unsigned int count)
{
volatile unsigned int wait = count;
while (wait--)
;
}
DECLARE_GLOBAL_DATA_PTR;
int dram_init(void)
{
gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1,
PHYS_SDRAM_1_SIZE);
return 0;
}
static void board_setup_sdram(void)
{
struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR;
/* Initialize with default values both CSD0/1 */
writel(0x2000, &esdc->esdctl0);
writel(0x2000, &esdc->esdctl1);
mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG,
13, 10, 2, 0x8080);
}
static void setup_iomux_uart3(void)
{
static const iomux_v3_cfg_t uart3_pads[] = {
MX35_PAD_RTS2__UART3_RXD_MUX,
MX35_PAD_CTS2__UART3_TXD_MUX,
};
imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads));
}
#define I2C_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_ODE)
static void setup_iomux_i2c(void)
{
static const iomux_v3_cfg_t i2c_pads[] = {
NEW_PAD_CTRL(MX35_PAD_I2C1_CLK__I2C1_SCL, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX35_PAD_I2C1_DAT__I2C1_SDA, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX35_PAD_TX3_RX2__I2C3_SCL, I2C_PAD_CTRL),
NEW_PAD_CTRL(MX35_PAD_TX2_RX3__I2C3_SDA, I2C_PAD_CTRL),
};
imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads));
}
static void setup_iomux_spi(void)
{
static const iomux_v3_cfg_t spi_pads[] = {
MX35_PAD_CSPI1_MOSI__CSPI1_MOSI,
MX35_PAD_CSPI1_MISO__CSPI1_MISO,
MX35_PAD_CSPI1_SS0__CSPI1_SS0,
MX35_PAD_CSPI1_SS1__CSPI1_SS1,
MX35_PAD_CSPI1_SCLK__CSPI1_SCLK,
};
imx_iomux_v3_setup_multiple_pads(spi_pads, ARRAY_SIZE(spi_pads));
}
static void setup_iomux_fec(void)
{
static const iomux_v3_cfg_t fec_pads[] = {
MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
MX35_PAD_FEC_RX_DV__FEC_RX_DV,
MX35_PAD_FEC_COL__FEC_COL,
MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
MX35_PAD_FEC_TX_EN__FEC_TX_EN,
MX35_PAD_FEC_MDC__FEC_MDC,
MX35_PAD_FEC_MDIO__FEC_MDIO,
MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
MX35_PAD_FEC_CRS__FEC_CRS,
MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
/* GPIO used to power off ethernet */
MX35_PAD_STXFS4__GPIO2_31,
};
/* setup pins for FEC */
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
}
int board_early_init_f(void)
{
struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;
/* setup GPIO3_1 to set HighVCore signal */
imx_iomux_v3_setup_pad(MX35_PAD_ATA_DA1__GPIO3_1);
gpio_direction_output(65, 1);
/* initialize PLL and clock configuration */
writel(CCM_CCMR_CONFIG, &ccm->ccmr);
writel(CCM_MPLL_532_HZ, &ccm->mpctl);
writel(CCM_PPLL_300_HZ, &ccm->ppctl);
/* Set the core to run at 532 Mhz */
writel(0x00001000, &ccm->pdr0);
/* Set-up RAM */
board_setup_sdram();
/* enable clocks */
writel(readl(&ccm->cgr0) |
MXC_CCM_CGR0_EMI_MASK |
MXC_CCM_CGR0_EDIO_MASK |
MXC_CCM_CGR0_EPIT1_MASK,
&ccm->cgr0);
writel(readl(&ccm->cgr1) |
MXC_CCM_CGR1_FEC_MASK |
MXC_CCM_CGR1_GPIO1_MASK |
MXC_CCM_CGR1_GPIO2_MASK |
MXC_CCM_CGR1_GPIO3_MASK |
MXC_CCM_CGR1_I2C1_MASK |
MXC_CCM_CGR1_I2C2_MASK |
MXC_CCM_CGR1_I2C3_MASK,
&ccm->cgr1);
/* Set-up NAND */
__raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr);
/* Set pinmux for the required peripherals */
setup_iomux_uart3();
setup_iomux_i2c();
setup_iomux_fec();
setup_iomux_spi();
return 0;
}
int board_init(void)
{
/* address of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* Enable power for ethernet */
gpio_direction_output(63, 0);
udelay(2000);
return 0;
}
#ifdef CONFIG_REVISION_TAG
u32 get_board_rev(void)
{
int rev = 0;
return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
}
#endif
/*
* called prior to booting kernel or by 'fdt boardsetup' command
*
*/
int ft_board_setup(void *blob, struct bd_info *bd)
{
static const struct node_info nodes[] = {
{ "physmap-flash.0", MTD_DEV_TYPE_NOR, }, /* NOR flash */
{ "mxc_nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
};
if (env_get("fdt_noauto")) {
puts(" Skiping ft_board_setup (fdt_noauto defined)\n");
return 0;
}
fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
return 0;
}

24
board/CarMediaLab/flea3/lowlevel_init.S
View File

@ -1,24 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
*
* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
*
* Copyright (C) 2011, Stefano Babic <sbabic@denx.de>
*/
#include <config.h>
#include <asm/arch/lowlevel_macro.S>
.globl lowlevel_init
lowlevel_init:
core_init
init_aips
init_max
init_m3if
mov pc, lr

15
board/Marvell/aspenite/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_ASPENITE
config SYS_BOARD
default "aspenite"
config SYS_VENDOR
default "Marvell"
config SYS_SOC
default "armada100"
config SYS_CONFIG_NAME
default "aspenite"
endif

6
board/Marvell/aspenite/MAINTAINERS
View File

@ -1,6 +0,0 @@
ASPENITE BOARD
M: Prafulla Wadaskar <prafulla@marvell.com>
S: Maintained
F: board/Marvell/aspenite/
F: include/configs/aspenite.h
F: configs/aspenite_defconfig

8
board/Marvell/aspenite/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2010
# Marvell Semiconductor <www.marvell.com>
# Written-by: Prafulla Wadaskar <prafulla@marvell.com>
# Contributor: Mahavir Jain <mjain@marvell.com>
obj-y := aspenite.o

45
board/Marvell/aspenite/aspenite.c
View File

@ -1,45 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
* Contributor: Mahavir Jain <mjain@marvell.com>
*/
#include <common.h>
#include <init.h>
#include <mvmfp.h>
#include <asm/global_data.h>
#include <asm/mach-types.h>
#include <asm/arch/cpu.h>
#include <asm/arch/mfp.h>
#include <asm/arch/armada100.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
u32 mfp_cfg[] = {
/* I2C */
MFP105_CI2C_SDA,
MFP106_CI2C_SCL,
/* Enable Console on UART1 */
MFP107_UART1_RXD,
MFP108_UART1_TXD,
MFP_EOC /*End of configureation*/
};
/* configure MFP's */
mfp_config(mfp_cfg);
return 0;
}
int board_init(void)
{
/* arch number of Board */
gd->bd->bi_arch_number = MACH_TYPE_ASPENITE;
/* adress of boot parameters */
gd->bd->bi_boot_params = armd1_sdram_base(0) + 0x100;
return 0;
}

25
board/freescale/mpc8349emds/Kconfig
View File

@ -1,25 +0,0 @@
if TARGET_MPC8349EMDS
config SYS_BOARD
default "mpc8349emds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8349EMDS"
endif
if TARGET_MPC8349EMDS_SDRAM
config SYS_BOARD
default "mpc8349emds"
config SYS_VENDOR
default "freescale"
config SYS_CONFIG_NAME
default "MPC8349EMDS_SDRAM"
endif

9
board/freescale/mpc8349emds/MAINTAINERS
View File

@ -1,9 +0,0 @@
MPC8349EMDS BOARD
#M: Kim Phillips <kim.phillips@freescale.com>
S: Orphan (since 2018-05)
F: board/freescale/mpc8349emds/
F: include/configs/MPC8349EMDS.h
F: configs/MPC8349EMDS_defconfig
F: configs/MPC8349EMDS_SDRAM_defconfig
F: configs/MPC8349EMDS_PCI64_defconfig
F: configs/MPC8349EMDS_SLAVE_defconfig

8
board/freescale/mpc8349emds/Makefile
View File

@ -1,8 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
obj-y += mpc8349emds.o
obj-$(CONFIG_PCI) += pci.o
obj-$(CONFIG_SYS_FSL_DDR2) += ddr.o

100
board/freescale/mpc8349emds/ddr.c
View File

@ -1,100 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2011 Freescale Semiconductor, Inc.
*/
#include <common.h>
#include <fsl_ddr_sdram.h>
#include <fsl_ddr_dimm_params.h>
struct board_specific_parameters {
u32 n_ranks;
u32 datarate_mhz_high;
u32 clk_adjust;
u32 cpo;
u32 write_data_delay;
u32 force_2t;
};
/*
* This table contains all valid speeds we want to override with board
* specific parameters. datarate_mhz_high values need to be in ascending order
* for each n_ranks group.
*/
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
* num| hi| clk| cpo|wrdata|2T
* ranks| mhz|adjst| | delay|
*/
{2, 300, 4, 4, 2, 0},
{2, 365, 4, 6, 2, 0},
{2, 450, 4, 7, 2, 0},
{2, 850, 4, 31, 2, 0},
{1, 300, 4, 4, 2, 0},
{1, 365, 4, 6, 2, 0},
{1, 450, 4, 7, 2, 0},
{1, 850, 4, 31, 2, 0},
{}
};
void fsl_ddr_board_options(memctl_options_t *popts,
dimm_params_t *pdimm,
unsigned int ctrl_num)
{
const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
unsigned int i;
ulong ddr_freq;
if (ctrl_num != 0) /* we have only one controller */
return;
for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
if (pdimm[i].n_ranks)
break;
}
if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
return;
pbsp = udimm0;
/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
* freqency and n_banks specified in board_specific_parameters table.
*/
ddr_freq = get_ddr_freq(0) / 1000000;
while (pbsp->datarate_mhz_high) {
if (pbsp->n_ranks == pdimm[i].n_ranks) {
if (ddr_freq <= pbsp->datarate_mhz_high) {
popts->clk_adjust = pbsp->clk_adjust;
popts->cpo_override = pbsp->cpo;
popts->write_data_delay =
pbsp->write_data_delay;
popts->twot_en = pbsp->force_2t;
goto found;
}
pbsp_highest = pbsp;
}
pbsp++;
}
if (pbsp_highest) {
printf("Error: board specific timing not found "
"for data rate %lu MT/s!\n"
"Trying to use the highest speed (%u) parameters\n",
ddr_freq, pbsp_highest->datarate_mhz_high);
popts->clk_adjust = pbsp_highest->clk_adjust;
popts->cpo_override = pbsp_highest->cpo;
popts->write_data_delay = pbsp_highest->write_data_delay;
popts->twot_en = pbsp_highest->force_2t;
} else {
panic("DIMM is not supported by this board");
}
found:
/*
* Factors to consider for half-strength driver enable:
* - number of DIMMs installed
*/
popts->half_strength_driver_enable = 0;
popts->dqs_config = 0; /* only true DQS signal is used on board */
}

277
board/freescale/mpc8349emds/mpc8349emds.c
View File

@ -1,277 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
#include <common.h>
#include <fdt_support.h>
#include <init.h>
#include <ioports.h>
#include <mpc83xx.h>
#include <asm/bitops.h>
#include <asm/global_data.h>
#include <asm/mpc8349_pci.h>
#include <i2c.h>
#include <spi.h>
#include <miiphy.h>
#ifdef CONFIG_SYS_FSL_DDR2
#include <fsl_ddr_sdram.h>
#else
#include <spd_sdram.h>
#endif
#include <linux/delay.h>
#if defined(CONFIG_OF_LIBFDT)
#include <linux/libfdt.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
int fixed_sdram(void);
void sdram_init(void);
#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83xx)
void ddr_enable_ecc(unsigned int dram_size);
#endif
int board_early_init_f (void)
{
volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
/* Enable flash write */
bcsr[1] &= ~0x01;
#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
/* Use USB PHY on SYS board */
bcsr[5] |= 0x02;
#endif
return 0;
}
int dram_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
phys_size_t msize = 0;
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -ENXIO;
/* DDR SDRAM - Main SODIMM */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
#if defined(CONFIG_SPD_EEPROM)
#ifndef CONFIG_SYS_FSL_DDR2
msize = spd_sdram() * 1024 * 1024;
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
ddr_enable_ecc(msize);
#endif
#else
msize = fsl_ddr_sdram();
#endif
#else
msize = fixed_sdram() * 1024 * 1024;
#endif
/*
* Initialize SDRAM if it is on local bus.
*/
sdram_init();
/* set total bus SDRAM size(bytes) -- DDR */
gd->ram_size = msize;
return 0;
}
#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
* fixed sdram init -- doesn't use serial presence detect.
************************************************************************/
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_DDR_SIZE;
u32 ddr_size = msize << 20; /* DDR size in bytes */
u32 ddr_size_log2 = __ilog2(ddr_size);
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE != 256)
#warning Currenly any ddr size other than 256 is not supported
#endif
#if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
#warning Chip select bounds is only configurable in 16MB increments
#endif
im->ddr.csbnds[2].csbnds =
((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
(((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
CSBNDS_EA_SHIFT) & CSBNDS_EA);
im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
/* currently we use only one CS, so disable the other banks */
im->ddr.cs_config[0] = 0;
im->ddr.cs_config[1] = 0;
im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.sdram_cfg =
SDRAM_CFG_SREN
| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
udelay(200);
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
#endif/*!CONFIG_SYS_SPD_EEPROM*/
int checkboard (void)
{
/*
* Warning: do not read the BCSR registers here
*
* There is a timing bug in the 8349E and 8349EA BCSR code
* version 1.2 (read from BCSR 11) that will cause the CFI
* flash initialization code to overwrite BCSR 0, disabling
* the serial ports and gigabit ethernet
*/
puts("Board: Freescale MPC8349EMDS\n");
return 0;
}
/*
* if MPC8349EMDS is soldered with SDRAM
*/
#if defined(CONFIG_SYS_BR2_PRELIM) \
&& defined(CONFIG_SYS_OR2_PRELIM) \
&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
/*
* Initialize SDRAM memory on the Local Bus.
*/
void sdram_init(void)
{
volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
volatile fsl_lbc_t *lbc = &immap->im_lbc;
uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
const u32 lsdmr_common = LSDMR_RFEN | LSDMR_BSMA1516 | LSDMR_RFCR8 |
LSDMR_PRETOACT6 | LSDMR_ACTTORW3 | LSDMR_BL8 |
LSDMR_WRC3 | LSDMR_CL3;
/*
* Setup SDRAM Base and Option Registers, already done in cpu_init.c
*/
/* setup mtrpt, lsrt and lbcr for LB bus */
lbc->lbcr = 0x00000000;
/* LB refresh timer prescal, 266MHz/32 */
lbc->mrtpr = 0x20000000;
/* LB sdram refresh timer, about 6us */
lbc->lsrt = 0x32000000;
asm("sync");
/*
* Configure the SDRAM controller Machine Mode Register.
*/
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
/* 0x68636733; precharge all the banks */
lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
/* 0x48636733; auto refresh */
lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync");
/*1 times*/
*sdram_addr = 0xff;
udelay(100);
/*2 times*/
*sdram_addr = 0xff;
udelay(100);
/*3 times*/
*sdram_addr = 0xff;
udelay(100);
/*4 times*/
*sdram_addr = 0xff;
udelay(100);
/*5 times*/
*sdram_addr = 0xff;
udelay(100);
/*6 times*/
*sdram_addr = 0xff;
udelay(100);
/*7 times*/
*sdram_addr = 0xff;
udelay(100);
/*8 times*/
*sdram_addr = 0xff;
udelay(100);
/* 0x58636733; mode register write operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
/* 0x40636733; normal operation */
lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync");
*sdram_addr = 0xff;
udelay(100);
}
#else
void sdram_init(void)
{
}
#endif
/*
* The following are used to control the SPI chip selects for the SPI command.
*/
#ifdef CONFIG_MPC8XXX_SPI
#define SPI_CS_MASK 0x80000000
int spi_cs_is_valid(unsigned int bus, unsigned int cs)
{
return bus == 0 && cs == 0;
}
void spi_cs_activate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat &= ~SPI_CS_MASK;
}
void spi_cs_deactivate(struct spi_slave *slave)
{
volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
iopd->dat |= SPI_CS_MASK;
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
return 0;
}
#endif

118
board/freescale/mpc8349emds/pci.c
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@ -1,118 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
*/
#include <init.h>
#include <asm/mmu.h>
#include <asm/io.h>
#include <common.h>
#include <mpc83xx.h>
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
#include <linux/delay.h>
static struct pci_region pci1_regions[] = {
{
bus_start: CONFIG_SYS_PCI1_MEM_BASE,
phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
size: CONFIG_SYS_PCI1_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI1_IO_BASE,
phys_start: CONFIG_SYS_PCI1_IO_PHYS,
size: CONFIG_SYS_PCI1_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
size: CONFIG_SYS_PCI1_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#ifdef CONFIG_MPC83XX_PCI2
static struct pci_region pci2_regions[] = {
{
bus_start: CONFIG_SYS_PCI2_MEM_BASE,
phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
size: CONFIG_SYS_PCI2_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI2_IO_BASE,
phys_start: CONFIG_SYS_PCI2_IO_PHYS,
size: CONFIG_SYS_PCI2_IO_SIZE,
flags: PCI_REGION_IO
},
{
bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
size: CONFIG_SYS_PCI2_MMIO_SIZE,
flags: PCI_REGION_MEM
},
};
#endif
#ifndef CONFIG_PCISLAVE
void pib_init(void)
{
u8 val8, orig_i2c_bus;
/*
* Assign PIB PMC slot to desired PCI bus
*/
/* Switch temporarily to I2C bus #2 */
orig_i2c_bus = i2c_get_bus_num();
i2c_set_bus_num(1);
val8 = 0;
i2c_write(0x23, 0x6, 1, &val8, 1);
i2c_write(0x23, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x23, 0x2, 1, &val8, 1);
i2c_write(0x23, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x26, 0x6, 1, &val8, 1);
val8 = 0x34;
i2c_write(0x26, 0x7, 1, &val8, 1);
#if defined(CONFIG_PCI_64BIT)
val8 = 0xf4; /* PMC2:PCI1/64-bit */
#elif defined(CONFIG_PCI_ALL_PCI1)
val8 = 0xf3; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI1 */
#elif defined(CONFIG_PCI_ONE_PCI1)
val8 = 0xf9; /* PMC1:PCI1 PMC2:PCI2 PMC3:PCI2 */
#else
val8 = 0xf5; /* PMC1:PCI1 PMC2:PCI1 PMC3:PCI2 */
#endif
i2c_write(0x26, 0x2, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x26, 0x3, 1, &val8, 1);
val8 = 0;
i2c_write(0x27, 0x6, 1, &val8, 1);
i2c_write(0x27, 0x7, 1, &val8, 1);
val8 = 0xff;
i2c_write(0x27, 0x2, 1, &val8, 1);
val8 = 0xef;
i2c_write(0x27, 0x3, 1, &val8, 1);
asm("eieio");
#if defined(CONFIG_PCI_64BIT)
printf("PCI1: 64-bit on PMC2\n");
#elif defined(CONFIG_PCI_ALL_PCI1)
printf("PCI1: 32-bit on PMC1, PMC2, PMC3\n");
#elif defined(CONFIG_PCI_ONE_PCI1)
printf("PCI1: 32-bit on PMC1\n");
printf("PCI2: 32-bit on PMC2, PMC3\n");
#else
printf("PCI1: 32-bit on PMC1, PMC2\n");
printf("PCI2: 32-bit on PMC3\n");
#endif
/* Reset to original I2C bus */
i2c_set_bus_num(orig_i2c_bus);
}
#endif /* CONFIG_PCISLAVE */

15
board/ppcag/bg0900/Kconfig
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@ -1,15 +0,0 @@
if TARGET_BG0900
config SYS_BOARD
default "bg0900"
config SYS_VENDOR
default "ppcag"
config SYS_SOC
default "mxs"
config SYS_CONFIG_NAME
default "bg0900"
endif

6
board/ppcag/bg0900/MAINTAINERS
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@ -1,6 +0,0 @@
BG0900 BOARD
M: Marek Vasut <marex@denx.de>
S: Maintained
F: board/ppcag/bg0900/
F: include/configs/bg0900.h
F: configs/bg0900_defconfig

10
board/ppcag/bg0900/Makefile
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@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_SPL_BUILD
obj-y := bg0900.o
else
obj-y := spl_boot.o
endif

89
board/ppcag/bg0900/bg0900.c
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@ -1,89 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PPC-AG BG0900 board
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
#include <linux/mii.h>
#include <miiphy.h>
#include <netdev.h>
#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Functions
*/
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* IO1 clock at 480MHz */
mxs_set_ioclk(MXC_IOCLK1, 480000);
/* SSP2 clock at 160MHz */
mxs_set_sspclk(MXC_SSPCLK2, 160000, 0);
return 0;
}
int dram_init(void)
{
return mxs_dram_init();
}
int board_init(void)
{
/* Adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
return 0;
}
#ifdef CONFIG_CMD_NET
int board_eth_init(struct bd_info *bis)
{
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
struct eth_device *dev;
int ret;
ret = cpu_eth_init(bis);
/* BG0900 uses ENET_CLK PAD to drive FEC clock */
writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN,
&clkctrl_regs->hw_clkctrl_enet);
/* Reset FEC PHYs */
gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0);
udelay(200);
gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1);
ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE);
if (ret) {
puts("FEC MXS: Unable to init FEC0\n");
return ret;
}
dev = eth_get_dev_by_name("FEC0");
if (!dev) {
puts("FEC MXS: Unable to get FEC0 device entry\n");
return -EINVAL;
}
return ret;
}
#endif

152
board/ppcag/bg0900/spl_boot.c
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@ -1,152 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* PPC-AG BG0900 Boot setup
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx28.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP)
const iomux_cfg_t iomux_setup[] = {
/* DUART */
MX28_PAD_PWM0__DUART_RX,
MX28_PAD_PWM1__DUART_TX,
/* GPMI NAND */
MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RDN__GPMI_RDN |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,
/* FEC0 */
MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET,
MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET,
MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET,
MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET,
/* FEC0 Reset */
MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
(MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
/* EMI */
MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI,
MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI,
MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI,
MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
/* SPI2 (for SPI flash) */
MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2,
MX28_PAD_SSP2_SS0__SSP2_D3 |
(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
};
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
/*
* DDR Controller Registers
* Manufacturer: Winbond
* Device Part Number: W972GG6JB-25I
* Clock Freq.: 200MHz
* Density: 2Gb
* Chip Selects: 1
* Number of Banks: 8
* Row address: 14
* Column address: 10
*/
dram_vals[0x74 / 4] = 0x0102010A;
dram_vals[0x98 / 4] = 0x04005003;
dram_vals[0x9c / 4] = 0x090000c8;
dram_vals[0xa8 / 4] = 0x0036b009;
dram_vals[0xac / 4] = 0x03270612;
dram_vals[0xb0 / 4] = 0x02020202;
dram_vals[0xb4 / 4] = 0x00c80029;
dram_vals[0xc0 / 4] = 0x00011900;
dram_vals[0x12c / 4] = 0x07400300;
dram_vals[0x130 / 4] = 0x07400300;
dram_vals[0x2c4 / 4] = 0x02030303;
}
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}

15
board/syteco/zmx25/Kconfig
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@ -1,15 +0,0 @@
if TARGET_ZMX25
config SYS_BOARD
default "zmx25"
config SYS_VENDOR
default "syteco"
config SYS_SOC
default "mx25"
config SYS_CONFIG_NAME
default "zmx25"
endif

6
board/syteco/zmx25/MAINTAINERS
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@ -1,6 +0,0 @@
ZMX25 BOARD
M: Matthias Weisser <weisserm@arcor.de>
S: Maintained
F: board/syteco/zmx25/
F: include/configs/zmx25.h
F: configs/zmx25_defconfig

7
board/syteco/zmx25/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (c) 2010 Graf-Syteco, Matthias Weisser
# <weisserm@arcor.de>
obj-y += zmx25.o
obj-y += lowlevel_init.o

96
board/syteco/zmx25/lowlevel_init.S
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@ -1,96 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* (C) Copyright 2011
* Matthias Weisser <weisserm@arcor.de>
*
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on U-Boot and RedBoot sources for several different i.mx
* platforms.
*/
#include <asm/macro.h>
#include <asm/arch/macro.h>
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
/*
* clocks
*/
.macro init_clocks
/* disable clock output */
write32 IMX_CCM_BASE + CCM_MCR, 0x00000000
write32 IMX_CCM_BASE + CCM_CCTL, 0x50030000
/*
* enable all implemented clocks in all three
* clock control registers
*/
write32 IMX_CCM_BASE + CCM_CGCR0, 0x1fffffff
write32 IMX_CCM_BASE + CCM_CGCR1, 0xffffffff
write32 IMX_CCM_BASE + CCM_CGCR2, 0xfffff
/* Devide NAND clock by 32 */
write32 IMX_CCM_BASE + CCM_PCDR2, 0x0101011F
.endm
/*
* sdram controller init
*/
.macro init_lpddr
ldr r0, =IMX_ESDRAMC_BASE
ldr r2, =IMX_SDRAM_BANK0_BASE
/*
* reset SDRAM controller
* then wait for initialization to complete
*/
ldr r1, =(1 << 1) | (1 << 2)
str r1, [r0, #ESDRAMC_ESDMISC]
1: ldr r3, [r0, #ESDRAMC_ESDMISC]
tst r3, #(1 << 31)
beq 1b
ldr r1, =(1 << 2)
str r1, [r0, #ESDRAMC_ESDMISC]
ldr r1, =0x002a7420
str r1, [r0, #ESDRAMC_ESDCFG0]
/* control | precharge */
ldr r1, =0x92216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* dram command encoded in address */
str r1, [r2, #0x400]
/* auto refresh */
ldr r1, =0xa2216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* read dram twice to auto refresh */
ldr r3, [r2]
ldr r3, [r2]
/* control | load mode */
ldr r1, =0xb2216008
str r1, [r0, #ESDRAMC_ESDCTL0]
/* mode register of lpddram */
strb r1, [r2, #0x33]
/* extended mode register of lpddrram */
ldr r2, =0x81000000
strb r1, [r2]
/* control | normal */
ldr r1, =0x82216008
str r1, [r0, #ESDRAMC_ESDCTL0]
.endm
.globl lowlevel_init
lowlevel_init:
init_aips
init_max
init_clocks
init_lpddr
mov pc, lr

178
board/syteco/zmx25/zmx25.c
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@ -1,178 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (c) 2011 Graf-Syteco, Matthias Weisser
* <weisserm@arcor.de>
*
* Based on tx25.c:
* (C) Copyright 2009 DENX Software Engineering
* Author: John Rigby <jrigby@gmail.com>
*
* Based on imx27lite.c:
* Copyright (C) 2008,2009 Eric Jarrige <jorasse@users.sourceforge.net>
* Copyright (C) 2009 Ilya Yanok <yanok@emcraft.com>
* And:
* RedBoot tx25_misc.c Copyright (C) 2009 Red Hat
*/
#include <common.h>
#include <cpu_func.h>
#include <env.h>
#include <init.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/iomux-mx25.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
int board_init()
{
static const iomux_v3_cfg_t sdhc1_pads[] = {
NEW_PAD_CTRL(MX25_PAD_SD1_CMD__SD1_CMD, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_CLK__SD1_CLK, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA0__SD1_DATA0, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA1__SD1_DATA1, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA2__SD1_DATA2, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_SD1_DATA3__SD1_DATA3, NO_PAD_CTRL),
};
static const iomux_v3_cfg_t dig_out_pads[] = {
MX25_PAD_CSI_D8__GPIO_1_7, /* Ouput 1 Ctrl */
MX25_PAD_CSI_D7__GPIO_1_6, /* Ouput 2 Ctrl */
NEW_PAD_CTRL(MX25_PAD_CSI_D6__GPIO_1_31, 0), /* Ouput 1 Stat */
NEW_PAD_CTRL(MX25_PAD_CSI_D5__GPIO_1_30, 0), /* Ouput 2 Stat */
};
static const iomux_v3_cfg_t led_pads[] = {
MX25_PAD_CSI_D9__GPIO_4_21,
MX25_PAD_CSI_D4__GPIO_1_29,
};
static const iomux_v3_cfg_t can_pads[] = {
NEW_PAD_CTRL(MX25_PAD_GPIO_A__CAN1_TX, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_GPIO_B__CAN1_RX, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_GPIO_C__CAN2_TX, NO_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_GPIO_D__CAN2_RX, NO_PAD_CTRL),
};
static const iomux_v3_cfg_t i2c3_pads[] = {
MX25_PAD_CSPI1_SS1__I2C3_DAT,
MX25_PAD_GPIO_E__I2C3_CLK,
};
icache_enable();
/* Setup of core voltage selection pin to run at 1.4V */
imx_iomux_v3_setup_pad(MX25_PAD_EXT_ARMCLK__GPIO_3_15); /* VCORE */
gpio_direction_output(IMX_GPIO_NR(3, 15), 1);
/* Setup of SD card pins*/
imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads));
/* Setup of digital output for USB power and OC */
imx_iomux_v3_setup_pad(MX25_PAD_CSI_D3__GPIO_1_28); /* USB Power */
gpio_direction_output(IMX_GPIO_NR(1, 28), 1);
imx_iomux_v3_setup_pad(MX25_PAD_CSI_D2__GPIO_1_27); /* USB OC */
gpio_direction_input(IMX_GPIO_NR(1, 18));
/* Setup of digital output control pins */
imx_iomux_v3_setup_multiple_pads(dig_out_pads,
ARRAY_SIZE(dig_out_pads));
/* Switch both output drivers off */
gpio_direction_output(IMX_GPIO_NR(1, 7), 0);
gpio_direction_output(IMX_GPIO_NR(1, 6), 0);
/* Setup of key input pin */
imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX25_PAD_KPP_ROW0__GPIO_2_29, 0));
gpio_direction_input(IMX_GPIO_NR(2, 29));
/* Setup of status LED outputs */
imx_iomux_v3_setup_multiple_pads(led_pads, ARRAY_SIZE(led_pads));
/* Switch both LEDs off */
gpio_direction_output(IMX_GPIO_NR(4, 21), 0);
gpio_direction_output(IMX_GPIO_NR(1, 29), 0);
/* Setup of CAN1 and CAN2 signals */
imx_iomux_v3_setup_multiple_pads(can_pads, ARRAY_SIZE(can_pads));
/* Setup of I2C3 signals */
imx_iomux_v3_setup_multiple_pads(i2c3_pads, ARRAY_SIZE(i2c3_pads));
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
return 0;
}
int board_late_init(void)
{
const char *e;
#ifdef CONFIG_FEC_MXC
/*
* FIXME: need to revisit this
* The original code enabled PUE and 100-k pull-down without PKE, so the right
* value here is likely:
* 0 for no pull
* or:
* PAD_CTL_PUS_100K_DOWN for 100-k pull-down
*/
#define FEC_OUT_PAD_CTRL 0
static const iomux_v3_cfg_t fec_pads[] = {
MX25_PAD_FEC_TX_CLK__FEC_TX_CLK,
MX25_PAD_FEC_RX_DV__FEC_RX_DV,
MX25_PAD_FEC_RDATA0__FEC_RDATA0,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA0__FEC_TDATA0, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_TX_EN__FEC_TX_EN, FEC_OUT_PAD_CTRL),
NEW_PAD_CTRL(MX25_PAD_FEC_MDC__FEC_MDC, FEC_OUT_PAD_CTRL),
MX25_PAD_FEC_MDIO__FEC_MDIO,
MX25_PAD_FEC_RDATA1__FEC_RDATA1,
NEW_PAD_CTRL(MX25_PAD_FEC_TDATA1__FEC_TDATA1, FEC_OUT_PAD_CTRL),
MX25_PAD_UPLL_BYPCLK__GPIO_3_16, /* LAN-RESET */
MX25_PAD_UART2_CTS__FEC_RX_ER, /* FEC_RX_ERR */
};
imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
/* assert PHY reset (low) */
gpio_direction_output(IMX_GPIO_NR(3, 16), 0);
udelay(5000);
/* deassert PHY reset */
gpio_set_value(IMX_GPIO_NR(3, 16), 1);
udelay(5000);
#endif
e = env_get("gs_base_board");
if (e != NULL) {
if (strcmp(e, "G283") == 0) {
int key = gpio_get_value(IMX_GPIO_NR(2, 29));
if (key) {
/* Switch on both LEDs to inidcate boot mode */
gpio_set_value(IMX_GPIO_NR(1, 29), 0);
gpio_set_value(IMX_GPIO_NR(4, 21), 0);
env_set("preboot", "run gs_slow_boot");
} else
env_set("preboot", "run gs_fast_boot");
}
}
return 0;
}
int dram_init(void)
{
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
PHYS_SDRAM_SIZE);
return 0;
}

127
configs/MPC8349EMDS_PCI64_defconfig
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@ -1,127 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_64BIT_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2400000
CONFIG_LBLAW1_NAME="BCSR"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_32_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="BCSR"
CONFIG_BR1_OR1_BASE=0xE2400000
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

138
configs/MPC8349EMDS_SDRAM_defconfig
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@ -1,138 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS_SDRAM=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_PCI_INT_ARBITER2_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2400000
CONFIG_LBLAW1_NAME="BCSR"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_LBLAW2=y
CONFIG_LBLAW2_BASE=0xF0000000
CONFIG_LBLAW2_NAME="SDRAM"
CONFIG_LBLAW2_LENGTH_64_MBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_32_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="BCSR"
CONFIG_BR1_OR1_BASE=0xE2400000
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_ELBC_BR2_OR2=y
CONFIG_BR2_OR2_NAME="SDRAM"
CONFIG_BR2_OR2_BASE=0xF0000000
CONFIG_BR2_PORTSIZE_32BIT=y
CONFIG_BR2_MACHINE_SDRAM=y
CONFIG_OR2_COLS_9=y
CONFIG_OR2_ROWS_13=y
CONFIG_OR2_EAD_EXTRA=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_LIBFDT=y

127
configs/MPC8349EMDS_SLAVE_defconfig
View File

@ -1,127 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_CLK_FREQ=66666666
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_64BIT_MODE_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2400000
CONFIG_LBLAW1_NAME="BCSR"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_32_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="BCSR"
CONFIG_BR1_OR1_BASE=0xE2400000
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_SYS_EXTRA_OPTIONS="PCISLAVE"
CONFIG_BOOTDELAY=6
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

130
configs/MPC8349EMDS_defconfig
View File

@ -1,130 +0,0 @@
CONFIG_PPC=y
CONFIG_SYS_TEXT_BASE=0xFE000000
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_SYS_MALLOC_LEN=0x40000
CONFIG_SYS_CLK_FREQ=66000000
CONFIG_MPC83xx=y
CONFIG_HIGH_BATS=y
CONFIG_TARGET_MPC8349EMDS=y
CONFIG_DDR_MC_CLOCK_MODE_1_1=y
CONFIG_SYSTEM_PLL_FACTOR_4_1=y
CONFIG_CORE_PLL_RATIO_2_1=y
CONFIG_PCI_HOST_MODE_ENABLE=y
CONFIG_PCI_INT_ARBITER1_ENABLE=y
CONFIG_PCI_INT_ARBITER2_ENABLE=y
CONFIG_BOOT_MEMORY_SPACE_LOW=y
CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y
CONFIG_TSEC1_MODE_GMII=y
CONFIG_TSEC2_MODE_GMII=y
CONFIG_BAT0=y
CONFIG_BAT0_NAME="SDRAM"
CONFIG_BAT0_BASE=0x00000000
CONFIG_BAT0_LENGTH_256_MBYTES=y
CONFIG_BAT0_ACCESS_RW=y
CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT0_USER_MODE_VALID=y
CONFIG_BAT0_SUPERVISOR_MODE_VALID=y
CONFIG_BAT5=y
CONFIG_BAT5_NAME="IMMR"
CONFIG_BAT5_BASE=0xE0000000
CONFIG_BAT5_LENGTH_256_MBYTES=y
CONFIG_BAT5_ACCESS_RW=y
CONFIG_BAT5_ICACHE_INHIBITED=y
CONFIG_BAT5_ICACHE_GUARDED=y
CONFIG_BAT5_DCACHE_INHIBITED=y
CONFIG_BAT5_DCACHE_GUARDED=y
CONFIG_BAT5_USER_MODE_VALID=y
CONFIG_BAT5_SUPERVISOR_MODE_VALID=y
CONFIG_BAT6=y
CONFIG_BAT6_NAME="STACK_IN_DCACHE"
CONFIG_BAT6_BASE=0xF0000000
CONFIG_BAT6_LENGTH_256_MBYTES=y
CONFIG_BAT6_ACCESS_RW=y
CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_ICACHE_GUARDED=y
CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y
CONFIG_BAT6_DCACHE_GUARDED=y
CONFIG_BAT6_USER_MODE_VALID=y
CONFIG_BAT6_SUPERVISOR_MODE_VALID=y
CONFIG_LBLAW0=y
CONFIG_LBLAW0_BASE=0xFE000000
CONFIG_LBLAW0_NAME="FLASH"
CONFIG_LBLAW0_LENGTH_32_MBYTES=y
CONFIG_LBLAW1=y
CONFIG_LBLAW1_BASE=0xE2400000
CONFIG_LBLAW1_NAME="BCSR"
CONFIG_LBLAW1_LENGTH_32_KBYTES=y
CONFIG_ELBC_BR0_OR0=y
CONFIG_BR0_OR0_NAME="FLASH"
CONFIG_BR0_OR0_BASE=0xFE000000
CONFIG_BR0_PORTSIZE_16BIT=y
CONFIG_OR0_AM_32_MBYTES=y
CONFIG_OR0_XAM_SET=y
CONFIG_OR0_SCY_15=y
CONFIG_OR0_CSNT_EARLIER=y
CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y
CONFIG_OR0_XACS_EXTENDED=y
CONFIG_OR0_TRLX_RELAXED=y
CONFIG_OR0_EHTR_8_CYCLE=y
CONFIG_OR0_EAD_EXTRA=y
CONFIG_ELBC_BR1_OR1=y
CONFIG_BR1_OR1_NAME="BCSR"
CONFIG_BR1_OR1_BASE=0xE2400000
CONFIG_OR1_XAM_SET=y
CONFIG_OR1_SCY_15=y
CONFIG_OR1_CSNT_EARLIER=y
CONFIG_HID0_FINAL_EMCP=y
CONFIG_HID0_FINAL_ICE=y
CONFIG_HID2_HBE=y
CONFIG_ACR_PIPE_DEP_4=y
CONFIG_ACR_RPTCNT_4=y
CONFIG_SPCR_TSEC1EP_3=y
CONFIG_SPCR_TSEC2EP_3=y
CONFIG_LCRR_DBYP_PLL_BYPASSED=y
CONFIG_LCRR_CLKDIV_4=y
CONFIG_PCI_ONE_PCI1=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_STDOUT_VIA_ALIAS=y
CONFIG_BOOTDELAY=6
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_DATE=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xFE080000
CONFIG_ENV_ADDR_REDUND=0xFE0A0000
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
CONFIG_SYS_I2C_SLAVE=0x7F
CONFIG_SYS_I2C_SPEED=400000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_PHY_ATHEROS=y
CONFIG_PHY_BROADCOM=y
CONFIG_PHY_DAVICOM=y
CONFIG_PHY_LXT=y
CONFIG_PHY_MARVELL=y
CONFIG_PHY_NATSEMI=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_SMSC=y
CONFIG_PHY_VITESSE=y
CONFIG_TSEC_ENET=y
CONFIG_SYS_NS16550=y
CONFIG_SPI=y
CONFIG_OF_LIBFDT=y

19
configs/aspenite_defconfig
View File

@ -1,19 +0,0 @@
CONFIG_ARM=y
CONFIG_SKIP_LOWLEVEL_INIT=y
CONFIG_ARCH_CPU_INIT=y
CONFIG_TARGET_ASPENITE=y
CONFIG_SYS_TEXT_BASE=0x600000
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x20000
CONFIG_IDENT_STRING="\nMarvell-Aspenite DB"
CONFIG_SYS_LOAD_ADDR=0x800000
CONFIG_BOOTDELAY=3
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
# CONFIG_NET is not set
# CONFIG_MMC is not set
CONFIG_SYS_NS16550=y
CONFIG_OF_LIBFDT=y

43
configs/bg0900_defconfig
View File

@ -1,43 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX28=y
CONFIG_SYS_TEXT_BASE=0x40002000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x4000
CONFIG_IMX_CONFIG=""
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_BG0900=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL=y
CONFIG_SYS_LOAD_ADDR=0x42000000
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200"
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_NAND_TRIMFFS=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_DOS_PARTITION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_MXS_GPIO=y
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXS=y
CONFIG_MII=y
CONFIG_CONS_INDEX=0
CONFIG_SPI=y
CONFIG_OF_LIBFDT=y

58
configs/flea3_defconfig
View File

@ -1,58 +0,0 @@
CONFIG_ARM=y
CONFIG_SYS_DCACHE_OFF=y
CONFIG_TARGET_FLEA3=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_SYS_I2C_MXC_I2C1=y
CONFIG_SYS_I2C_MXC_I2C2=y
CONFIG_SYS_I2C_MXC_I2C3=y
CONFIG_SYS_MALLOC_LEN=0x110000
CONFIG_SYS_LOAD_ADDR=0x80800000
CONFIG_FIT=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=3
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_BOARD_EARLY_INIT_F=y
CONFIG_HUSH_PARSER=y
CONFIG_SYS_PROMPT="flea3 U-Boot > "
CONFIG_CMD_IMLS=y
CONFIG_CMD_I2C=y
CONFIG_CMD_SPI=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=mxc_nand,nor0=physmap-flash.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=mxc_nand:50m(root1),32m(rootfb),64m(pcache),64m(app1),10m(app2),-(spool);physmap-flash.0:512k(u-boot),64k(env1),64k(env2),3776k(kernel1),3776k(kernel2)"
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_ENV_ADDR=0xA0080000
CONFIG_ENV_ADDR_REDUND=0xA0090000
CONFIG_MXC_GPIO=y
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_MXC=y
CONFIG_SYS_MXC_I2C3_SLAVE=0xfe
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_FLASH_CFI_MTD=y
CONFIG_SYS_FLASH_PROTECTION=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MTD_RAW_NAND=y
CONFIG_NAND_MXC=y
CONFIG_PHYLIB=y
CONFIG_PHY_MICREL=y
CONFIG_PHY_MICREL_KSZ8XXX=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_SPI=y
CONFIG_MXC_SPI=y
CONFIG_OF_LIBFDT=y
CONFIG_FDT_FIXUP_PARTITIONS=y

38
configs/zmx25_defconfig
View File

@ -1,38 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX25=y
CONFIG_SYS_TEXT_BASE=0xA0000000
CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_TARGET_ZMX25=y
CONFIG_IMX_CONFIG=""
CONFIG_SYS_MALLOC_LEN=0x3f8000
CONFIG_SYS_LOAD_ADDR=0x80000000
CONFIG_BOOTDELAY=5
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="boot in %d s\n"
CONFIG_AUTOBOOT_DELAY_STR="delaygs"
CONFIG_AUTOBOOT_STOP_STR="stopgs"
CONFIG_USE_PREBOOT=y
# CONFIG_DISPLAY_CPUINFO is not set
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_HUSH_PARSER=y
# CONFIG_AUTO_COMPLETE is not set
CONFIG_SYS_PROMPT="zmx25> "
CONFIG_CMD_IMLS=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_FAT=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_ENV_ADDR=0xA0040000
# CONFIG_MMC is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_MII=y
CONFIG_MXC_UART=y
CONFIG_USB=y
CONFIG_LZO=y

10
doc/imx/common/imx25.txt
View File

@ -1,10 +0,0 @@
U-Boot for Freescale i.MX25
This file contains information for the port of U-Boot to the Freescale i.MX25
SoC.
1. CONVENTIONS FOR FUSE ASSIGNMENTS
-----------------------------------
1.1 MAC Address: It is stored in the words 26 to 31 of fuse bank 0, using the
natural MAC byte order (i.e. MSB first).

1
drivers/gpio/Makefile
View File

@ -23,7 +23,6 @@ obj-$(CONFIG_IPROC_GPIO) += iproc_gpio.o
obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_KONA_GPIO) += kona_gpio.o
obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o
obj-$(CONFIG_MARVELL_MFP) += mvmfp.o
obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o obj-$(CONFIG_MCP230XX_GPIO) += mcp230xx_gpio.o
obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o
obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o obj-$(CONFIG_MXS_GPIO) += mxs_gpio.o

55
drivers/gpio/mvmfp.c
View File

@ -1,55 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>,
*/
#include <common.h>
#include <asm/io.h>
#include <mvmfp.h>
#include <asm/arch/mfp.h>
/*
* mfp_config
*
* On most of Marvell SoCs (ex. ARMADA100) there is Multi-Funtion-Pin
* configuration registers to configure each GPIO/Function pin on the
* SoC.
*
* This function reads the array of values for
* MFPR_X registers and programms them into respective
* Multi-Function Pin registers.
* It supports - Alternate Function Selection programming.
*
* Whereas,
* The Configureation value is constructed using MFP()
* array consists of 32bit values as defined in MFP(xx,xx..) macro
*/
void mfp_config(u32 *mfp_cfgs)
{
u32 *p_mfpr = NULL;
u32 cfg_val, val;
do {
cfg_val = *mfp_cfgs++;
/* exit if End of configuration table detected */
if (cfg_val == MFP_EOC)
break;
p_mfpr = (u32 *)(MV_MFPR_BASE
+ MFP_REG_GET_OFFSET(cfg_val));
/* Write a mfg register as per configuration */
val = 0;
if (cfg_val & MFP_VALUE_MASK)
val |= cfg_val & MFP_VALUE_MASK;
writel(val, p_mfpr);
} while (1);
/*
* perform a read-back of any MFPR register to make sure the
* previous writings are finished
*/
readl(p_mfpr);
}

6
drivers/gpio/mxc_gpio.c
View File

@ -44,7 +44,7 @@ static unsigned long gpio_ports[] = {
[0] = GPIO1_BASE_ADDR, [0] = GPIO1_BASE_ADDR,
[1] = GPIO2_BASE_ADDR, [1] = GPIO2_BASE_ADDR,
[2] = GPIO3_BASE_ADDR, [2] = GPIO3_BASE_ADDR,
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ #if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \ defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || \
defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050) defined(CONFIG_ARCH_IMX8) || defined(CONFIG_IMXRT1050)
@ -352,7 +352,7 @@ static const struct mxc_gpio_plat mxc_plat[] = {
{ 0, (struct gpio_regs *)GPIO1_BASE_ADDR }, { 0, (struct gpio_regs *)GPIO1_BASE_ADDR },
{ 1, (struct gpio_regs *)GPIO2_BASE_ADDR }, { 1, (struct gpio_regs *)GPIO2_BASE_ADDR },
{ 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, { 2, (struct gpio_regs *)GPIO3_BASE_ADDR },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ #if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, { 3, (struct gpio_regs *)GPIO4_BASE_ADDR },
@ -376,7 +376,7 @@ U_BOOT_DRVINFOS(mxc_gpios) = {
{ "gpio_mxc", &mxc_plat[0] }, { "gpio_mxc", &mxc_plat[0] },
{ "gpio_mxc", &mxc_plat[1] }, { "gpio_mxc", &mxc_plat[1] },
{ "gpio_mxc", &mxc_plat[2] }, { "gpio_mxc", &mxc_plat[2] },
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ #if defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ defined(CONFIG_MX53) || defined(CONFIG_MX6) || \
defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8) defined(CONFIG_IMX8M) || defined(CONFIG_ARCH_IMX8)
{ "gpio_mxc", &mxc_plat[3] }, { "gpio_mxc", &mxc_plat[3] },

24
drivers/mmc/mv_sdhci.c
View File

@ -44,29 +44,6 @@ static void sdhci_mvebu_mbus_config(void __iomem *base)
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
static struct sdhci_ops mv_ops; static struct sdhci_ops mv_ops;
#if defined(CONFIG_SHEEVA_88SV331xV5)
#define SD_CE_ATA_2 0xEA
#define MMC_CARD 0x1000
#define MMC_WIDTH 0x0100
static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
{
struct mmc *mmc = host->mmc;
u32 ata = (unsigned long)host->ioaddr + SD_CE_ATA_2;
if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
if (mmc->bus_width == 8)
writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
else
writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
}
writeb(val, host->ioaddr + reg);
}
#else
#define mv_sdhci_writeb NULL
#endif /* CONFIG_SHEEVA_88SV331xV5 */
#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */ #endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks) int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
@ -84,7 +61,6 @@ int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks)
host->max_clk = max_clk; host->max_clk = max_clk;
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
memset(&mv_ops, 0, sizeof(struct sdhci_ops)); memset(&mv_ops, 0, sizeof(struct sdhci_ops));
mv_ops.write_b = mv_sdhci_writeb;
host->ops = &mv_ops; host->ops = &mv_ops;
#endif #endif

2
drivers/mtd/nand/raw/mxc_nand.c
View File

@ -11,7 +11,7 @@
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/err.h> #include <linux/err.h>
#include <asm/io.h> #include <asm/io.h>
#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \ #if defined(CONFIG_MX27) || \
defined(CONFIG_MX51) || defined(CONFIG_MX53) defined(CONFIG_MX51) || defined(CONFIG_MX53)
#include <asm/arch/imx-regs.h> #include <asm/arch/imx-regs.h>
#endif #endif

5
drivers/mtd/nand/raw/mxc_nand.h
View File

@ -29,11 +29,6 @@
#define is_mxc_nfc_1() 1 #define is_mxc_nfc_1() 1
#define is_mxc_nfc_21() 0 #define is_mxc_nfc_21() 0
#define is_mxc_nfc_32() 0 #define is_mxc_nfc_32() 0
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_NFC_V2_1
#define is_mxc_nfc_1() 0
#define is_mxc_nfc_21() 1
#define is_mxc_nfc_32() 0
#elif defined(CONFIG_MX51) || defined(CONFIG_MX53) #elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
#define MXC_NFC_V3 #define MXC_NFC_V3
#define MXC_NFC_V3_2 #define MXC_NFC_V3_2

2
drivers/net/fec_mxc.c
View File

@ -521,7 +521,7 @@ static int fec_open(struct eth_device *edev)
&fec->eth->ecntrl); &fec->eth->ecntrl);
#endif #endif
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
udelay(100); udelay(100);
/* setup the MII gasket for RMII mode */ /* setup the MII gasket for RMII mode */

4
drivers/net/fec_mxc.h
View File

@ -128,7 +128,7 @@ struct ethernet_regs {
uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */ uint32_t res14[7]; /* MBAR_ETH + 0x2E4-2FC */
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */ uint16_t miigsk_cfgr; /* MBAR_ETH + 0x300 */
uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */ uint16_t res15[3]; /* MBAR_ETH + 0x302-306 */
uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */ uint16_t miigsk_enr; /* MBAR_ETH + 0x308 */
@ -196,7 +196,7 @@ struct ethernet_regs {
#define FEC_X_DES_ACTIVE_TDAR 0x01000000 #define FEC_X_DES_ACTIVE_TDAR 0x01000000
#define FEC_R_DES_ACTIVE_RDAR 0x01000000 #define FEC_R_DES_ACTIVE_RDAR 0x01000000
#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL) #if defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
/* defines for MIIGSK */ /* defines for MIIGSK */
/* RMII frequency control: 0=50MHz, 1=5MHz */ /* RMII frequency control: 0=50MHz, 1=5MHz */
#define MIIGSK_CFGR_FRCONT (1 << 6) #define MIIGSK_CFGR_FRCONT (1 << 6)

3
drivers/serial/Kconfig
View File

@ -645,8 +645,7 @@ config MCFUART
config MXC_UART config MXC_UART
bool "IMX serial port support" bool "IMX serial port support"
depends on ARCH_MX25 || ARCH_MX31 || TARGET_FLEA3 \ depends on ARCH_MX31 || MX5 || MX6 || MX7 || IMX8M
|| MX5 || MX6 || MX7 || IMX8M
help help
If you have a machine based on a Motorola IMX CPU you If you have a machine based on a Motorola IMX CPU you
can enable its onboard serial port by enabling this option. can enable its onboard serial port by enabling this option.

4
drivers/serial/serial-uclass.c
View File

@ -27,10 +27,6 @@ DECLARE_GLOBAL_DATA_PTR;
*/ */
static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE;
#if !CONFIG_VAL(SYS_MALLOC_F_LEN)
#error "Serial is required before relocation - define CONFIG_$(SPL_)SYS_MALLOC_F_LEN to make this work"
#endif
#if CONFIG_IS_ENABLED(SERIAL_PRESENT) #if CONFIG_IS_ENABLED(SERIAL_PRESENT)
static int serial_check_stdout(const void *blob, struct udevice **devp) static int serial_check_stdout(const void *blob, struct udevice **devp)
{ {

12
drivers/spi/mxc_spi.c
View File

@ -23,7 +23,7 @@
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* MX35 and older is CSPI */ /* MX35 and older is CSPI */
#if defined(CONFIG_MX25) || defined(CONFIG_MX31) || defined(CONFIG_MX35) #if defined(CONFIG_MX31)
#define MXC_CSPI #define MXC_CSPI
struct cspi_regs { struct cspi_regs {
u32 rxdata; u32 rxdata;
@ -48,17 +48,10 @@ struct cspi_regs {
#define MXC_CSPICTRL_RXOVF BIT(6) #define MXC_CSPICTRL_RXOVF BIT(6)
#define MXC_CSPIPERIOD_32KHZ BIT(15) #define MXC_CSPIPERIOD_32KHZ BIT(15)
#define MAX_SPI_BYTES 4 #define MAX_SPI_BYTES 4
#if defined(CONFIG_MX25) || defined(CONFIG_MX35)
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
#define MXC_CSPICTRL_TC BIT(7)
#define MXC_CSPICTRL_MAXBITS 0xfff
#else /* MX31 */
#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
#define MXC_CSPICTRL_TC BIT(8) #define MXC_CSPICTRL_TC BIT(8)
#define MXC_CSPICTRL_MAXBITS 0x1f #define MXC_CSPICTRL_MAXBITS 0x1f
#endif
#else /* MX51 and newer is ECSPI */ #else /* MX51 and newer is ECSPI */
#define MXC_ECSPI #define MXC_ECSPI
@ -211,9 +204,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) | MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
MXC_CSPICTRL_DATARATE(div) | MXC_CSPICTRL_DATARATE(div) |
MXC_CSPICTRL_EN | MXC_CSPICTRL_EN |
#ifdef CONFIG_MX35
MXC_CSPICTRL_SSCTL |
#endif
MXC_CSPICTRL_MODE; MXC_CSPICTRL_MODE;
if (mode & SPI_CPHA) if (mode & SPI_CPHA)

104
drivers/usb/host/ehci-mxc.c
View File

@ -67,56 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
unsigned int v; unsigned int v;
v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET); v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
#if defined(CONFIG_MX25) #if defined(CONFIG_MX31)
switch (port) {
case 0: /* OTG port */
v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
MX25_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
MX25_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX25_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX25_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX25_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX25_H1_TLL_BIT;
if (flags & MXC_EHCI_INTERNAL_PHY)
v |= MX25_H1_USBTE_BIT;
if (flags & MXC_EHCI_IPPUE_DOWN)
v |= MX25_H1_IPPUE_DOWN_BIT;
if (flags & MXC_EHCI_IPPUE_UP)
v |= MX25_H1_IPPUE_UP_BIT;
break;
default:
return -EINVAL;
}
#elif defined(CONFIG_MX31)
switch (port) { switch (port) {
case 0: /* OTG port */ case 0: /* OTG port */
v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT); v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
@ -147,55 +98,6 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
if (!(flags & MXC_EHCI_TTL_ENABLED)) if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX31_H2_DT_BIT; v |= MX31_H2_DT_BIT;
break;
default:
return -EINVAL;
}
#elif defined(CONFIG_MX35)
switch (port) {
case 0: /* OTG port */
v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
MX35_OTG_OCPOL_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_OTG_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX35_OTG_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX35_OTG_OCPOL_BIT;
break;
case 1: /* H1 port */
v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
MX35_H1_IPPUE_UP_BIT);
v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
v |= MX35_H1_PM_BIT;
if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
v |= MX35_H1_PP_BIT;
if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
v |= MX35_H1_OCPOL_BIT;
if (!(flags & MXC_EHCI_TTL_ENABLED))
v |= MX35_H1_TLL_BIT;
if (flags & MXC_EHCI_INTERNAL_PHY)
v |= MX35_H1_USBTE_BIT;
if (flags & MXC_EHCI_IPPUE_DOWN)
v |= MX35_H1_IPPUE_DOWN_BIT;
if (flags & MXC_EHCI_IPPUE_UP)
v |= MX35_H1_IPPUE_UP_BIT;
break; break;
default: default:
return -EINVAL; return -EINVAL;
@ -230,10 +132,6 @@ int ehci_hcd_init(int index, enum usb_init_type init,
setbits_le32(&ehci->usbmode, CM_HOST); setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
#ifdef CONFIG_MX35
/* Workaround for ENGcm11601 */
__raw_writel(0, &ehci->sbuscfg);
#endif
udelay(10000); udelay(10000);

2
drivers/w1/Kconfig
View File

@ -20,7 +20,7 @@ config W1_GPIO
config W1_MXC config W1_MXC
bool "Enable 1-wire controller on i.MX processors" bool "Enable 1-wire controller on i.MX processors"
depends on ARCH_MX25 || ARCH_MX31 || ARCH_MX5 depends on ARCH_MX31 || ARCH_MX5
help help
Support the one wire controller found in some members of the NXP Support the one wire controller found in some members of the NXP
i.MX SoC family. i.MX SoC family.

2
drivers/watchdog/Kconfig
View File

@ -24,7 +24,7 @@ config WATCHDOG_AUTOSTART
config WATCHDOG_TIMEOUT_MSECS config WATCHDOG_TIMEOUT_MSECS
int "Watchdog timeout in msec" int "Watchdog timeout in msec"
default 128000 if ARCH_MX25 || ARCH_MX31 || ARCH_MX5 || ARCH_MX6 default 128000 if ARCH_MX31 || ARCH_MX5 || ARCH_MX6
default 128000 if ARCH_MX7 || ARCH_VF610 default 128000 if ARCH_MX7 || ARCH_VF610
default 30000 if ARCH_SOCFPGA default 30000 if ARCH_SOCFPGA
default 60000 default 60000

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