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arm: fsl-layerscape: Migrate more DP-DDR options to Kconfig

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Based on current usage, migrate a number of DP-DDR related options to
Kconfig.

Cc: Priyanka Jain <priyanka.jain@nxp.com>
Cc: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2022-03-30 18:07:35 -04:00
parent 001a56b008
commit 6751b70055
3 changed files with 25 additions and 13 deletions
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3
README
View File

@ -487,9 +487,6 @@ The following options need to be configured:
CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
Number of controllers used for other than main memory. Number of controllers used for other than main memory.
CONFIG_SYS_FSL_HAS_DP_DDR
Defines the SoC has DP-DDR used for DPAA.
CONFIG_SYS_FSL_SEC_BE CONFIG_SYS_FSL_SEC_BE
Defines the SEC controller register space as Big Endian Defines the SEC controller register space as Big Endian

25
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
View File

@ -502,6 +502,31 @@ config SYS_FSL_HAS_CCN508
config SYS_FSL_HAS_DP_DDR config SYS_FSL_HAS_DP_DDR
bool bool
help
Defines the SoC has DP-DDR used for DPAA.
config DP_DDR_CTRL
int
depends on SYS_FSL_HAS_DP_DDR
default 2 if ARCH_LS2080A
config DP_DDR_NUM_CTRLS
int
depends on SYS_FSL_HAS_DP_DDR
default 1 if ARCH_LS2080A
config SYS_DP_DDR_BASE
hex
depends on SYS_FSL_HAS_DP_DDR
default 0x6000000000 if ARCH_LS2080A
config SYS_DP_DDR_BASE_PHY
int
depends on SYS_FSL_HAS_DP_DDR
default 0 if ARCH_LS2080A
help
DDR controller uses this value as the base address for binding.
It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
config SYS_FSL_SRDS_1 config SYS_FSL_SRDS_1
bool bool

10
include/configs/ls2080a_common.h
View File

@ -40,16 +40,6 @@
#define CPU_RELEASE_ADDR secondary_boot_addr #define CPU_RELEASE_ADDR secondary_boot_addr
#define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
#define CONFIG_SYS_DP_DDR_BASE 0x6000000000ULL
/*
* DDR controller use 0 as the base address for binding.
* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
*/
#define CONFIG_SYS_DP_DDR_BASE_PHY 0
#define CONFIG_DP_DDR_CTRL 2
#define CONFIG_DP_DDR_NUM_CTRLS 1
#endif
/* Generic Timer Definitions */ /* Generic Timer Definitions */
/* /*