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ARMV7: Fix udelay for OMAP4

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The OMAP4 x-load code sets gptimer1 clock source to 32Khz.  This isn't
acceptable for udelay.  This patch changes from gptimer1 to gptimer2,
which uses sys_clk at 38.4 Mhz.

Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
This commit is contained in:
Steve Sakoman 2010-07-20 14:56:07 -07:00 committed by Sandeep Paulraj
parent 2ad853c348
commit 674e0b217f
3 changed files with 2 additions and 11 deletions
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9
arch/arm/cpu/armv7/omap-common/timer.c
View File

@ -41,12 +41,8 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE;
/*
* Nothing really to do with interrupts, just starts up a counter.
* We run the counter with 13MHz, divided by 8, resulting in timer
* frequency of 1.625MHz. With 32bit counter register, counter
* overflows in ~44min
*/
/* 13MHz / 8 = 1.625MHz */
#define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV))
#define TIMER_LOAD_VAL 0xffffffff
@ -84,11 +80,6 @@ void set_timer(ulong t)
/* delay x useconds */
void __udelay(unsigned long usec)
{
#if defined(CONFIG_OMAP44XX)
/* TODO temporary hack until OMAP4 clock setup routines are present */
if (usec > 1000)
usec = usec/1000;
#endif
long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
unsigned long now, last = readl(&timer_base->tcrr);

2
include/configs/omap4_panda.h
View File

@ -196,7 +196,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x80000000
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT1_BASE
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000

2
include/configs/omap4_sdp4430.h
View File

@ -197,7 +197,7 @@
#define CONFIG_SYS_LOAD_ADDR 0x80000000
/* Use General purpose timer 1 */
#define CONFIG_SYS_TIMERBASE GPT1_BASE
#define CONFIG_SYS_TIMERBASE GPT2_BASE
#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ 1000