sound: x86: link: Add sound support
Add sound support for link, using the HDA codec implementation. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
@@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE
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imply USB_EHCI_HCD
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imply USB_XHCI_HCD
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imply VIDEO_VESA
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imply SOUND_IVYBRIDGE
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if NORTHBRIDGE_INTEL_IVYBRIDGE
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@@ -177,6 +177,35 @@ static void sandybridge_setup_northbridge_bars(struct udevice *dev)
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dm_pci_write_config8(dev, PAM6, 0x33);
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}
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/**
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* sandybridge_init_iommu() - Set up IOMMU so that azalia can be used
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*
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* It is not obvious where these values come from. They may be undocumented.
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*/
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static void sandybridge_init_iommu(struct udevice *dev)
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{
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u32 capid0_a;
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dm_pci_read_config32(dev, 0xe4, &capid0_a);
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if (capid0_a & (1 << 23)) {
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log_debug("capid0_a not needed\n");
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return;
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}
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/* setup BARs */
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writel(IOMMU_BASE1 >> 32, MCHBAR_REG(0x5404));
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writel(IOMMU_BASE1 | 1, MCHBAR_REG(0x5400));
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writel(IOMMU_BASE2 >> 32, MCHBAR_REG(0x5414));
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writel(IOMMU_BASE2 | 1, MCHBAR_REG(0x5410));
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/* lock policies */
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writel(0x80000000, IOMMU_BASE1 + 0xff0);
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/* Enable azalia sound */
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writel(0x20000000, IOMMU_BASE2 + 0xff0);
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writel(0xa0000000, IOMMU_BASE2 + 0xff0);
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}
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static int bd82x6x_northbridge_early_init(struct udevice *dev)
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{
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const int chipset_type = SANDYBRIDGE_MOBILE;
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@@ -197,6 +226,9 @@ static int bd82x6x_northbridge_early_init(struct udevice *dev)
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sandybridge_setup_northbridge_bars(dev);
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/* Setup IOMMU BARs */
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sandybridge_init_iommu(dev);
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/* Device Enable */
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dm_pci_write_config32(dev, DEVEN, DEVEN_HOST | DEVEN_IGD);
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@@ -1,6 +1,8 @@
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/dts-v1/;
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#include <dt-bindings/gpio/x86-gpio.h>
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#include <dt-bindings/sound/azalia.h>
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#include <pci_ids.h>
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/include/ "skeleton.dtsi"
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/include/ "keyboard.dtsi"
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@@ -372,6 +374,32 @@
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compatible = "ehci-pci";
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};
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hda@1b,0 {
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reg = <0x0000d800 0 0 0 0>;
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compatible = "intel,bd82x6x-hda";
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/* These correspond to the Intel HDA specification */
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beep-verbs = <
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0x00170500 /* power up codec */
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0x00270500 /* power up DAC */
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0x00b70500 /* power up speaker */
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0x00b70740 /* enable speaker out */
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0x00b78d00 /* enable EAPD pin */
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0x00b70c02 /* set EAPD pin */
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0x0143b013>; /* beep volume */
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codecs {
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creative_codec: creative-ca0132 {
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vendor-id = <PCI_VENDOR_ID_CREATIVE>;
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device-id = <PCI_DEVICE_ID_CREATIVE_CA01322>;
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};
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intel_hdmi: hdmi {
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vendor-id = <PCI_VENDOR_ID_INTEL>;
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device-id = <PCI_DEVICE_ID_INTEL_COUGARPOINT_HDMI>;
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};
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};
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};
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usb_0: usb@1d,0 {
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reg = <0x0000e800 0 0 0 0>;
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compatible = "ehci-pci";
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@@ -492,3 +520,71 @@
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};
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};
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&creative_codec {
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verbs = <
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/**
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* Malcolm Setup. These correspond to the Intel HDA
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* specification.
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*/
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0x01570d09 0x01570c23 0x01570a01 0x01570df0
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0x01570efe 0x01570775 0x015707d3 0x01570709
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0x01570753 0x015707d4 0x015707ef 0x01570775
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0x015707d3 0x01570709 0x01570702 0x01570737
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0x01570778 0x01553cce 0x015575c9 0x01553dce
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0x0155b7c9 0x01570de8 0x01570efe 0x01570702
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0x01570768 0x01570762 0x01553ace 0x015546c9
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0x01553bce 0x0155e8c9 0x01570d49 0x01570c88
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0x01570d20 0x01570e19 0x01570700 0x01571a05
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0x01571b29 0x01571a04 0x01571b29 0x01570a01
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/* Pin Widget Verb Table */
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/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x144dc0c2 */
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AZALIA_SUBVENDOR(0x0, 0x144dc0c2)
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/*
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* Pin Complex (NID 0x0B) Port-G Analog Unknown
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* Speaker at Int N/A
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*/
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AZALIA_PIN_CFG(0x0, 0x0b, 0x901700f0)
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/* Pin Complex (NID 0x0C) N/C */
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AZALIA_PIN_CFG(0x0, 0x0c, 0x70f000f0)
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/* Pin Complex (NID 0x0D) N/C */
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AZALIA_PIN_CFG(0x0, 0x0d, 0x70f000f0)
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/* Pin Complex (NID 0x0E) N/C */
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AZALIA_PIN_CFG(0x0, 0x0e, 0x70f000f0)
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/* Pin Complex (NID 0x0F) N/C */
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AZALIA_PIN_CFG(0x0, 0x0f, 0x70f000f0)
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/* Pin Complex (NID 0x10) Port-D 1/8 Black HP Out at Ext Left */
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AZALIA_PIN_CFG(0x0, 0x10, 0x032110f0)
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/* Pin Complex (NID 0x11) Port-B Click Mic */
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AZALIA_PIN_CFG(0x0, 0x11, 0x90a700f0)
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/* Pin Complex (NID 0x12) Port-C Combo Jack Mic or D-Mic */
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AZALIA_PIN_CFG(0x0, 0x12, 0x03a110f0)
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/* Pin Complex (NID 0x13) What you hear */
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AZALIA_PIN_CFG(0x0, 0x13, 0x90d600f0)>;
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};
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&intel_hdmi {
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verbs = <
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/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
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AZALIA_SUBVENDOR(0x3, 0x80860101)
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/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
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AZALIA_PIN_CFG(0x3, 0x05, 0x18560010)
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/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
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AZALIA_PIN_CFG(0x3, 0x06, 0x18560020)
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/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
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AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)>;
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};
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@@ -43,6 +43,9 @@
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/* 4 KB per PCIe device */
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#define DEFAULT_PCIEXBAR CONFIG_PCIE_ECAM_BASE
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#define IOMMU_BASE1 0xfed90000ULL
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#define IOMMU_BASE2 0xfed91000ULL
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/* Device 0:0.0 PCI configuration space (Host Bridge) */
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#define EPBAR 0x40
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#define MCHBAR 0x48
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