x86: ivybridge: Drop the SMM-locking code
U-Boot does not support SMM yet, so we can drop this code. It is easy to bring back when needed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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@ -379,59 +379,6 @@ static void enable_clock_gating(struct udevice *pch)
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setbits_le32(RCB_REG(0x3564), 0x3);
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}
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#if CONFIG_HAVE_SMI_HANDLER
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static void pch_lock_smm(pci_dev_t dev)
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{
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#if TEST_SMM_FLASH_LOCKDOWN
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u8 reg8;
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#endif
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if (acpi_slp_type != 3) {
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#if ENABLE_ACPI_MODE_IN_COREBOOT
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debug("Enabling ACPI via APMC:\n");
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outb(0xe1, 0xb2); /* Enable ACPI mode */
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debug("done.\n");
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#else
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debug("Disabling ACPI via APMC:\n");
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outb(0x1e, 0xb2); /* Disable ACPI mode */
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debug("done.\n");
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#endif
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}
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/* Don't allow evil boot loaders, kernels, or
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* userspace applications to deceive us:
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*/
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smm_lock();
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#if TEST_SMM_FLASH_LOCKDOWN
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/* Now try this: */
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debug("Locking BIOS to RO... ");
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reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
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(reg8 & 1) ? "rw" : "ro");
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reg8 &= ~(1 << 0); /* clear BIOSWE */
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x86_pci_write_config8(dev, 0xdc, reg8);
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reg8 |= (1 << 1); /* set BLE */
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x86_pci_write_config8(dev, 0xdc, reg8);
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debug("ok.\n");
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reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
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(reg8 & 1) ? "rw" : "ro");
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debug("Writing:\n");
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writeb(0, 0xfff00000);
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debug("Testing:\n");
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reg8 |= (1 << 0); /* set BIOSWE */
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x86_pci_write_config8(dev, 0xdc, reg8);
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reg8 = x86_pci_read_config8(dev, 0xdc); /* BIOS_CNTL */
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debug(" BLE: %s; BWE: %s\n", (reg8 & 2) ? "on" : "off",
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(reg8 & 1) ? "rw" : "ro");
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debug("Done.\n");
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#endif
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}
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#endif
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static void pch_disable_smm_only_flashing(struct udevice *pch)
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{
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u8 reg8;
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@ -596,10 +543,6 @@ static int lpc_init_extra(struct udevice *dev)
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pch_disable_smm_only_flashing(pch);
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#if CONFIG_HAVE_SMI_HANDLER
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pch_lock_smm(dev);
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#endif
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pch_fixups(pch);
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return 0;
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