Add support for CompactFlash on ATC board
(includes support for Intel 82365 and compatible PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers)
This commit is contained in:
wdenk
parent
45219c4660
commit
66fd3d1ce7
@ -2,6 +2,10 @@
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Changes since U-Boot 0.3.1:
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======================================================================
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* Add support for CompactFlash on ATC board
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(includes support for Intel 82365 and compatible PC Card controllers,
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and Yenta-compatible PCI-to-CardBus controllers)
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* Patch by Mathijs Haarman, 08 May 2003:
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Add lan91c96 driver (tested on Lubbock and custom PXA250 board only)
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@ -24,6 +24,7 @@
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#include <common.h>
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#include <ioports.h>
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#include <mpc8260.h>
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#include <pci.h>
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/*
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* I/O Port configuration table
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@ -364,3 +365,14 @@ void doc_init (void)
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doc_probe (CFG_DOC_BASE);
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}
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#endif
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#ifdef CONFIG_PCI
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struct pci_controller hose;
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extern void pci_mpc8250_init(struct pci_controller *);
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void pci_init_board(void)
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{
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pci_mpc8250_init(&hose);
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}
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#endif
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@ -72,16 +72,20 @@ int pcmcia_on (void);
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
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static int pcmcia_off (void);
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#endif
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#ifdef CONFIG_I82365
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extern int i82365_init (void);
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extern void i82365_exit (void);
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#else /* ! CONFIG_I82365 */
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
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static int hardware_disable(int slot);
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#endif
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static int hardware_enable (int slot);
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static int voltage_set(int slot, int vcc, int vpp);
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#ifdef CONFIG_IDE_8xx_PCCARD
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static void print_funcid (int func);
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static void print_fixed (volatile uchar *p);
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static int identify (volatile uchar *p);
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static int check_ide_device (int slot);
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#endif /* CONFIG_IDE_8xx_PCCARD */
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static u_int m8xx_get_graycode(u_int size);
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#if 0
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@ -99,6 +103,15 @@ static u_int *pcmcia_pgcrx[2] = {
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#define PCMCIA_PGCRX(slot) (*pcmcia_pgcrx[slot])
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#endif /* CONFIG_I82365 */
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#ifdef CONFIG_IDE_8xx_PCCARD
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static void print_funcid (int func);
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static void print_fixed (volatile uchar *p);
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static int identify (volatile uchar *p);
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static int check_ide_device (int slot);
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#endif /* CONFIG_IDE_8xx_PCCARD */
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const char *indent = "\t ";
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/* -------------------------------------------------------------------- */
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@ -128,6 +141,24 @@ int do_pinit (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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/* -------------------------------------------------------------------- */
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#ifdef CONFIG_I82365
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int pcmcia_on (void)
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{
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u_int rc;
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debug ("Enable PCMCIA " PCMCIA_SLOT_MSG "\n");
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rc = i82365_init();
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if (rc == 0)
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{
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rc = check_ide_device(0);
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}
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return (rc);
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}
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#else
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#if defined(CONFIG_LWMON)
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# define CFG_PCMCIA_TIMING (PCMCIA_SHT(9) | PCMCIA_SST(3) | PCMCIA_SL(12))
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#else
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@ -222,11 +253,22 @@ int pcmcia_on (void)
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}
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return (rc);
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}
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#endif /* CONFIG_I82365 */
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/* -------------------------------------------------------------------- */
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#if (CONFIG_COMMANDS & CFG_CMD_PCMCIA)
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#ifdef CONFIG_I82365
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static int pcmcia_off (void)
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{
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printf ("Disable PCMCIA " PCMCIA_SLOT_MSG "\n");
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i82365_exit();
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return 0;
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}
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#else
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static int pcmcia_off (void)
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{
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int i;
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@ -258,6 +300,7 @@ static int pcmcia_off (void)
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hardware_disable(_slot_);
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return 0;
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}
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#endif /* CONFIG_I82365 */
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#endif /* CFG_CMD_PCMCIA */
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@ -95,7 +95,11 @@
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*/
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#define PCI_MSTR_IO_LOCAL 0xA0000000 /* Local base */
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#ifdef CONFIG_ATC
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#define PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
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#else
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#define PCI_MSTR_IO_BUS 0xA0000000 /* PCI base */
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#endif
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#define CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
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#define PCI_MSTR_IO_SIZE 0x10000000 /* 256MB */
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#define POCMR2_MASK_ATTRIB (POCMR_MASK_256MB | POCMR_ENABLE | POCMR_PCI_IO)
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@ -30,8 +30,8 @@ LIB = libdrivers.a
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OBJS = 3c589.o 5701rls.o at91rm9200_ether.o \
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bcm570x.o bcm570x_autoneg.o \
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cfb_console.o cs8900.o ct69000.o dc2114x.o \
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eepro100.o i8042.o inca-ip_sw.o lan91c96.o\
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natsemi.o ns16550.o ns8382x.o ns87308.o \
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eepro100.o i8042.o i82365.o inca-ip_sw.o \
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lan91c96.o natsemi.o ns16550.o ns8382x.o ns87308.o \
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pci.o pci_auto.o pci_indirect.o \
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pcnet.o plb2800_eth.o \
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s3c24x0_i2c.o sed13806.o serial.o \
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590
drivers/i82365.c
Normal file
590
drivers/i82365.c
Normal file
@ -0,0 +1,590 @@
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/*
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* (C) Copyright 2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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********************************************************************
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*
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* Lots of code copied from:
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*
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* i82365.c 1.352 - Linux driver for Intel 82365 and compatible
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* PC Card controllers, and Yenta-compatible PCI-to-CardBus controllers.
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* (C) 1999 David A. Hinds <dahinds@users.sourceforge.net>
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*/
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#include <common.h>
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#ifdef CONFIG_I82365
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#include <command.h>
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#include <pci.h>
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#include <pcmcia.h>
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#include <cmd_pcmcia.h>
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#include <asm/io.h>
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#include <pcmcia/ss.h>
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#include <pcmcia/i82365.h>
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#include <pcmcia/ti113x.h>
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#include <pcmcia/yenta.h>
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/* #define DEBUG */
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static struct pci_device_id supported[] = {
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{PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_1510},
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{0, 0}
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};
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#define CYCLE_TIME 120
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#ifdef DEBUG
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static void i82365_dump_regions (pci_dev_t dev);
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#endif
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typedef struct socket_info_t {
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pci_dev_t dev;
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u_short bcr;
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u_char pci_lat, cb_lat, sub_bus, cache;
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u_int cb_phys;
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socket_cap_t cap;
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ti113x_state_t state;
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} socket_info_t;
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static socket_info_t socket;
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static socket_state_t state;
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static struct pccard_mem_map mem;
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static struct pccard_io_map io;
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/*====================================================================*/
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/* Some PCI shortcuts */
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static int pci_readb (socket_info_t * s, int r, u_char * v)
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{
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return pci_read_config_byte (s->dev, r, v);
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}
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static int pci_writeb (socket_info_t * s, int r, u_char v)
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{
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return pci_write_config_byte (s->dev, r, v);
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}
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static int pci_readw (socket_info_t * s, int r, u_short * v)
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{
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return pci_read_config_word (s->dev, r, v);
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}
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static int pci_writew (socket_info_t * s, int r, u_short v)
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{
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return pci_write_config_word (s->dev, r, v);
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}
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static int pci_readl (socket_info_t * s, int r, u_int * v)
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{
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return pci_read_config_dword (s->dev, r, v);
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}
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static int pci_writel (socket_info_t * s, int r, u_int v)
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{
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return pci_write_config_dword (s->dev, r, v);
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}
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#define cb_readb(s, r) readb((s)->cb_phys + (r))
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#define cb_readl(s, r) readl((s)->cb_phys + (r))
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#define cb_writeb(s, r, v) writeb(v, (s)->cb_phys + (r))
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#define cb_writel(s, r, v) writel(v, (s)->cb_phys + (r))
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/*====================================================================*/
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static u_char i365_get (socket_info_t * s, u_short reg)
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{
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return cb_readb (s, 0x0800 + reg);
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}
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static void i365_set (socket_info_t * s, u_short reg, u_char data)
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{
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cb_writeb (s, 0x0800 + reg, data);
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}
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static void i365_bset (socket_info_t * s, u_short reg, u_char mask)
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{
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i365_set (s, reg, i365_get (s, reg) | mask);
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}
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static void i365_bclr (socket_info_t * s, u_short reg, u_char mask)
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{
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i365_set (s, reg, i365_get (s, reg) & ~mask);
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}
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#if 0 /* not used */
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static void i365_bflip (socket_info_t * s, u_short reg, u_char mask, int b)
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{
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u_char d = i365_get (s, reg);
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i365_set (s, reg, (b) ? (d | mask) : (d & ~mask));
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}
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static u_short i365_get_pair (socket_info_t * s, u_short reg)
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{
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return (i365_get (s, reg) + (i365_get (s, reg + 1) << 8));
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}
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#endif /* not used */
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static void i365_set_pair (socket_info_t * s, u_short reg, u_short data)
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{
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i365_set (s, reg, data & 0xff);
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i365_set (s, reg + 1, data >> 8);
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}
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/*======================================================================
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Code to save and restore global state information for TI 1130 and
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TI 1131 controllers, and to set and report global configuration
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options.
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======================================================================*/
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static void ti113x_get_state (socket_info_t * s)
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{
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ti113x_state_t *p = &s->state;
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pci_readl (s, TI113X_SYSTEM_CONTROL, &p->sysctl);
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pci_readb (s, TI113X_CARD_CONTROL, &p->cardctl);
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pci_readb (s, TI113X_DEVICE_CONTROL, &p->devctl);
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pci_readb (s, TI1250_DIAGNOSTIC, &p->diag);
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pci_readl (s, TI12XX_IRQMUX, &p->irqmux);
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}
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static void ti113x_set_state (socket_info_t * s)
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{
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ti113x_state_t *p = &s->state;
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pci_writel (s, TI113X_SYSTEM_CONTROL, p->sysctl);
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pci_writeb (s, TI113X_CARD_CONTROL, p->cardctl);
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pci_writeb (s, TI113X_DEVICE_CONTROL, p->devctl);
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pci_writeb (s, TI1250_MULTIMEDIA_CTL, 0);
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pci_writeb (s, TI1250_DIAGNOSTIC, p->diag);
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pci_writel (s, TI12XX_IRQMUX, p->irqmux);
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i365_set_pair (s, TI113X_IO_OFFSET (0), 0);
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i365_set_pair (s, TI113X_IO_OFFSET (1), 0);
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}
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static u_int ti113x_set_opts (socket_info_t * s)
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{
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ti113x_state_t *p = &s->state;
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u_int mask = 0xffff;
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p->cardctl &= ~TI113X_CCR_ZVENABLE;
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p->cardctl |= TI113X_CCR_SPKROUTEN;
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return mask;
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}
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/*======================================================================
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Routines to handle common CardBus options
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======================================================================*/
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/* Default settings for PCI command configuration register */
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#define CMD_DFLT (PCI_COMMAND_IO|PCI_COMMAND_MEMORY| \
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PCI_COMMAND_MASTER|PCI_COMMAND_WAIT)
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static void cb_get_state (socket_info_t * s)
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{
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pci_readb (s, PCI_CACHE_LINE_SIZE, &s->cache);
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pci_readb (s, PCI_LATENCY_TIMER, &s->pci_lat);
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pci_readb (s, CB_LATENCY_TIMER, &s->cb_lat);
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pci_readb (s, CB_CARDBUS_BUS, &s->cap.cardbus);
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pci_readb (s, CB_SUBORD_BUS, &s->sub_bus);
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pci_readw (s, CB_BRIDGE_CONTROL, &s->bcr);
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}
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static void cb_set_state (socket_info_t * s)
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{
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pci_writel (s, CB_LEGACY_MODE_BASE, 0);
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pci_writel (s, PCI_BASE_ADDRESS_0, s->cb_phys);
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pci_writew (s, PCI_COMMAND, CMD_DFLT);
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pci_writeb (s, PCI_CACHE_LINE_SIZE, s->cache);
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pci_writeb (s, PCI_LATENCY_TIMER, s->pci_lat);
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pci_writeb (s, CB_LATENCY_TIMER, s->cb_lat);
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pci_writeb (s, CB_CARDBUS_BUS, s->cap.cardbus);
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pci_writeb (s, CB_SUBORD_BUS, s->sub_bus);
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pci_writew (s, CB_BRIDGE_CONTROL, s->bcr);
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}
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static void cb_set_opts (socket_info_t * s)
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{
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if (s->cache == 0)
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s->cache = 8;
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if (s->pci_lat == 0)
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s->pci_lat = 0xa8;
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if (s->cb_lat == 0)
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s->cb_lat = 0xb0;
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}
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/*======================================================================
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Power control for Cardbus controllers: used both for 16-bit and
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Cardbus cards.
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======================================================================*/
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static int cb_set_power (socket_info_t * s, socket_state_t * state)
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{
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u_int reg = 0;
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/* restart card voltage detection if it seems appropriate */
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if ((state->Vcc == 0) && (state->Vpp == 0) &&
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!(cb_readl (s, CB_SOCKET_STATE) & CB_SS_VSENSE))
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cb_writel (s, CB_SOCKET_FORCE, CB_SF_CVSTEST);
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switch (state->Vcc) {
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case 0:
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reg = 0;
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break;
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case 33:
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reg = CB_SC_VCC_3V;
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break;
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case 50:
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reg = CB_SC_VCC_5V;
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break;
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default:
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return -1;
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}
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switch (state->Vpp) {
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case 0:
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break;
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case 33:
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reg |= CB_SC_VPP_3V;
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break;
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case 50:
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reg |= CB_SC_VPP_5V;
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break;
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case 120:
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reg |= CB_SC_VPP_12V;
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break;
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default:
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return -1;
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}
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if (reg != cb_readl (s, CB_SOCKET_CONTROL))
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cb_writel (s, CB_SOCKET_CONTROL, reg);
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return 0;
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}
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/*======================================================================
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Generic routines to get and set controller options
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======================================================================*/
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static void get_bridge_state (socket_info_t * s)
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{
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ti113x_get_state (s);
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cb_get_state (s);
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}
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static void set_bridge_state (socket_info_t * s)
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{
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cb_set_state (s);
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i365_set (s, I365_GBLCTL, 0x00);
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i365_set (s, I365_GENCTL, 0x00);
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ti113x_set_state (s);
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}
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static void set_bridge_opts (socket_info_t * s)
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{
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||||
ti113x_set_opts (s);
|
||||
cb_set_opts (s);
|
||||
}
|
||||
|
||||
/*====================================================================*/
|
||||
|
||||
static int i365_get_status (socket_info_t * s, u_int * value)
|
||||
{
|
||||
u_int status;
|
||||
|
||||
status = i365_get (s, I365_STATUS);
|
||||
*value = ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
|
||||
if (i365_get (s, I365_INTCTL) & I365_PC_IOCARD) {
|
||||
*value |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
|
||||
} else {
|
||||
*value |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
|
||||
*value |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
|
||||
}
|
||||
*value |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
|
||||
*value |= (status & I365_CS_READY) ? SS_READY : 0;
|
||||
*value |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
|
||||
|
||||
status = cb_readl (s, CB_SOCKET_STATE);
|
||||
*value |= (status & CB_SS_32BIT) ? SS_CARDBUS : 0;
|
||||
*value |= (status & CB_SS_3VCARD) ? SS_3VCARD : 0;
|
||||
*value |= (status & CB_SS_XVCARD) ? SS_XVCARD : 0;
|
||||
*value |= (status & CB_SS_VSENSE) ? 0 : SS_PENDING;
|
||||
/* For now, ignore cards with unsupported voltage keys */
|
||||
if (*value & SS_XVCARD)
|
||||
*value &= ~(SS_DETECT | SS_3VCARD | SS_XVCARD);
|
||||
|
||||
return 0;
|
||||
} /* i365_get_status */
|
||||
|
||||
static int i365_set_socket (socket_info_t * s, socket_state_t * state)
|
||||
{
|
||||
u_char reg;
|
||||
|
||||
set_bridge_state (s);
|
||||
|
||||
/* IO card, RESET flag */
|
||||
reg = 0;
|
||||
reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
|
||||
reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
|
||||
i365_set (s, I365_INTCTL, reg);
|
||||
|
||||
reg = I365_PWR_NORESET;
|
||||
if (state->flags & SS_PWR_AUTO)
|
||||
reg |= I365_PWR_AUTO;
|
||||
if (state->flags & SS_OUTPUT_ENA)
|
||||
reg |= I365_PWR_OUT;
|
||||
|
||||
cb_set_power (s, state);
|
||||
reg |= i365_get (s, I365_POWER) & (I365_VCC_MASK | I365_VPP1_MASK);
|
||||
|
||||
if (reg != i365_get (s, I365_POWER))
|
||||
i365_set (s, I365_POWER, reg);
|
||||
|
||||
return 0;
|
||||
} /* i365_set_socket */
|
||||
|
||||
/*====================================================================*/
|
||||
|
||||
static int i365_set_mem_map (socket_info_t * s, struct pccard_mem_map *mem)
|
||||
{
|
||||
u_short base, i;
|
||||
u_char map;
|
||||
|
||||
map = mem->map;
|
||||
if ((map > 4) ||
|
||||
(mem->card_start > 0x3ffffff) ||
|
||||
(mem->sys_start > mem->sys_stop) ||
|
||||
(mem->speed > 1000)) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* Turn off the window before changing anything */
|
||||
if (i365_get (s, I365_ADDRWIN) & I365_ENA_MEM (map))
|
||||
i365_bclr (s, I365_ADDRWIN, I365_ENA_MEM (map));
|
||||
|
||||
/* Take care of high byte, for PCI controllers */
|
||||
i365_set (s, CB_MEM_PAGE (map), mem->sys_start >> 24);
|
||||
|
||||
base = I365_MEM (map);
|
||||
i = (mem->sys_start >> 12) & 0x0fff;
|
||||
if (mem->flags & MAP_16BIT)
|
||||
i |= I365_MEM_16BIT;
|
||||
if (mem->flags & MAP_0WS)
|
||||
i |= I365_MEM_0WS;
|
||||
i365_set_pair (s, base + I365_W_START, i);
|
||||
|
||||
i = (mem->sys_stop >> 12) & 0x0fff;
|
||||
switch (mem->speed / CYCLE_TIME) {
|
||||
case 0:
|
||||
break;
|
||||
case 1:
|
||||
i |= I365_MEM_WS0;
|
||||
break;
|
||||
case 2:
|
||||
i |= I365_MEM_WS1;
|
||||
break;
|
||||
default:
|
||||
i |= I365_MEM_WS1 | I365_MEM_WS0;
|
||||
break;
|
||||
}
|
||||
i365_set_pair (s, base + I365_W_STOP, i);
|
||||
|
||||
i = ((mem->card_start - mem->sys_start) >> 12) & 0x3fff;
|
||||
if (mem->flags & MAP_WRPROT)
|
||||
i |= I365_MEM_WRPROT;
|
||||
if (mem->flags & MAP_ATTRIB)
|
||||
i |= I365_MEM_REG;
|
||||
i365_set_pair (s, base + I365_W_OFF, i);
|
||||
|
||||
/* Turn on the window if necessary */
|
||||
if (mem->flags & MAP_ACTIVE)
|
||||
i365_bset (s, I365_ADDRWIN, I365_ENA_MEM (map));
|
||||
return 0;
|
||||
} /* i365_set_mem_map */
|
||||
|
||||
static int i365_set_io_map (socket_info_t * s, struct pccard_io_map *io)
|
||||
{
|
||||
u_char map, ioctl;
|
||||
|
||||
map = io->map;
|
||||
if ((map > 1) || (io->start > 0xffff) || (io->stop > 0xffff) ||
|
||||
(io->stop < io->start))
|
||||
return -1;
|
||||
/* Turn off the window before changing anything */
|
||||
if (i365_get (s, I365_ADDRWIN) & I365_ENA_IO (map))
|
||||
i365_bclr (s, I365_ADDRWIN, I365_ENA_IO (map));
|
||||
i365_set_pair (s, I365_IO (map) + I365_W_START, io->start);
|
||||
i365_set_pair (s, I365_IO (map) + I365_W_STOP, io->stop);
|
||||
ioctl = i365_get (s, I365_IOCTL) & ~I365_IOCTL_MASK (map);
|
||||
if (io->speed)
|
||||
ioctl |= I365_IOCTL_WAIT (map);
|
||||
if (io->flags & MAP_0WS)
|
||||
ioctl |= I365_IOCTL_0WS (map);
|
||||
if (io->flags & MAP_16BIT)
|
||||
ioctl |= I365_IOCTL_16BIT (map);
|
||||
if (io->flags & MAP_AUTOSZ)
|
||||
ioctl |= I365_IOCTL_IOCS16 (map);
|
||||
i365_set (s, I365_IOCTL, ioctl);
|
||||
/* Turn on the window if necessary */
|
||||
if (io->flags & MAP_ACTIVE)
|
||||
i365_bset (s, I365_ADDRWIN, I365_ENA_IO (map));
|
||||
return 0;
|
||||
} /* i365_set_io_map */
|
||||
|
||||
/*====================================================================*/
|
||||
|
||||
int i82365_init (void)
|
||||
{
|
||||
u_int val;
|
||||
int i;
|
||||
|
||||
if ((socket.dev = pci_find_devices (supported, 0)) < 0) {
|
||||
/* Controller not found */
|
||||
return 1;
|
||||
}
|
||||
|
||||
pci_read_config_dword (socket.dev, PCI_BASE_ADDRESS_0, &socket.cb_phys);
|
||||
socket.cb_phys &= ~0xf;
|
||||
|
||||
get_bridge_state (&socket);
|
||||
set_bridge_opts (&socket);
|
||||
|
||||
i365_get_status (&socket, &val);
|
||||
|
||||
if (val & SS_DETECT) {
|
||||
if (val & SS_3VCARD) {
|
||||
state.Vcc = state.Vpp = 33;
|
||||
puts (" 3.3V card found: ");
|
||||
} else if (!(val & SS_XVCARD)) {
|
||||
state.Vcc = state.Vpp = 50;
|
||||
puts (" 5.0V card found: ");
|
||||
} else {
|
||||
printf ("i82365: unsupported voltage key\n");
|
||||
state.Vcc = state.Vpp = 0;
|
||||
}
|
||||
} else {
|
||||
/* No card inserted */
|
||||
return 1;
|
||||
}
|
||||
|
||||
state.flags = SS_IOCARD | SS_OUTPUT_ENA;
|
||||
state.csc_mask = 0;
|
||||
state.io_irq = 0;
|
||||
|
||||
i365_set_socket (&socket, &state);
|
||||
|
||||
for (i = 500; i; i--) {
|
||||
if ((i365_get (&socket, I365_STATUS) & I365_CS_READY))
|
||||
break;
|
||||
udelay (1000);
|
||||
}
|
||||
|
||||
if (i == 0) {
|
||||
/* PC Card not ready for data transfer */
|
||||
return 1;
|
||||
}
|
||||
|
||||
mem.map = 0;
|
||||
mem.flags = MAP_ATTRIB | MAP_ACTIVE;
|
||||
mem.speed = 300;
|
||||
mem.sys_start = CFG_PCMCIA_MEM_ADDR;
|
||||
mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
|
||||
mem.card_start = 0;
|
||||
|
||||
i365_set_mem_map (&socket, &mem);
|
||||
|
||||
io.map = 0;
|
||||
io.flags = MAP_AUTOSZ | MAP_ACTIVE;
|
||||
io.speed = 0;
|
||||
io.start = 0x0100;
|
||||
io.stop = 0x010F;
|
||||
|
||||
i365_set_io_map (&socket, &io);
|
||||
|
||||
#ifdef DEBUG
|
||||
i82365_dump_regions (socket.dev);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i82365_exit (void)
|
||||
{
|
||||
io.map = 0;
|
||||
io.flags = 0;
|
||||
io.speed = 0;
|
||||
io.start = 0;
|
||||
io.stop = 0x1;
|
||||
|
||||
i365_set_io_map (&socket, &io);
|
||||
|
||||
mem.map = 0;
|
||||
mem.flags = 0;
|
||||
mem.speed = 0;
|
||||
mem.sys_start = 0;
|
||||
mem.sys_stop = 0x1000;
|
||||
mem.card_start = 0;
|
||||
|
||||
i365_set_mem_map (&socket, &mem);
|
||||
|
||||
socket.state.sysctl &= 0xFFFF00FF;
|
||||
|
||||
state.Vcc = state.Vpp = 0;
|
||||
|
||||
i365_set_socket (&socket, &state);
|
||||
}
|
||||
|
||||
/*======================================================================
|
||||
|
||||
Debug stuff
|
||||
|
||||
======================================================================*/
|
||||
|
||||
#ifdef DEBUG
|
||||
static void i82365_dump_regions (pci_dev_t dev)
|
||||
{
|
||||
u_int tmp[2];
|
||||
u_int *mem = (void *) sock.cb_phys;
|
||||
u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
|
||||
u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
|
||||
|
||||
pci_read_config_dword (dev, 0x00, tmp + 0);
|
||||
pci_read_config_dword (dev, 0x80, tmp + 1);
|
||||
|
||||
printf ("PCI CONF: %08X ... %08X\n", tmp[0], tmp[1]);
|
||||
printf ("PCI MEM: ... %08X ... %08X\n", mem[0x8 / 4], mem[0x800 / 4]);
|
||||
printf ("CIS: ...%c%c%c%c%c%c%c%c...\n",
|
||||
cis[0x38], cis[0x3a], cis[0x3c], cis[0x3e],
|
||||
cis[0x40], cis[0x42], cis[0x44], cis[0x48]);
|
||||
printf ("CIS CONF: %02X %02X %02X ...\n",
|
||||
cis[0x200], cis[0x202], cis[0x204]);
|
||||
printf ("IDE: %02X %02X %02X %02X %02X %02X %02X %02X\n",
|
||||
ide[0], ide[1], ide[2], ide[3],
|
||||
ide[4], ide[5], ide[6], ide[7]);
|
||||
}
|
||||
#endif /* DEBUG */
|
||||
|
||||
#endif /* CONFIG_I82365 */
|
||||
@ -21,7 +21,7 @@
|
||||
#define cfg_read(val, addr, type, op) *val = op((type)(addr))
|
||||
#define cfg_write(val, addr, type, op) op((type *)(addr), (val))
|
||||
|
||||
#ifdef CONFIG_PM826
|
||||
#if defined(CONFIG_PM826) || defined(CONFIG_ATC)
|
||||
#define INDIRECT_PCI_OP(rw, size, type, op, mask) \
|
||||
static int \
|
||||
indirect_##rw##_config_##size(struct pci_controller *hose, \
|
||||
|
||||
@ -92,6 +92,7 @@
|
||||
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
|
||||
CFG_CMD_ASKENV | \
|
||||
CFG_CMD_DHCP | \
|
||||
CFG_CMD_ELF | \
|
||||
CFG_CMD_IDE | \
|
||||
CFG_CMD_DATE )
|
||||
|
||||
|
||||
@ -125,7 +125,12 @@
|
||||
|
||||
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
|
||||
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | CFG_CMD_EEPROM)
|
||||
#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
|
||||
CFG_CMD_EEPROM | \
|
||||
CFG_CMD_PCI | \
|
||||
CFG_CMD_PCMCIA | \
|
||||
CFG_CMD_IDE)
|
||||
#define CONFIG_DOS_PARTITION
|
||||
|
||||
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
|
||||
#include <cmd_confdefs.h>
|
||||
@ -149,6 +154,8 @@
|
||||
|
||||
#define CFG_LOAD_ADDR 0x100000 /* default load address */
|
||||
|
||||
#define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
|
||||
|
||||
#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
|
||||
|
||||
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
|
||||
@ -239,6 +246,9 @@
|
||||
# define CFG_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI
|
||||
#define CONFIG_PCI_PNP
|
||||
|
||||
#if 1
|
||||
/* environment is in Flash */
|
||||
#define CFG_ENV_IS_IN_FLASH 1
|
||||
@ -441,4 +451,41 @@
|
||||
#define CFG_PSDMR CFG_PSDMR_8COL
|
||||
#endif /* CFG_RAMBOOT */
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* PCMCIA stuff
|
||||
*-----------------------------------------------------------------------
|
||||
*
|
||||
*/
|
||||
#define CONFIG_I82365
|
||||
|
||||
#define CFG_PCMCIA_MEM_ADDR 0x81000000
|
||||
#define CFG_PCMCIA_MEM_SIZE 0x1000
|
||||
|
||||
/*-----------------------------------------------------------------------
|
||||
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
|
||||
*-----------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
|
||||
|
||||
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
|
||||
#undef CONFIG_IDE_LED /* LED for ide not supported */
|
||||
#undef CONFIG_IDE_RESET /* reset for ide not supported */
|
||||
|
||||
#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
|
||||
#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
|
||||
|
||||
#define CFG_ATA_IDE0_OFFSET 0x0000
|
||||
|
||||
#define CFG_ATA_BASE_ADDR 0xa0000000
|
||||
|
||||
/* Offset for data I/O */
|
||||
#define CFG_ATA_DATA_OFFSET 0x100
|
||||
|
||||
/* Offset for normal register accesses */
|
||||
#define CFG_ATA_REG_OFFSET 0x100
|
||||
|
||||
/* Offset for alternate registers */
|
||||
#define CFG_ATA_ALT_OFFSET 0x108
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
|
||||
@ -439,6 +439,7 @@
|
||||
#define PCI_DEVICE_ID_TI_1211 0xac1e
|
||||
#define PCI_DEVICE_ID_TI_1251B 0xac1f
|
||||
#define PCI_DEVICE_ID_TI_1420 0xac51
|
||||
#define PCI_DEVICE_ID_TI_1510 0xac56
|
||||
|
||||
#define PCI_VENDOR_ID_SONY 0x104d
|
||||
#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
|
||||
|
||||
@ -62,6 +62,8 @@
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#elif defined(CONFIG_R360MPI) /* The R360MPI use SLOT_B */
|
||||
# define CONFIG_PCMCIA_SLOT_B
|
||||
#elif defined(CONFIG_ATC) /* The ATC use SLOT_A */
|
||||
# define CONFIG_PCMCIA_SLOT_A
|
||||
#else
|
||||
# error "PCMCIA Slot not configured"
|
||||
#endif
|
||||
|
||||
154
include/pcmcia/i82365.h
Normal file
154
include/pcmcia/i82365.h
Normal file
@ -0,0 +1,154 @@
|
||||
/*
|
||||
* i82365.h 1.21 2001/08/24 12:15:33
|
||||
*
|
||||
* The contents of this file are subject to the Mozilla Public License
|
||||
* Version 1.1 (the "License"); you may not use this file except in
|
||||
* compliance with the License. You may obtain a copy of the License
|
||||
* at http://www.mozilla.org/MPL/
|
||||
*
|
||||
* Software distributed under the License is distributed on an "AS IS"
|
||||
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
|
||||
* the License for the specific language governing rights and
|
||||
* limitations under the License.
|
||||
*
|
||||
* The initial developer of the original code is David A. Hinds
|
||||
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
|
||||
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the
|
||||
* terms of the GNU General Public License version 2 (the "GPL"), in
|
||||
* which case the provisions of the GPL are applicable instead of the
|
||||
* above. If you wish to allow the use of your version of this file
|
||||
* only under the terms of the GPL and not to allow others to use
|
||||
* your version of this file under the MPL, indicate your decision by
|
||||
* deleting the provisions above and replace them with the notice and
|
||||
* other provisions required by the GPL. If you do not delete the
|
||||
* provisions above, a recipient may use your version of this file
|
||||
* under either the MPL or the GPL.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_I82365_H
|
||||
#define _LINUX_I82365_H
|
||||
|
||||
/* register definitions for the Intel 82365SL PCMCIA controller */
|
||||
|
||||
/* Offsets for PCIC registers */
|
||||
#define I365_IDENT 0x00 /* Identification and revision */
|
||||
#define I365_STATUS 0x01 /* Interface status */
|
||||
#define I365_POWER 0x02 /* Power and RESETDRV control */
|
||||
#define I365_INTCTL 0x03 /* Interrupt and general control */
|
||||
#define I365_CSC 0x04 /* Card status change */
|
||||
#define I365_CSCINT 0x05 /* Card status change interrupt control */
|
||||
#define I365_ADDRWIN 0x06 /* Address window enable */
|
||||
#define I365_IOCTL 0x07 /* I/O control */
|
||||
#define I365_GENCTL 0x16 /* Card detect and general control */
|
||||
#define I365_GBLCTL 0x1E /* Global control register */
|
||||
|
||||
/* Offsets for I/O and memory window registers */
|
||||
#define I365_IO(map) (0x08+((map)<<2))
|
||||
#define I365_MEM(map) (0x10+((map)<<3))
|
||||
#define I365_W_START 0
|
||||
#define I365_W_STOP 2
|
||||
#define I365_W_OFF 4
|
||||
|
||||
/* Flags for I365_STATUS */
|
||||
#define I365_CS_BVD1 0x01
|
||||
#define I365_CS_STSCHG 0x01
|
||||
#define I365_CS_BVD2 0x02
|
||||
#define I365_CS_SPKR 0x02
|
||||
#define I365_CS_DETECT 0x0C
|
||||
#define I365_CS_WRPROT 0x10
|
||||
#define I365_CS_READY 0x20 /* Inverted */
|
||||
#define I365_CS_POWERON 0x40
|
||||
#define I365_CS_GPI 0x80
|
||||
|
||||
/* Flags for I365_POWER */
|
||||
#define I365_PWR_OFF 0x00 /* Turn off the socket */
|
||||
#define I365_PWR_OUT 0x80 /* Output enable */
|
||||
#define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */
|
||||
#define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */
|
||||
#define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */
|
||||
/* There are different layouts for B-step and DF-step chips: the B
|
||||
step has independent Vpp1/Vpp2 control, and the DF step has only
|
||||
Vpp1 control, plus 3V control */
|
||||
#define I365_VCC_5V 0x10 /* Vcc = 5.0v */
|
||||
#define I365_VCC_3V 0x18 /* Vcc = 3.3v */
|
||||
#define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */
|
||||
#define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */
|
||||
#define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */
|
||||
#define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */
|
||||
#define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */
|
||||
#define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */
|
||||
|
||||
/* Flags for I365_INTCTL */
|
||||
#define I365_RING_ENA 0x80
|
||||
#define I365_PC_RESET 0x40
|
||||
#define I365_PC_IOCARD 0x20
|
||||
#define I365_INTR_ENA 0x10
|
||||
#define I365_IRQ_MASK 0x0F
|
||||
|
||||
/* Flags for I365_CSC and I365_CSCINT*/
|
||||
#define I365_CSC_BVD1 0x01
|
||||
#define I365_CSC_STSCHG 0x01
|
||||
#define I365_CSC_BVD2 0x02
|
||||
#define I365_CSC_READY 0x04
|
||||
#define I365_CSC_DETECT 0x08
|
||||
#define I365_CSC_ANY 0x0F
|
||||
#define I365_CSC_GPI 0x10
|
||||
|
||||
/* Flags for I365_ADDRWIN */
|
||||
#define I365_ADDR_MEMCS16 0x20
|
||||
#define I365_ENA_IO(map) (0x40 << (map))
|
||||
#define I365_ENA_MEM(map) (0x01 << (map))
|
||||
|
||||
/* Flags for I365_IOCTL */
|
||||
#define I365_IOCTL_MASK(map) (0x0F << (map<<2))
|
||||
#define I365_IOCTL_WAIT(map) (0x08 << (map<<2))
|
||||
#define I365_IOCTL_0WS(map) (0x04 << (map<<2))
|
||||
#define I365_IOCTL_IOCS16(map) (0x02 << (map<<2))
|
||||
#define I365_IOCTL_16BIT(map) (0x01 << (map<<2))
|
||||
|
||||
/* Flags for I365_GENCTL */
|
||||
#define I365_CTL_16DELAY 0x01
|
||||
#define I365_CTL_RESET 0x02
|
||||
#define I365_CTL_GPI_ENA 0x04
|
||||
#define I365_CTL_GPI_CTL 0x08
|
||||
#define I365_CTL_RESUME 0x10
|
||||
#define I365_CTL_SW_IRQ 0x20
|
||||
|
||||
/* Flags for I365_GBLCTL */
|
||||
#define I365_GBL_PWRDOWN 0x01
|
||||
#define I365_GBL_CSC_LEV 0x02
|
||||
#define I365_GBL_WRBACK 0x04
|
||||
#define I365_GBL_IRQ_0_LEV 0x08
|
||||
#define I365_GBL_IRQ_1_LEV 0x10
|
||||
|
||||
/* Flags for memory window registers */
|
||||
#define I365_MEM_16BIT 0x8000 /* In memory start high byte */
|
||||
#define I365_MEM_0WS 0x4000
|
||||
#define I365_MEM_WS1 0x8000 /* In memory stop high byte */
|
||||
#define I365_MEM_WS0 0x4000
|
||||
#define I365_MEM_WRPROT 0x8000 /* In offset high byte */
|
||||
#define I365_MEM_REG 0x4000
|
||||
|
||||
#define I365_REG(slot, reg) (((slot) << 6) | (reg))
|
||||
|
||||
/* Default ISA interrupt mask */
|
||||
#define I365_ISA_IRQ_MASK 0xdeb8 /* irq's 3-5,7,9-12,14,15 */
|
||||
|
||||
/* Device ID's for PCI-to-PCMCIA bridges */
|
||||
|
||||
#ifndef PCI_VENDOR_ID_INTEL
|
||||
#define PCI_VENDOR_ID_INTEL 0x8086
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_INTEL_82092AA_0
|
||||
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
|
||||
#endif
|
||||
#ifndef PCI_VENDOR_ID_OMEGA
|
||||
#define PCI_VENDOR_ID_OMEGA 0x119b
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_OMEGA_82C092G
|
||||
#define PCI_DEVICE_ID_OMEGA_82C092G 0x1221
|
||||
#endif
|
||||
|
||||
#endif /* _LINUX_I82365_H */
|
||||
133
include/pcmcia/ss.h
Normal file
133
include/pcmcia/ss.h
Normal file
@ -0,0 +1,133 @@
|
||||
/*
|
||||
* ss.h 1.31 2001/08/24 12:16:13
|
||||
*
|
||||
* The contents of this file are subject to the Mozilla Public License
|
||||
* Version 1.1 (the "License"); you may not use this file except in
|
||||
* compliance with the License. You may obtain a copy of the License
|
||||
* at http://www.mozilla.org/MPL/
|
||||
*
|
||||
* Software distributed under the License is distributed on an "AS IS"
|
||||
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
|
||||
* the License for the specific language governing rights and
|
||||
* limitations under the License.
|
||||
*
|
||||
* The initial developer of the original code is David A. Hinds
|
||||
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
|
||||
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the
|
||||
* terms of the GNU General Public License version 2 (the "GPL"), in
|
||||
* which case the provisions of the GPL are applicable instead of the
|
||||
* above. If you wish to allow the use of your version of this file
|
||||
* only under the terms of the GPL and not to allow others to use
|
||||
* your version of this file under the MPL, indicate your decision by
|
||||
* deleting the provisions above and replace them with the notice and
|
||||
* other provisions required by the GPL. If you do not delete the
|
||||
* provisions above, a recipient may use your version of this file
|
||||
* under either the MPL or the GPL.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_SS_H
|
||||
#define _LINUX_SS_H
|
||||
|
||||
/* For RegisterCallback */
|
||||
typedef struct ss_callback_t {
|
||||
void (*handler)(void *info, u_int events);
|
||||
void *info;
|
||||
} ss_callback_t;
|
||||
|
||||
/* Definitions for card status flags for GetStatus */
|
||||
#define SS_WRPROT 0x0001
|
||||
#define SS_CARDLOCK 0x0002
|
||||
#define SS_EJECTION 0x0004
|
||||
#define SS_INSERTION 0x0008
|
||||
#define SS_BATDEAD 0x0010
|
||||
#define SS_BATWARN 0x0020
|
||||
#define SS_READY 0x0040
|
||||
#define SS_DETECT 0x0080
|
||||
#define SS_POWERON 0x0100
|
||||
#define SS_GPI 0x0200
|
||||
#define SS_STSCHG 0x0400
|
||||
#define SS_CARDBUS 0x0800
|
||||
#define SS_3VCARD 0x1000
|
||||
#define SS_XVCARD 0x2000
|
||||
#define SS_PENDING 0x4000
|
||||
|
||||
/* for InquireSocket */
|
||||
typedef struct socket_cap_t {
|
||||
u_int features;
|
||||
u_int irq_mask;
|
||||
u_int map_size;
|
||||
u_char pci_irq;
|
||||
u_char cardbus;
|
||||
struct pci_bus *cb_bus;
|
||||
struct bus_operations *bus;
|
||||
} socket_cap_t;
|
||||
|
||||
/* InquireSocket capabilities */
|
||||
#define SS_CAP_PAGE_REGS 0x0001
|
||||
#define SS_CAP_VIRTUAL_BUS 0x0002
|
||||
#define SS_CAP_MEM_ALIGN 0x0004
|
||||
#define SS_CAP_STATIC_MAP 0x0008
|
||||
#define SS_CAP_PCCARD 0x4000
|
||||
#define SS_CAP_CARDBUS 0x8000
|
||||
|
||||
/* for GetSocket, SetSocket */
|
||||
typedef struct socket_state_t {
|
||||
u_int flags;
|
||||
u_int csc_mask;
|
||||
u_char Vcc, Vpp;
|
||||
u_char io_irq;
|
||||
} socket_state_t;
|
||||
|
||||
/* Socket configuration flags */
|
||||
#define SS_PWR_AUTO 0x0010
|
||||
#define SS_IOCARD 0x0020
|
||||
#define SS_RESET 0x0040
|
||||
#define SS_DMA_MODE 0x0080
|
||||
#define SS_SPKR_ENA 0x0100
|
||||
#define SS_OUTPUT_ENA 0x0200
|
||||
#define SS_ZVCARD 0x0400
|
||||
|
||||
/* Flags for I/O port and memory windows */
|
||||
#define MAP_ACTIVE 0x01
|
||||
#define MAP_16BIT 0x02
|
||||
#define MAP_AUTOSZ 0x04
|
||||
#define MAP_0WS 0x08
|
||||
#define MAP_WRPROT 0x10
|
||||
#define MAP_ATTRIB 0x20
|
||||
#define MAP_USE_WAIT 0x40
|
||||
#define MAP_PREFETCH 0x80
|
||||
|
||||
/* Use this just for bridge windows */
|
||||
#define MAP_IOSPACE 0x20
|
||||
|
||||
typedef struct pccard_io_map {
|
||||
u_char map;
|
||||
u_char flags;
|
||||
u_short speed;
|
||||
u_short start, stop;
|
||||
} pccard_io_map;
|
||||
|
||||
typedef struct pccard_mem_map {
|
||||
u_char map;
|
||||
u_char flags;
|
||||
u_short speed;
|
||||
u_long sys_start, sys_stop;
|
||||
u_int card_start;
|
||||
} pccard_mem_map;
|
||||
|
||||
typedef struct cb_bridge_map {
|
||||
u_char map;
|
||||
u_char flags;
|
||||
u_int start, stop;
|
||||
} cb_bridge_map;
|
||||
|
||||
enum ss_service {
|
||||
SS_RegisterCallback, SS_InquireSocket,
|
||||
SS_GetStatus, SS_GetSocket, SS_SetSocket,
|
||||
SS_GetIOMap, SS_SetIOMap, SS_GetMemMap, SS_SetMemMap,
|
||||
SS_GetBridge, SS_SetBridge, SS_ProcSetup
|
||||
};
|
||||
|
||||
#endif /* _LINUX_SS_H */
|
||||
234
include/pcmcia/ti113x.h
Normal file
234
include/pcmcia/ti113x.h
Normal file
@ -0,0 +1,234 @@
|
||||
/*
|
||||
* ti113x.h 1.31 2002/05/12 18:19:47
|
||||
*
|
||||
* The contents of this file are subject to the Mozilla Public License
|
||||
* Version 1.1 (the "License"); you may not use this file except in
|
||||
* compliance with the License. You may obtain a copy of the License
|
||||
* at http://www.mozilla.org/MPL/
|
||||
*
|
||||
* Software distributed under the License is distributed on an "AS IS"
|
||||
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
|
||||
* the License for the specific language governing rights and
|
||||
* limitations under the License.
|
||||
*
|
||||
* The initial developer of the original code is David A. Hinds
|
||||
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
|
||||
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the
|
||||
* terms of the GNU General Public License version 2 (the "GPL"), in
|
||||
* which case the provisions of the GPL are applicable instead of the
|
||||
* above. If you wish to allow the use of your version of this file
|
||||
* only under the terms of the GPL and not to allow others to use
|
||||
* your version of this file under the MPL, indicate your decision by
|
||||
* deleting the provisions above and replace them with the notice and
|
||||
* other provisions required by the GPL. If you do not delete the
|
||||
* provisions above, a recipient may use your version of this file
|
||||
* under either the MPL or the GPL.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_TI113X_H
|
||||
#define _LINUX_TI113X_H
|
||||
|
||||
#ifndef PCI_VENDOR_ID_TI
|
||||
#define PCI_VENDOR_ID_TI 0x104c
|
||||
#endif
|
||||
|
||||
#ifndef PCI_DEVICE_ID_TI_1130
|
||||
#define PCI_DEVICE_ID_TI_1130 0xac12
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1031
|
||||
#define PCI_DEVICE_ID_TI_1031 0xac13
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1131
|
||||
#define PCI_DEVICE_ID_TI_1131 0xac15
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1210
|
||||
#define PCI_DEVICE_ID_TI_1210 0xac1a
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1211
|
||||
#define PCI_DEVICE_ID_TI_1211 0xac1e
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1220
|
||||
#define PCI_DEVICE_ID_TI_1220 0xac17
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1221
|
||||
#define PCI_DEVICE_ID_TI_1221 0xac19
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1250A
|
||||
#define PCI_DEVICE_ID_TI_1250A 0xac16
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1225
|
||||
#define PCI_DEVICE_ID_TI_1225 0xac1c
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1251A
|
||||
#define PCI_DEVICE_ID_TI_1251A 0xac1d
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1251B
|
||||
#define PCI_DEVICE_ID_TI_1251B 0xac1f
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1410
|
||||
#define PCI_DEVICE_ID_TI_1410 0xac50
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1420
|
||||
#define PCI_DEVICE_ID_TI_1420 0xac51
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1450
|
||||
#define PCI_DEVICE_ID_TI_1450 0xac1b
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1451
|
||||
#define PCI_DEVICE_ID_TI_1451 0xac52
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_1510
|
||||
#define PCI_DEVICE_ID_TI_1510 0xac56
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_4410
|
||||
#define PCI_DEVICE_ID_TI_4410 0xac41
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_4450
|
||||
#define PCI_DEVICE_ID_TI_4450 0xac40
|
||||
#endif
|
||||
#ifndef PCI_DEVICE_ID_TI_4451
|
||||
#define PCI_DEVICE_ID_TI_4451 0xac42
|
||||
#endif
|
||||
|
||||
/* Register definitions for TI 113X PCI-to-CardBus bridges */
|
||||
|
||||
/* System Control Register */
|
||||
#define TI113X_SYSTEM_CONTROL 0x80 /* 32 bit */
|
||||
#define TI113X_SCR_SMIROUTE 0x04000000
|
||||
#define TI113X_SCR_SMISTATUS 0x02000000
|
||||
#define TI113X_SCR_SMIENB 0x01000000
|
||||
#define TI113X_SCR_VCCPROT 0x00200000
|
||||
#define TI113X_SCR_REDUCEZV 0x00100000
|
||||
#define TI113X_SCR_CDREQEN 0x00080000
|
||||
#define TI113X_SCR_CDMACHAN 0x00070000
|
||||
#define TI113X_SCR_SOCACTIVE 0x00002000
|
||||
#define TI113X_SCR_PWRSTREAM 0x00000800
|
||||
#define TI113X_SCR_DELAYUP 0x00000400
|
||||
#define TI113X_SCR_DELAYDOWN 0x00000200
|
||||
#define TI113X_SCR_INTERROGATE 0x00000100
|
||||
#define TI113X_SCR_CLKRUN_SEL 0x00000080
|
||||
#define TI113X_SCR_PWRSAVINGS 0x00000040
|
||||
#define TI113X_SCR_SUBSYSRW 0x00000020
|
||||
#define TI113X_SCR_CB_DPAR 0x00000010
|
||||
#define TI113X_SCR_CDMA_EN 0x00000008
|
||||
#define TI113X_SCR_ASYNC_IRQ 0x00000004
|
||||
#define TI113X_SCR_KEEPCLK 0x00000002
|
||||
#define TI113X_SCR_CLKRUN_ENA 0x00000001
|
||||
|
||||
#define TI122X_SCR_SER_STEP 0xc0000000
|
||||
#define TI122X_SCR_INTRTIE 0x20000000
|
||||
#define TI122X_SCR_P2CCLK 0x08000000
|
||||
#define TI122X_SCR_CBRSVD 0x00400000
|
||||
#define TI122X_SCR_MRBURSTDN 0x00008000
|
||||
#define TI122X_SCR_MRBURSTUP 0x00004000
|
||||
#define TI122X_SCR_RIMUX 0x00000001
|
||||
|
||||
/* Multimedia Control Register */
|
||||
#define TI1250_MULTIMEDIA_CTL 0x84 /* 8 bit */
|
||||
#define TI1250_MMC_ZVOUTEN 0x80
|
||||
#define TI1250_MMC_PORTSEL 0x40
|
||||
#define TI1250_MMC_ZVEN1 0x02
|
||||
#define TI1250_MMC_ZVEN0 0x01
|
||||
|
||||
#define TI1250_GENERAL_STATUS 0x85 /* 8 bit */
|
||||
#define TI1250_GPIO0_CONTROL 0x88 /* 8 bit */
|
||||
#define TI1250_GPIO1_CONTROL 0x89 /* 8 bit */
|
||||
#define TI1250_GPIO2_CONTROL 0x8a /* 8 bit */
|
||||
#define TI1250_GPIO3_CONTROL 0x8b /* 8 bit */
|
||||
#define TI12XX_IRQMUX 0x8c /* 32 bit */
|
||||
|
||||
/* Retry Status Register */
|
||||
#define TI113X_RETRY_STATUS 0x90 /* 8 bit */
|
||||
#define TI113X_RSR_PCIRETRY 0x80
|
||||
#define TI113X_RSR_CBRETRY 0x40
|
||||
#define TI113X_RSR_TEXP_CBB 0x20
|
||||
#define TI113X_RSR_MEXP_CBB 0x10
|
||||
#define TI113X_RSR_TEXP_CBA 0x08
|
||||
#define TI113X_RSR_MEXP_CBA 0x04
|
||||
#define TI113X_RSR_TEXP_PCI 0x02
|
||||
#define TI113X_RSR_MEXP_PCI 0x01
|
||||
|
||||
/* Card Control Register */
|
||||
#define TI113X_CARD_CONTROL 0x91 /* 8 bit */
|
||||
#define TI113X_CCR_RIENB 0x80
|
||||
#define TI113X_CCR_ZVENABLE 0x40
|
||||
#define TI113X_CCR_PCI_IRQ_ENA 0x20
|
||||
#define TI113X_CCR_PCI_IREQ 0x10
|
||||
#define TI113X_CCR_PCI_CSC 0x08
|
||||
#define TI113X_CCR_SPKROUTEN 0x02
|
||||
#define TI113X_CCR_IFG 0x01
|
||||
|
||||
#define TI1220_CCR_PORT_SEL 0x20
|
||||
#define TI122X_CCR_AUD2MUX 0x04
|
||||
|
||||
/* Device Control Register */
|
||||
#define TI113X_DEVICE_CONTROL 0x92 /* 8 bit */
|
||||
#define TI113X_DCR_5V_FORCE 0x40
|
||||
#define TI113X_DCR_3V_FORCE 0x20
|
||||
#define TI113X_DCR_IMODE_MASK 0x06
|
||||
#define TI113X_DCR_IMODE_ISA 0x02
|
||||
#define TI113X_DCR_IMODE_SERIAL 0x04
|
||||
|
||||
#define TI12XX_DCR_IMODE_PCI_ONLY 0x00
|
||||
#define TI12XX_DCR_IMODE_ALL_SERIAL 0x06
|
||||
|
||||
/* Buffer Control Register */
|
||||
#define TI113X_BUFFER_CONTROL 0x93 /* 8 bit */
|
||||
#define TI113X_BCR_CB_READ_DEPTH 0x08
|
||||
#define TI113X_BCR_CB_WRITE_DEPTH 0x04
|
||||
#define TI113X_BCR_PCI_READ_DEPTH 0x02
|
||||
#define TI113X_BCR_PCI_WRITE_DEPTH 0x01
|
||||
|
||||
/* Diagnostic Register */
|
||||
#define TI1250_DIAGNOSTIC 0x93 /* 8 bit */
|
||||
#define TI1250_DIAG_TRUE_VALUE 0x80
|
||||
#define TI1250_DIAG_PCI_IREQ 0x40
|
||||
#define TI1250_DIAG_PCI_CSC 0x20
|
||||
#define TI1250_DIAG_ASYNC_CSC 0x01
|
||||
|
||||
/* DMA Registers */
|
||||
#define TI113X_DMA_0 0x94 /* 32 bit */
|
||||
#define TI113X_DMA_1 0x98 /* 32 bit */
|
||||
|
||||
/* ExCA IO offset registers */
|
||||
#define TI113X_IO_OFFSET(map) (0x36+((map)<<1))
|
||||
|
||||
/* Data structure for tracking vendor-specific state */
|
||||
typedef struct ti113x_state_t {
|
||||
u32 sysctl; /* TI113X_SYSTEM_CONTROL */
|
||||
u8 cardctl; /* TI113X_CARD_CONTROL */
|
||||
u8 devctl; /* TI113X_DEVICE_CONTROL */
|
||||
u8 diag; /* TI1250_DIAGNOSTIC */
|
||||
u32 irqmux; /* TI12XX_IRQMUX */
|
||||
} ti113x_state_t;
|
||||
|
||||
#define TI_PCIC_ID \
|
||||
IS_TI1130, IS_TI1131, IS_TI1031, IS_TI1210, IS_TI1211, \
|
||||
IS_TI1220, IS_TI1221, IS_TI1225, IS_TI1250A, IS_TI1251A, \
|
||||
IS_TI1251B, IS_TI1410, IS_TI1420, IS_TI1450, IS_TI1451, \
|
||||
IS_TI1510, IS_TI4410, IS_TI4450, IS_TI4451
|
||||
|
||||
#define TI_PCIC_INFO \
|
||||
{ "TI 1130", IS_TI|IS_CARDBUS, ID(TI, 1130) }, \
|
||||
{ "TI 1131", IS_TI|IS_CARDBUS, ID(TI, 1131) }, \
|
||||
{ "TI 1031", IS_TI|IS_CARDBUS, ID(TI, 1031) }, \
|
||||
{ "TI 1210", IS_TI|IS_CARDBUS, ID(TI, 1210) }, \
|
||||
{ "TI 1211", IS_TI|IS_CARDBUS, ID(TI, 1211) }, \
|
||||
{ "TI 1220", IS_TI|IS_CARDBUS, ID(TI, 1220) }, \
|
||||
{ "TI 1221", IS_TI|IS_CARDBUS, ID(TI, 1221) }, \
|
||||
{ "TI 1225", IS_TI|IS_CARDBUS, ID(TI, 1225) }, \
|
||||
{ "TI 1250A", IS_TI|IS_CARDBUS, ID(TI, 1250A) }, \
|
||||
{ "TI 1251A", IS_TI|IS_CARDBUS, ID(TI, 1251A) }, \
|
||||
{ "TI 1251B", IS_TI|IS_CARDBUS, ID(TI, 1251B) }, \
|
||||
{ "TI 1410", IS_TI|IS_CARDBUS, ID(TI, 1410) }, \
|
||||
{ "TI 1420", IS_TI|IS_CARDBUS, ID(TI, 1420) }, \
|
||||
{ "TI 1450", IS_TI|IS_CARDBUS, ID(TI, 1450) }, \
|
||||
{ "TI 1451", IS_TI|IS_CARDBUS, ID(TI, 1451) }, \
|
||||
{ "TI 1510", IS_TI|IS_CARDBUS, ID(TI, 1510) }, \
|
||||
{ "TI 4410", IS_TI|IS_CARDBUS, ID(TI, 4410) }, \
|
||||
{ "TI 4450", IS_TI|IS_CARDBUS, ID(TI, 4450) }, \
|
||||
{ "TI 4451", IS_TI|IS_CARDBUS, ID(TI, 4451) }
|
||||
|
||||
#endif /* _LINUX_TI113X_H */
|
||||
156
include/pcmcia/yenta.h
Normal file
156
include/pcmcia/yenta.h
Normal file
@ -0,0 +1,156 @@
|
||||
/*
|
||||
* yenta.h 1.20 2001/08/24 12:15:34
|
||||
*
|
||||
* The contents of this file are subject to the Mozilla Public License
|
||||
* Version 1.1 (the "License"); you may not use this file except in
|
||||
* compliance with the License. You may obtain a copy of the License
|
||||
* at http://www.mozilla.org/MPL/
|
||||
*
|
||||
* Software distributed under the License is distributed on an "AS IS"
|
||||
* basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
|
||||
* the License for the specific language governing rights and
|
||||
* limitations under the License.
|
||||
*
|
||||
* The initial developer of the original code is David A. Hinds
|
||||
* <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
|
||||
* are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
|
||||
*
|
||||
* Alternatively, the contents of this file may be used under the
|
||||
* terms of the GNU General Public License version 2 (the "GPL"), in
|
||||
* which case the provisions of the GPL are applicable instead of the
|
||||
* above. If you wish to allow the use of your version of this file
|
||||
* only under the terms of the GPL and not to allow others to use
|
||||
* your version of this file under the MPL, indicate your decision by
|
||||
* deleting the provisions above and replace them with the notice and
|
||||
* other provisions required by the GPL. If you do not delete the
|
||||
* provisions above, a recipient may use your version of this file
|
||||
* under either the MPL or the GPL.
|
||||
*/
|
||||
|
||||
#ifndef _LINUX_YENTA_H
|
||||
#define _LINUX_YENTA_H
|
||||
|
||||
/* PCI Configuration Registers */
|
||||
|
||||
#define PCI_STATUS_CAPLIST 0x10
|
||||
#define PCI_CB_CAPABILITY_POINTER 0x14 /* 8 bit */
|
||||
#define PCI_CAPABILITY_ID 0x00 /* 8 bit */
|
||||
#define PCI_CAPABILITY_PM 0x01
|
||||
#define PCI_NEXT_CAPABILITY 0x01 /* 8 bit */
|
||||
#define PCI_PM_CAPABILITIES 0x02 /* 16 bit */
|
||||
#define PCI_PMCAP_PME_D3COLD 0x8000
|
||||
#define PCI_PMCAP_PME_D3HOT 0x4000
|
||||
#define PCI_PMCAP_PME_D2 0x2000
|
||||
#define PCI_PMCAP_PME_D1 0x1000
|
||||
#define PCI_PMCAP_PME_D0 0x0800
|
||||
#define PCI_PMCAP_D2_CAP 0x0400
|
||||
#define PCI_PMCAP_D1_CAP 0x0200
|
||||
#define PCI_PMCAP_DYN_DATA 0x0100
|
||||
#define PCI_PMCAP_DSI 0x0020
|
||||
#define PCI_PMCAP_AUX_PWR 0x0010
|
||||
#define PCI_PMCAP_PMECLK 0x0008
|
||||
#define PCI_PMCAP_VERSION_MASK 0x0007
|
||||
#define PCI_PM_CONTROL_STATUS 0x04 /* 16 bit */
|
||||
#define PCI_PMCS_PME_STATUS 0x8000
|
||||
#define PCI_PMCS_DATASCALE_MASK 0x6000
|
||||
#define PCI_PMCS_DATASCALE_SHIFT 13
|
||||
#define PCI_PMCS_DATASEL_MASK 0x1e00
|
||||
#define PCI_PMCS_DATASEL_SHIFT 9
|
||||
#define PCI_PMCS_PME_ENABLE 0x0100
|
||||
#define PCI_PMCS_PWR_STATE_MASK 0x0003
|
||||
#define PCI_PMCS_PWR_STATE_D0 0x0000
|
||||
#define PCI_PMCS_PWR_STATE_D1 0x0001
|
||||
#define PCI_PMCS_PWR_STATE_D2 0x0002
|
||||
#define PCI_PMCS_PWR_STATE_D3 0x0003
|
||||
#define PCI_PM_BRIDGE_EXT 0x06 /* 8 bit */
|
||||
#define PCI_PM_DATA 0x07 /* 8 bit */
|
||||
|
||||
#define CB_PRIMARY_BUS 0x18 /* 8 bit */
|
||||
#define CB_CARDBUS_BUS 0x19 /* 8 bit */
|
||||
#define CB_SUBORD_BUS 0x1a /* 8 bit */
|
||||
#define CB_LATENCY_TIMER 0x1b /* 8 bit */
|
||||
|
||||
#define CB_MEM_BASE(m) (0x1c + 8*(m))
|
||||
#define CB_MEM_LIMIT(m) (0x20 + 8*(m))
|
||||
#define CB_IO_BASE(m) (0x2c + 8*(m))
|
||||
#define CB_IO_LIMIT(m) (0x30 + 8*(m))
|
||||
|
||||
#define CB_BRIDGE_CONTROL 0x3e /* 16 bit */
|
||||
#define CB_BCR_PARITY_ENA 0x0001
|
||||
#define CB_BCR_SERR_ENA 0x0002
|
||||
#define CB_BCR_ISA_ENA 0x0004
|
||||
#define CB_BCR_VGA_ENA 0x0008
|
||||
#define CB_BCR_MABORT 0x0020
|
||||
#define CB_BCR_CB_RESET 0x0040
|
||||
#define CB_BCR_ISA_IRQ 0x0080
|
||||
#define CB_BCR_PREFETCH(m) (0x0100 << (m))
|
||||
#define CB_BCR_WRITE_POST 0x0400
|
||||
|
||||
#define CB_LEGACY_MODE_BASE 0x44
|
||||
|
||||
/* Memory mapped registers */
|
||||
|
||||
#define CB_SOCKET_EVENT 0x0000
|
||||
#define CB_SE_CSTSCHG 0x00000001
|
||||
#define CB_SE_CCD 0x00000006
|
||||
#define CB_SE_CCD1 0x00000002
|
||||
#define CB_SE_CCD2 0x00000004
|
||||
#define CB_SE_PWRCYCLE 0x00000008
|
||||
|
||||
#define CB_SOCKET_MASK 0x0004
|
||||
#define CB_SM_CSTSCHG 0x00000001
|
||||
#define CB_SM_CCD 0x00000006
|
||||
#define CB_SM_PWRCYCLE 0x00000008
|
||||
|
||||
#define CB_SOCKET_STATE 0x0008
|
||||
#define CB_SS_CSTSCHG 0x00000001
|
||||
#define CB_SS_CCD 0x00000006
|
||||
#define CB_SS_CCD1 0x00000002
|
||||
#define CB_SS_CCD2 0x00000004
|
||||
#define CB_SS_PWRCYCLE 0x00000008
|
||||
#define CB_SS_16BIT 0x00000010
|
||||
#define CB_SS_32BIT 0x00000020
|
||||
#define CB_SS_CINT 0x00000040
|
||||
#define CB_SS_BADCARD 0x00000080
|
||||
#define CB_SS_DATALOST 0x00000100
|
||||
#define CB_SS_BADVCC 0x00000200
|
||||
#define CB_SS_5VCARD 0x00000400
|
||||
#define CB_SS_3VCARD 0x00000800
|
||||
#define CB_SS_XVCARD 0x00001000
|
||||
#define CB_SS_YVCARD 0x00002000
|
||||
#define CB_SS_VSENSE 0x00003c86
|
||||
#define CB_SS_5VSOCKET 0x10000000
|
||||
#define CB_SS_3VSOCKET 0x20000000
|
||||
#define CB_SS_XVSOCKET 0x40000000
|
||||
#define CB_SS_YVSOCKET 0x80000000
|
||||
|
||||
#define CB_SOCKET_FORCE 0x000c
|
||||
#define CB_SF_CVSTEST 0x00004000
|
||||
|
||||
#define CB_SOCKET_CONTROL 0x0010
|
||||
#define CB_SC_VPP_MASK 0x00000007
|
||||
#define CB_SC_VPP_OFF 0x00000000
|
||||
#define CB_SC_VPP_12V 0x00000001
|
||||
#define CB_SC_VPP_5V 0x00000002
|
||||
#define CB_SC_VPP_3V 0x00000003
|
||||
#define CB_SC_VPP_XV 0x00000004
|
||||
#define CB_SC_VPP_YV 0x00000005
|
||||
#define CB_SC_VCC_MASK 0x00000070
|
||||
#define CB_SC_VCC_OFF 0x00000000
|
||||
#define CB_SC_VCC_5V 0x00000020
|
||||
#define CB_SC_VCC_3V 0x00000030
|
||||
#define CB_SC_VCC_XV 0x00000040
|
||||
#define CB_SC_VCC_YV 0x00000050
|
||||
#define CB_SC_CCLK_STOP 0x00000080
|
||||
|
||||
#define CB_SOCKET_POWER 0x0020
|
||||
#define CB_SP_CLK_CTRL 0x00000001
|
||||
#define CB_SP_CLK_CTRL_ENA 0x00010000
|
||||
#define CB_SP_CLK_MODE 0x01000000
|
||||
#define CB_SP_ACCESS 0x02000000
|
||||
|
||||
/* Address bits 31..24 for memory windows for 16-bit cards,
|
||||
accessable only by memory mapping the 16-bit register set */
|
||||
#define CB_MEM_PAGE(map) (0x40 + (map))
|
||||
|
||||
#endif /* _LINUX_YENTA_H */
|
||||
Loading…
Reference in New Issue
Block a user