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Merge branch 'zynq' of git://www.denx.de/git/u-boot-microblaze

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This commit is contained in:
Tom Rini 2015-07-28 11:31:21 -04:00
commit 66d10c18bf
32 changed files with 1427 additions and 117 deletions
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2
Kconfig
View File

@ -178,7 +178,7 @@ config SYS_EXTRA_OPTIONS
new boards should not use this option.
config SYS_TEXT_BASE
depends on SPARC || ARC || X86 || ARCH_UNIPHIER
depends on SPARC || ARC || X86 || ARCH_UNIPHIER || ARCH_ZYNQMP
hex "Text Base"
help
TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture

5
arch/arm/Kconfig
View File

@ -681,7 +681,7 @@ config ARCH_ZYNQ
select DM_SPI
select DM_SPI_FLASH
config TARGET_XILINX_ZYNQMP
config ARCH_ZYNQMP
bool "Support Xilinx ZynqMP Platform"
select ARM64
@ -874,6 +874,8 @@ source "arch/arm/mach-zynq/Kconfig"
source "arch/arm/cpu/armv7/Kconfig"
source "arch/arm/cpu/armv8/zynqmp/Kconfig"
source "arch/arm/cpu/armv8/Kconfig"
source "arch/arm/imx-common/Kconfig"
@ -991,7 +993,6 @@ source "board/warp/Kconfig"
source "board/woodburn/Kconfig"
source "board/work-microwave/work_92105/Kconfig"
source "board/xaeniax/Kconfig"
source "board/xilinx/zynqmp/Kconfig"
source "board/zipitz2/Kconfig"
source "arch/arm/Kconfig.debug"

2
arch/arm/cpu/armv8/Makefile
View File

@ -16,4 +16,4 @@ obj-y += tlb.o
obj-y += transition.o
obj-$(CONFIG_FSL_LSCH3) += fsl-lsch3/
obj-$(CONFIG_TARGET_XILINX_ZYNQMP) += zynqmp/
obj-$(CONFIG_ARCH_ZYNQMP) += zynqmp/

23
arch/arm/cpu/armv8/zynqmp/Kconfig Normal file
View File

@ -0,0 +1,23 @@
if ARCH_ZYNQMP
choice
prompt "Xilinx ZynqMP board select"
config TARGET_ZYNQMP_EP
bool "ZynqMP EP Board"
endchoice
config SYS_BOARD
default "zynqmp"
config SYS_VENDOR
default "xilinx"
config SYS_SOC
default "zynqmp"
config SYS_CONFIG_NAME
default "xilinx_zynqmp_ep" if TARGET_ZYNQMP_EP
endif

1
arch/arm/cpu/armv8/zynqmp/Makefile
View File

@ -8,3 +8,4 @@
obj-y += clk.o
obj-y += cpu.o
obj-$(CONFIG_MP) += mp.o
obj-y += slcr.o

7
arch/arm/cpu/armv8/zynqmp/mp.c
View File

@ -216,12 +216,7 @@ int cpu_release(int nr, int argc, char * const argv[])
printf("R5 lockstep mode\n");
set_r5_tcm_mode(LOCK);
set_r5_halt_mode(HALT, LOCK);
if (boot_addr == 0)
set_r5_start(0);
else
set_r5_start(1);
set_r5_start(boot_addr);
enable_clock_r5();
release_r5_reset(LOCK);
set_r5_halt_mode(RELEASE, LOCK);

63
arch/arm/cpu/armv8/zynqmp/slcr.c Normal file
View File

@ -0,0 +1,63 @@
/*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <malloc.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/clk.h>
/*
* zynq_slcr_mio_get_status - Get the status of MIO peripheral.
*
* @peri_name: Name of the peripheral for checking MIO status
* @get_pins: Pointer to array of get pin for this peripheral
* @num_pins: Number of pins for this peripheral
* @mask: Mask value
* @check_val: Required check value to get the status of periph
*/
struct zynq_slcr_mio_get_status {
const char *peri_name;
const int *get_pins;
int num_pins;
u32 mask;
u32 check_val;
};
static const struct zynq_slcr_mio_get_status mio_periphs[] = {
};
/*
* zynq_slcr_get_mio_pin_status - Get the MIO pin status of peripheral.
*
* @periph: Name of the peripheral
*
* Returns count to indicate the number of pins configured for the
* given @periph.
*/
int zynq_slcr_get_mio_pin_status(const char *periph)
{
const struct zynq_slcr_mio_get_status *mio_ptr;
int val, i, j;
int mio = 0;
for (i = 0; i < ARRAY_SIZE(mio_periphs); i++) {
if (strcmp(periph, mio_periphs[i].peri_name) == 0) {
mio_ptr = &mio_periphs[i];
for (j = 0; j < mio_ptr->num_pins; j++) {
val = readl(&slcr_base->mio_pin
[mio_ptr->get_pins[j]]);
if ((val & mio_ptr->mask) == mio_ptr->check_val)
mio++;
}
break;
}
}
return mio;
}

1
arch/arm/dts/Makefile
View File

@ -45,6 +45,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += zynq-zc702.dtb \
zynq-microzed.dtb \
zynq-picozed.dtb \
zynq-zc770-xm010.dtb \
zynq-zc770-xm011.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb

174
arch/arm/dts/zynq-7000.dtsi
View File

@ -2,7 +2,7 @@
* Xilinx Zynq 7000 DTSI
* Describes the hardware common to all Zynq 7000-based boards.
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2011 - 2015 Xilinx
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -21,11 +21,11 @@
reg = <0>;
clocks = <&clkc 3>;
clock-latency = <1000>;
cpu0-supply = <&regulator_vccpint>;
operating-points = <
/* kHz uV */
666667 1000000
333334 1000000
222223 1000000
>;
};
@ -44,14 +44,65 @@
reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
};
amba {
regulator_vccpint: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "VCCPINT";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-boot-on;
regulator-always-on;
};
amba: amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
ranges;
i2c0: zynq-i2c@e0004000 {
adc: adc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&intc>;
clocks = <&clkc 12>;
};
can0: can@e0008000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 19>, <&clkc 36>;
clock-names = "can_clk", "pclk";
reg = <0xe0008000 0x1000>;
interrupts = <0 28 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
can1: can@e0009000 {
compatible = "xlnx,zynq-can-1.0";
status = "disabled";
clocks = <&clkc 20>, <&clkc 37>;
clock-names = "can_clk", "pclk";
reg = <0xe0009000 0x1000>;
interrupts = <0 51 4>;
interrupt-parent = <&intc>;
tx-fifo-depth = <0x40>;
rx-fifo-depth = <0x40>;
};
gpio0: gpio@e000a000 {
compatible = "xlnx,zynq-gpio-1.0";
#gpio-cells = <2>;
clocks = <&clkc 42>;
gpio-controller;
interrupt-parent = <&intc>;
interrupts = <0 20 4>;
reg = <0xe000a000 0x1000>;
};
i2c0: i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 38>;
@ -62,7 +113,7 @@
#size-cells = <0>;
};
i2c1: zynq-i2c@e0005000 {
i2c1: i2c@e0005000 {
compatible = "cdns,i2c-r1p10";
status = "disabled";
clocks = <&clkc 39>;
@ -76,41 +127,46 @@
intc: interrupt-controller@f8f01000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <1>;
interrupt-controller;
reg = <0xF8F01000 0x1000>,
<0xF8F00100 0x100>;
};
L2: cache-controller {
L2: cache-controller@f8f02000 {
compatible = "arm,pl310-cache";
reg = <0xF8F02000 0x1000>;
interrupts = <0 2 4>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
cache-unified;
cache-level = <2>;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
mc: memory-controller@f8006000 {
compatible = "xlnx,zynq-ddrc-a05";
reg = <0xf8006000 0x1000>;
};
uart0: serial@e0000000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
clock-names = "ref_clk", "aper_clk";
clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};
uart1: uart@e0001000 {
compatible = "xlnx,xuartps";
uart1: serial@e0001000 {
compatible = "xlnx,xuartps", "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
clock-names = "ref_clk", "aper_clk";
clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
};
spi0: spi@e0006000 {
compatible = "xlnx,zynq-spi";
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
@ -123,7 +179,7 @@
};
spi1: spi@e0007000 {
compatible = "xlnx,zynq-spi";
compatible = "xlnx,zynq-spi-r1p6";
reg = <0xe0007000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
@ -136,24 +192,28 @@
};
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x4000>;
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
gem1: ethernet@e000c000 {
compatible = "cdns,gem";
reg = <0xe000c000 0x4000>;
compatible = "cdns,zynq-gem", "cdns,gem";
reg = <0xe000c000 0x1000>;
status = "disabled";
interrupts = <0 45 4>;
clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
};
sdhci0: ps7-sdhci@e0100000 {
sdhci0: sdhci@e0100000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
@ -163,7 +223,7 @@
reg = <0xe0100000 0x1000>;
} ;
sdhci1: ps7-sdhci@e0101000 {
sdhci1: sdhci@e0101000 {
compatible = "arasan,sdhci-8.9a";
status = "disabled";
clock-names = "clk_xin", "clk_ahb";
@ -176,13 +236,12 @@
slcr: slcr@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "xlnx,zynq-slcr", "syscon";
compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
reg = <0xF8000000 0x1000>;
ranges;
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
@ -197,6 +256,35 @@
"dbg_trc", "dbg_apb";
reg = <0x100 0x100>;
};
pinctrl0: pinctrl@700 {
compatible = "xlnx,pinctrl-zynq";
reg = <0x700 0x200>;
syscon = <&slcr>;
};
};
dmac_s: dmac@f8003000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0xf8003000 0x1000>;
interrupt-parent = <&intc>;
interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
"dma4", "dma5", "dma6", "dma7";
interrupts = <0 13 4>,
<0 14 4>, <0 15 4>,
<0 16 4>, <0 17 4>,
<0 40 4>, <0 41 4>,
<0 42 4>, <0 43 4>;
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <4>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
devcfg: devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
};
global_timer: timer@f8f00200 {
@ -207,27 +295,57 @@
clocks = <&clkc 4>;
};
ttc0: ttc0@f8001000 {
ttc0: timer@f8001000 {
interrupt-parent = <&intc>;
interrupts = < 0 10 4 0 11 4 0 12 4 >;
interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8001000 0x1000>;
};
ttc1: ttc1@f8002000 {
ttc1: timer@f8002000 {
interrupt-parent = <&intc>;
interrupts = < 0 37 4 0 38 4 0 39 4 >;
interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
compatible = "cdns,ttc";
clocks = <&clkc 6>;
reg = <0xF8002000 0x1000>;
};
scutimer: scutimer@f8f00600 {
scutimer: timer@f8f00600 {
interrupt-parent = <&intc>;
interrupts = < 1 13 0x301 >;
compatible = "arm,cortex-a9-twd-timer";
reg = < 0xf8f00600 0x20 >;
clocks = <&clkc 4>;
} ;
usb0: usb@e0002000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 28>;
interrupt-parent = <&intc>;
interrupts = <0 21 4>;
reg = <0xe0002000 0x1000>;
phy_type = "ulpi";
};
usb1: usb@e0003000 {
compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
status = "disabled";
clocks = <&clkc 29>;
interrupt-parent = <&intc>;
interrupts = <0 44 4>;
reg = <0xe0003000 0x1000>;
phy_type = "ulpi";
};
watchdog0: watchdog@f8005000 {
clocks = <&clkc 45>;
compatible = "cdns,wdt-r1p2";
interrupt-parent = <&intc>;
interrupts = <0 9 1>;
reg = <0xf8005000 0x1000>;
timeout-sec = <10>;
};
};
};

372
arch/arm/dts/zynq-zc702.dts
View File

@ -1,7 +1,8 @@
/*
* Xilinx ZC702 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,15 +10,380 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC702 Board";
model = "Zynq ZC702 Development Board";
compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw14 {
label = "sw14";
gpios = <&gpio0 12 0>;
linux,code = <108>; /* down */
gpio-key,wakeup;
autorepeat;
};
sw13 {
label = "sw13";
gpios = <&gpio0 14 0>;
linux,code = <103>; /* up */
gpio-key,wakeup;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
ds23 {
label = "ds23";
gpios = <&gpio0 10 0>;
linux,default-trigger = "heartbeat";
};
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&amba {
ocm: sram@fffc0000 {
compatible = "mmio-sram";
reg = <0xfffc0000 0x10000>;
};
};
&can0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can0_default>;
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
si570: clock-generator@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x5d>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
hwmon@52 {
compatible = "ti,ucd9248";
reg = <52>;
};
hwmon@53 {
compatible = "ti,ucd9248";
reg = <53>;
};
hwmon@54 {
compatible = "ti,ucd9248";
reg = <54>;
};
};
};
};
&pinctrl0 {
pinctrl_can0_default: can0-default {
mux {
function = "can0";
groups = "can0_9_grp";
};
conf {
groups = "can0_9_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO46";
bias-high-impedance;
};
conf-tx {
pins = "MIO47";
bias-disable;
};
};
pinctrl_gem0_default: gem0-default {
mux {
function = "ethernet0";
groups = "ethernet0_0_grp";
};
conf {
groups = "ethernet0_0_grp";
slew-rate = <0>;
io-standard = <4>;
};
conf-rx {
pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
bias-disable;
low-power-enable;
};
mux-mdio {
function = "mdio0";
groups = "mdio0_0_grp";
};
conf-mdio {
groups = "mdio0_0_grp";
slew-rate = <0>;
io-standard = <1>;
bias-disable;
};
};
pinctrl_gpio0_default: gpio0-default {
mux {
function = "gpio0";
groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
"gpio0_13_grp", "gpio0_14_grp";
};
conf {
groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
"gpio0_13_grp", "gpio0_14_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-pull-up {
pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
bias-pull-up;
};
conf-pull-none {
pins = "MIO7", "MIO8";
bias-disable;
};
};
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_10_grp";
function = "i2c0";
};
conf {
groups = "i2c0_10_grp";
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_2_grp";
function = "sdio0";
};
conf {
groups = "sdio0_2_grp";
slew-rate = <0>;
io-standard = <1>;
bias-disable;
};
mux-cd {
groups = "gpio0_0_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "gpio0_0_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
mux-wp {
groups = "gpio0_15_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "gpio0_15_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO29", "MIO31", "MIO36";
bias-high-impedance;
};
conf-tx {
pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
"MIO35", "MIO37", "MIO38", "MIO39";
bias-disable;
};
};
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};

293
arch/arm/dts/zynq-zc706.dts
View File

@ -1,7 +1,8 @@
/*
* Xilinx ZC706 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,15 +10,301 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC706 Board";
model = "Zynq ZC706 Development Board";
compatible = "xlnx,zynq-zc706", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gem0_default>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&gpio0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio0_default>;
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0_default>;
i2cswitch@74 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x74>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
si570: clock-generator@5d {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x5d>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
eeprom@54 {
compatible = "at,24c08";
reg = <0x54>;
};
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
gpio@21 {
compatible = "ti,tca6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
};
i2c@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
rtc@51 {
compatible = "nxp,pcf8563";
reg = <0x51>;
};
};
i2c@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
ucd90120@65 {
compatible = "ti,ucd90120";
reg = <0x65>;
};
};
};
};
&pinctrl0 {
pinctrl_gem0_default: gem0-default {
mux {
function = "ethernet0";
groups = "ethernet0_0_grp";
};
conf {
groups = "ethernet0_0_grp";
slew-rate = <0>;
io-standard = <4>;
};
conf-rx {
pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
bias-high-impedance;
low-power-disable;
};
conf-tx {
pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
low-power-enable;
bias-disable;
};
mux-mdio {
function = "mdio0";
groups = "mdio0_0_grp";
};
conf-mdio {
groups = "mdio0_0_grp";
slew-rate = <0>;
io-standard = <1>;
bias-disable;
};
};
pinctrl_gpio0_default: gpio0-default {
mux {
function = "gpio0";
groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
};
conf {
groups = "gpio0_7_grp", "gpio0_46_grp", "gpio0_47_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-pull-up {
pins = "MIO46", "MIO47";
bias-pull-up;
};
conf-pull-none {
pins = "MIO7";
bias-disable;
};
};
pinctrl_i2c0_default: i2c0-default {
mux {
groups = "i2c0_10_grp";
function = "i2c0";
};
conf {
groups = "i2c0_10_grp";
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
};
pinctrl_sdhci0_default: sdhci0-default {
mux {
groups = "sdio0_2_grp";
function = "sdio0";
};
conf {
groups = "sdio0_2_grp";
slew-rate = <0>;
io-standard = <1>;
bias-disable;
};
mux-cd {
groups = "gpio0_14_grp";
function = "sdio0_cd";
};
conf-cd {
groups = "gpio0_14_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
mux-wp {
groups = "gpio0_15_grp";
function = "sdio0_wp";
};
conf-wp {
groups = "gpio0_15_grp";
bias-high-impedance;
bias-pull-up;
slew-rate = <0>;
io-standard = <1>;
};
};
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart1_10_grp";
function = "uart1";
};
conf {
groups = "uart1_10_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO49";
bias-high-impedance;
};
conf-tx {
pins = "MIO48";
bias-disable;
};
};
pinctrl_usb0_default: usb0-default {
mux {
groups = "usb0_0_grp";
function = "usb0";
};
conf {
groups = "usb0_0_grp";
slew-rate = <0>;
io-standard = <1>;
};
conf-rx {
pins = "MIO29", "MIO31", "MIO36";
bias-high-impedance;
};
conf-tx {
pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
"MIO35", "MIO37", "MIO38", "MIO39";
bias-disable;
};
};
};
&sdhci0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdhci0_default>;
};
&uart1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0_default>;
};

75
arch/arm/dts/zynq-zc770-xm010.dts
View File

@ -1,7 +1,7 @@
/*
* Xilinx ZC770 XM010 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2013 - 2015 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,20 +9,85 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC770 XM010 Board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;
i2c0 = &i2c0;
serial0 = &uart1;
spi1 = &spi1;
spi0 = &spi1;
};
memory {
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
flash@0 {
compatible = "sst25wf080";
reg = <1>;
spi-max-frequency = <1000000>;
#address-cells = <1>;
#size-cells = <1>;
partition@test {
label = "spi-flash";
reg = <0x0 0x100000>;
};
};
};
&can0 {
status = "okay";
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
m24c02_eeprom@52 {
compatible = "at,24c02";
reg = <0x52>;
};
};
&sdhci0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};

65
arch/arm/dts/zynq-zc770-xm011.dts Normal file
View File

@ -0,0 +1,65 @@
/*
* Xilinx ZC770 XM013 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
i2c0 = &i2c1;
serial0 = &uart1;
spi0 = &spi0;
};
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
usb_phy1: phy1 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&can0 {
status = "okay";
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
m24c02_eeprom@52 {
compatible = "at,24c02";
reg = <0x52>;
};
};
&uart1 {
status = "okay";
};
&usb1 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy1>;
};

51
arch/arm/dts/zynq-zc770-xm012.dts
View File

@ -1,7 +1,7 @@
/*
* Xilinx ZC770 XM012 board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2013 - 2015 Xilinx, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,15 +9,58 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC770 XM012 Board";
compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
serial0 = &uart1;
spi0 = &spi1;
};
memory {
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart1;
stdout-path = &uart1;
};
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
};
&spi1 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
};
&can1 {
status = "okay";
};
&i2c0 {
status = "okay";
clock-frequency = <400000>;
m24c02_eeprom@52 {
compatible = "at,24c02";
reg = <0x52>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
m24c02_eeprom@52 {
compatible = "at,24c02";
reg = <0x52>;
};
};
&uart1 {
status = "okay";
};

62
arch/arm/dts/zynq-zc770-xm013.dts
View File

@ -9,15 +9,71 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZC770 XM013 Board";
compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000";
model = "Xilinx Zynq";
aliases {
ethernet0 = &gem1;
i2c0 = &i2c1;
serial0 = &uart0;
spi0 = &spi0;
};
memory {
chosen {
bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
linux,stdout-path = &uart0;
stdout-path = &uart0;
};
memory@0 {
device_type = "memory";
reg = <0 0x40000000>;
reg = <0x0 0x40000000>;
};
};
&spi0 {
status = "okay";
num-cs = <4>;
is-decoded-cs = <0>;
eeprom: at25@0 {
at25,byte-len = <8192>;
at25,addr-mode = <2>;
at25,page-size = <32>;
compatible = "atmel,at25";
reg = <2>;
spi-max-frequency = <1000000>;
};
};
&can1 {
status = "okay";
};
&gem1 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@7 {
reg = <7>;
};
};
&i2c1 {
status = "okay";
clock-frequency = <400000>;
si570: clock-generator@55 {
#clock-cells = <0>;
compatible = "silabs,si570";
temperature-stability = <50>;
reg = <0x55>;
factory-fout = <156250000>;
clock-frequency = <148500000>;
};
};
&uart0 {
status = "okay";
};

46
arch/arm/dts/zynq-zed.dts
View File

@ -1,7 +1,8 @@
/*
* Xilinx ZED board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,15 +10,54 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZED Board";
model = "Zynq Zed Development Board";
compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x20000000>;
reg = <0x0 0x20000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
usb_phy0: phy0 {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
};
};
&clkc {
ps-clk-frequency = <33333333>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {
status = "okay";
};
&uart1 {
status = "okay";
};
&usb0 {
status = "okay";
dr_mode = "host";
usb-phy = <&usb_phy0>;
};

38
arch/arm/dts/zynq-zybo.dts
View File

@ -1,7 +1,8 @@
/*
* Digilent ZYBO board DTS
*
* Copyright (C) 2013 Xilinx, Inc.
* Copyright (C) 2011 - 2015 Xilinx
* Copyright (C) 2012 National Instruments Corp.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -9,15 +10,44 @@
#include "zynq-7000.dtsi"
/ {
model = "Zynq ZYBO Board";
compatible = "xlnx,zynq-zybo", "xlnx,zynq-7000";
model = "Zynq ZYBO Development Board";
compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
aliases {
ethernet0 = &gem0;
serial0 = &uart1;
};
memory {
device_type = "memory";
reg = <0 0x20000000>;
reg = <0x0 0x20000000>;
};
chosen {
bootargs = "earlyprintk";
stdout-path = "serial0:115200n8";
};
};
&clkc {
ps-clk-frequency = <50000000>;
};
&gem0 {
status = "okay";
phy-mode = "rgmii-id";
phy-handle = <&ethernet_phy>;
ethernet_phy: ethernet-phy@0 {
reg = <0>;
};
};
&sdhci0 {
status = "okay";
};
&uart1 {
status = "okay";
};

16
arch/arm/include/asm/arch-zynqmp/hardware.h
View File

@ -11,6 +11,11 @@
#define ZYNQ_SERIAL_BASEADDR0 0xFF000000
#define ZYNQ_SERIAL_BASEADDR1 0xFF001000
#define ZYNQ_GEM_BASEADDR0 0xFF0B0000
#define ZYNQ_GEM_BASEADDR1 0xFF0C0000
#define ZYNQ_GEM_BASEADDR2 0xFF0D0000
#define ZYNQ_GEM_BASEADDR3 0xFF0E0000
#define ZYNQ_SPI_BASEADDR0 0xFF040000
#define ZYNQ_SPI_BASEADDR1 0xFF050000
@ -20,6 +25,8 @@
#define ZYNQ_SDHCI_BASEADDR0 0xFF160000
#define ZYNQ_SDHCI_BASEADDR1 0xFF170000
#define ZYNQMP_SATA_BASEADDR 0xFD0C0000
#define ZYNQMP_CRL_APB_BASEADDR 0xFF5E0000
#define ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT 0x1000000
@ -55,6 +62,15 @@ struct iou_scntr {
#define EMMC_MODE 0x00000006
#define JTAG_MODE 0x00000000
#define ZYNQMP_IOU_SLCR_BASEADDR 0xFF180000
struct iou_slcr_regs {
u32 mio_pin[78];
u32 reserved[442];
};
#define slcr_base ((struct iou_slcr_regs *)ZYNQMP_IOU_SLCR_BASEADDR)
#define ZYNQMP_RPU_BASEADDR 0xFF9A0000
struct rpu_regs {

6
arch/arm/include/asm/arch-zynqmp/sys_proto.h
View File

@ -8,7 +8,13 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
/* Setup clk for network */
static inline void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate)
{
}
int zynq_sdhci_init(unsigned long regbase);
int zynq_slcr_get_mio_pin_status(const char *periph);
unsigned int zynqmp_get_silicon_version(void);

2
board/xilinx/zynq/Makefile
View File

@ -25,7 +25,7 @@ ifeq ($(init-objs),)
ifneq ($(wildcard $(srctree)/$(src)/ps7_init_gpl.c),)
init-objs := ps7_init_gpl.o
$(if $(CONFIG_SPL_BUILD),\
$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custome_hw_platform/))
$(warning Put custom ps7_init_gpl.c/h to board/xilinx/zynq/custom_hw_platform/))
endif
endif

15
board/xilinx/zynqmp/Kconfig
View File

@ -1,15 +0,0 @@
if TARGET_XILINX_ZYNQMP
config SYS_BOARD
default "zynqmp"
config SYS_VENDOR
default "xilinx"
config SYS_SOC
default "zynqmp"
config SYS_CONFIG_NAME
default "xilinx_zynqmp"
endif

5
board/xilinx/zynqmp/MAINTAINERS
View File

@ -1,6 +1,7 @@
XILINX_ZYNQMP BOARD
XILINX_ZYNQMP_EP BOARD
M: Michal Simek <michal.simek@xilinx.com>
S: Maintained
F: board/xilinx/zynqmp/
F: include/configs/xilinx_zynqmp.h
F: configs/xilinx_zynqmp_defconfig
F: include/configs/xilinx_zynqmp_ep.h
F: configs/xilinx_zynqmp_ep_defconfig

37
board/xilinx/zynqmp/zynqmp.c
View File

@ -7,6 +7,8 @@
#include <common.h>
#include <netdev.h>
#include <ahci.h>
#include <scsi.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
#include <asm/io.h>
@ -15,6 +17,8 @@ DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
{
printf("EL Level:\tEL%d\n", current_el());
return 0;
}
@ -51,6 +55,39 @@ void reset_cpu(ulong addr)
{
}
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
ahci_init((void __iomem *)ZYNQMP_SATA_BASEADDR);
scsi_scan(1);
}
#endif
int board_eth_init(bd_t *bis)
{
u32 ret = 0;
#if defined(CONFIG_ZYNQ_GEM)
# if defined(CONFIG_ZYNQ_GEM0)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM1)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM2)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR2,
CONFIG_ZYNQ_GEM_PHY_ADDR2, 0);
# endif
# if defined(CONFIG_ZYNQ_GEM3)
ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR3,
CONFIG_ZYNQ_GEM_PHY_ADDR3, 0);
# endif
#endif
return ret;
}
#ifdef CONFIG_CMD_MMC
int board_mmc_init(bd_t *bd)
{

22
common/cmd_mp.c
View File

@ -7,11 +7,32 @@
#include <common.h>
#include <command.h>
static int cpu_status_all(void)
{
unsigned long cpuid;
for (cpuid = 0; ; cpuid++) {
if (!is_core_valid(cpuid)) {
if (cpuid == 0) {
printf("Core num: %lu is not valid\n", cpuid);
return 1;
}
break;
}
cpu_status(cpuid);
}
return 0;
}
static int
cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long cpuid;
if (argc == 2 && strncmp(argv[1], "status", 6) == 0)
return cpu_status_all();
if (argc < 3)
return CMD_RET_USAGE;
@ -48,6 +69,7 @@ cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_LONGHELP
static char cpu_help_text[] =
"<num> reset - Reset cpu <num>\n"
"cpu status - Status of all cpus\n"
"cpu <num> status - Status of cpu <num>\n"
"cpu <num> disable - Disable cpu <num>\n"
"cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]"

5
configs/xilinx_zynqmp_defconfig → configs/xilinx_zynqmp_ep_defconfig
View File

@ -1,6 +1,6 @@
CONFIG_ARM=y
CONFIG_TARGET_XILINX_ZYNQMP=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp"
CONFIG_ARCH_ZYNQMP=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-ep"
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_XIMG is not set
@ -15,3 +15,4 @@ CONFIG_DEFAULT_DEVICE_TREE="zynqmp"
# CONFIG_CMD_NFS is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_TIMER=y
CONFIG_SYS_TEXT_BASE=0x8000000

13
configs/zynq_zc770_xm011_defconfig Normal file
View File

@ -0,0 +1,13 @@
CONFIG_ARM=y
CONFIG_ARCH_ZYNQ=y
CONFIG_TARGET_ZYNQ_ZC770=y
CONFIG_DEFAULT_DEVICE_TREE="zynq-zc770-xm011"
# CONFIG_SYS_MALLOC_F is not set
CONFIG_SPL=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SYS_EXTRA_OPTIONS="ZC770_XM011"
# CONFIG_CMD_IMLS is not set
# CONFIG_CMD_FLASH is not set
# CONFIG_CMD_SETEXPR is not set

35
doc/device-tree-bindings/spi/spi-zynq.txt
View File

@ -1,29 +1,32 @@
Zynq SPI controller Device Tree Bindings
----------------------------------------
Cadence SPI controller Device Tree Bindings
-------------------------------------------
Required properties:
- compatible : Should be "xlnx,spi-zynq".
- compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
- reg : Physical base address and size of SPI registers map.
- status : Status will be disabled in dtsi and enabled in required dts.
- interrupt-parent : Must be core interrupt controller.
- interrupts : Property with a value describing the interrupt
number.
- clocks : Clock phandles (see clock bindings for details).
- interrupt-parent : Must be core interrupt controller
- clock-names : List of input clock names - "ref_clk", "pclk"
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
- spi-max-frequency : Maximum SPI clocking speed of device in Hz
Optional properties:
- num-cs : Number of chip selects used.
If a decoder is used, this will be the number of
chip selects after the decoder.
- is-decoded-cs : Flag to indicate whether decoder is used or not.
Example:
spi@e0006000 {
compatible = "xlnx,zynq-spi";
reg = <0xe0006000 0x1000>;
status = "disabled";
interrupt-parent = <&intc>;
interrupts = <0 26 4>;
clocks = <&clkc 25>, <&clkc 34>;
spi@e0007000 {
compatible = "xlnx,zynq-spi-r1p6";
clock-names = "ref_clk", "pclk";
spi-max-frequency = <166666700>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clkc 26>, <&clkc 35>;
interrupt-parent = <&intc>;
interrupts = <0 49 4>;
num-cs = <4>;
is-decoded-cs = <0>;
reg = <0xe0007000 0x1000>;
} ;

26
drivers/net/zynq_gem.c
View File

@ -20,6 +20,7 @@
#include <phy.h>
#include <miiphy.h>
#include <watchdog.h>
#include <asm/system.h>
#include <asm/arch/hardware.h>
#include <asm/arch/sys_proto.h>
@ -58,7 +59,14 @@
#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000080000 /* Div pclk by 32, 80MHz */
#define ZYNQ_GEM_NWCFG_MDCCLKDIV2 0x0000c0000 /* Div pclk by 48, 120MHz */
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_NWCFG_FDEN | \
#ifdef CONFIG_ARM64
# define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */
#else
# define ZYNQ_GEM_DBUS_WIDTH (0 << 21) /* 32 bit bus */
#endif
#define ZYNQ_GEM_NWCFG_INIT (ZYNQ_GEM_DBUS_WIDTH | \
ZYNQ_GEM_NWCFG_FDEN | \
ZYNQ_GEM_NWCFG_FSREM | \
ZYNQ_GEM_NWCFG_MDCCLKDIV)
@ -130,7 +138,7 @@ struct emac_bd {
u32 status;
};
#define RX_BUF 3
#define RX_BUF 32
/* Page table entries are set to 1MB, or multiples of 1MB
* (not < 1MB). driver uses less bd's so use 1MB bdspace.
*/
@ -155,7 +163,7 @@ struct zynq_gem_priv {
static inline int mdio_wait(struct eth_device *dev)
{
struct zynq_gem_regs *regs = (struct zynq_gem_regs *)dev->iobase;
u32 timeout = 200;
u32 timeout = 20000;
/* Wait till MDIO interface is ready to accept a new transaction. */
while (--timeout) {
@ -395,12 +403,18 @@ static int zynq_gem_send(struct eth_device *dev, void *ptr, int len)
priv->tx_bd->addr = (u32)ptr;
priv->tx_bd->status = (len & ZYNQ_GEM_TXBUF_FRMLEN_MASK) |
ZYNQ_GEM_TXBUF_LAST_MASK;
ZYNQ_GEM_TXBUF_LAST_MASK |
ZYNQ_GEM_TXBUF_WRAP_MASK;
addr = (u32) ptr;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup(len, ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
addr = (u32)priv->rxbuffers;
addr &= ~(ARCH_DMA_MINALIGN - 1);
size = roundup((RX_BUF * PKTSIZE_ALIGN), ARCH_DMA_MINALIGN);
flush_dcache_range(addr, addr + size);
barrier();
/* Start transmit */
@ -436,8 +450,6 @@ static int zynq_gem_recv(struct eth_device *dev)
if (frame_len) {
u32 addr = current_bd->addr & ZYNQ_GEM_RXBUF_ADD_MASK;
addr &= ~(ARCH_DMA_MINALIGN - 1);
u32 size = roundup(frame_len, ARCH_DMA_MINALIGN);
invalidate_dcache_range(addr, addr + size);
net_process_received_packet((u8 *)addr, frame_len);
@ -511,7 +523,7 @@ int zynq_gem_initialize(bd_t *bis, phys_addr_t base_addr,
priv->rxbuffers = memalign(ARCH_DMA_MINALIGN, RX_BUF * PKTSIZE_ALIGN);
memset(priv->rxbuffers, 0, RX_BUF * PKTSIZE_ALIGN);
/* Align bd_space to 1MB */
/* Align bd_space to MMU_SECTION_SHIFT */
bd_space = memalign(1 << MMU_SECTION_SHIFT, BD_SPACE);
mmu_set_region_dcache_behaviour((phys_addr_t)bd_space,
BD_SPACE, DCACHE_OFF);

4
drivers/spi/zynq_spi.c
View File

@ -79,7 +79,7 @@ static int zynq_spi_ofdata_to_platdata(struct udevice *bus)
250000000);
plat->speed_hz = plat->frequency / 2;
debug("zynq_spi_ofdata_to_platdata: regs=%p max-frequency=%d\n",
debug("%s: regs=%p max-frequency=%d\n", __func__,
plat->regs, plat->frequency);
return 0;
@ -309,7 +309,7 @@ static const struct dm_spi_ops zynq_spi_ops = {
};
static const struct udevice_id zynq_spi_ids[] = {
{ .compatible = "xlnx,zynq-spi" },
{ .compatible = "xlnx,zynq-spi-r1p6" },
{ }
};

48
include/configs/xilinx_zynqmp.h
View File

@ -40,7 +40,6 @@
#define CONFIG_IDENT_STRING " Xilinx ZynqMP"
#define CONFIG_SYS_TEXT_BASE 0x8000000
#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
/* Flat Device Tree Definitions */
@ -53,16 +52,20 @@
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 0x400000)
/* Serial setup */
#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_SERIAL
#if defined(CONFIG_ZYNQMP_DCC)
# define CONFIG_ARM_DCC
# define CONFIG_CPU_ARMV8
#else
# if defined(CONFIG_ZYNQ_SERIAL_UART0) || defined(CONFIG_ZYNQ_SERIAL_UART1)
# define CONFIG_ZYNQ_SERIAL
# endif
#endif
#define CONFIG_CONS_INDEX 0
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE \
{ 4800, 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_ZYNQ_SDHCI0
/* Command line configuration */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_EXT2
@ -73,6 +76,16 @@
#define CONFIG_CMD_ELF
#define CONFIG_MP
#define CONFIG_CMD_MII
/* BOOTP options */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_MAY_FAIL
#define CONFIG_BOOTP_SERVERIP
/* SPI */
#ifdef CONFIG_ZYNQ_SPI
# define CONFIG_SPI_FLASH_SST
@ -127,8 +140,16 @@
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_MAXARGS 64
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
/* Ethernet driver */
#if defined(CONFIG_ZYNQ_GEM0) || defined(CONFIG_ZYNQ_GEM1) || \
defined(CONFIG_ZYNQ_GEM2) || defined(CONFIG_ZYNQ_GEM3)
# define CONFIG_NET_MULTI
# define CONFIG_ZYNQ_GEM
# define CONFIG_MII
# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
# define CONFIG_PHYLIB
# define CONFIG_PHY_MARVELL
#endif
/* I2C */
#if defined(CONFIG_SYS_I2C_ZYNQ)
@ -138,8 +159,6 @@
# define CONFIG_SYS_I2C_ZYNQ_SLAVE 0
#endif
#define CONFIG_ZYNQMP_EEPROM
/* EEPROM */
#ifdef CONFIG_ZYNQMP_EEPROM
# define CONFIG_CMD_EEPROM
@ -150,6 +169,17 @@
# define CONFIG_SYS_EEPROM_SIZE (64 * 1024)
#endif
#ifdef CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
#define CONFIG_SYS_SCSI_MAX_LUN 1
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_CMD_SCSI
#endif
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */

27
include/configs/xilinx_zynqmp_ep.h Normal file
View File

@ -0,0 +1,27 @@
/*
* Configuration for Xilinx ZynqMP emulation
* platforms. See zynqmp-common.h for ZynqMP
* common configs
*
* (C) Copyright 2014 - 2015 Xilinx, Inc.
* Michal Simek <michal.simek@xilinx.com>
* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
*
* Based on Configuration for Versatile Express
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __CONFIG_ZYNQMP_EP_H
#define __CONFIG_ZYNQMP_EP_H
#define CONFIG_ZYNQ_SERIAL_UART0
#define CONFIG_ZYNQ_SDHCI0
#define CONFIG_ZYNQ_I2C0
#define CONFIG_SYS_I2C_ZYNQ
#define CONFIG_ZYNQ_EEPROM
#define CONFIG_AHCI
#include <configs/xilinx_zynqmp.h>
#endif /* __CONFIG_ZYNQMP_EP_H */

3
include/configs/zynq_zc770.h
View File

@ -21,6 +21,9 @@
# define CONFIG_ZYNQ_SDHCI0
# define CONFIG_ZYNQ_SPI
#elif defined(CONFIG_ZC770_XM011)
# define CONFIG_ZYNQ_SERIAL_UART1
#elif defined(CONFIG_ZC770_XM012)
# define CONFIG_ZYNQ_SERIAL_UART1
# undef CONFIG_SYS_NO_FLASH