* Patch by Yuli Barcohen, 13 Jul 2004:
Allow clock setting on MPC866/MPC885 series chips according to environment variable `cpuclk' * Patch by Yuli Barcohen, 20 Apr 2004: Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
This commit is contained in:
parent
4ec3a7f0fd
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66ca92a5ba
@ -2,6 +2,13 @@
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Changes since U-Boot 1.1.1:
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======================================================================
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* Patch by Yuli Barcohen, 13 Jul 2004:
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Allow clock setting on MPC866/MPC885 series chips according to
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environment variable `cpuclk'
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* Patch by Yuli Barcohen, 20 Apr 2004:
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Remove unnecessary redefine of CPM_DATAONLY_SIZE for MPC826x
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* Patch by Vincent Dubey, 24 Sep 2004:
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Add support for xaeniax board
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17
README
17
README
@ -339,16 +339,17 @@ The following options need to be configured:
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CONFIG_MPC8240, CONFIG_MPC8245
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- 8xx CPU Options: (if using an MPC8xx cpu)
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Define one or more of
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CONFIG_8xx_GCLK_FREQ - if get_gclk_freq() cannot work
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CONFIG_8xx_GCLK_FREQ - deprecated: CPU clock if
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get_gclk_freq() cannot work
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e.g. if there is no 32KHz
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reference PIT/RTC clock
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CONFIG_8xx_OSCLK - PLL input clock (either EXTCLK
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or XTAL/EXTAL)
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- 859/866 CPU options: (if using a MPC859 or MPC866 CPU):
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CFG_866_OSCCLK
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CFG_866_CPUCLK_MIN
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CFG_866_CPUCLK_MAX
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CFG_866_CPUCLK_DEFAULT
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- 859/866/885 CPU options: (if using a MPC859 or MPC866 or MPC885 CPU):
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CFG_8xx_CPUCLK_MIN
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CFG_8xx_CPUCLK_MAX
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CONFIG_8xx_CPUCLK_DEFAULT
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See doc/README.MPC866
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CFG_MEASURE_CPUCLK
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@ -358,7 +359,7 @@ The following options need to be configured:
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values. Mostly useful for board bringup to make sure
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the PLL is locked at the intended frequency. Note
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that this requires a (stable) reference clock (32 kHz
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RTC clock),
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RTC clock or CFG_8XX_XIN)
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- Linux Kernel Interface:
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CONFIG_CLOCKS_IN_MHZ
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@ -20,13 +20,6 @@
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#include <common.h>
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#include <asm/cpm_8260.h>
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/*
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* because we have stack and init data in dual port ram
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* we must reduce the size
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*/
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#undef CPM_DATAONLY_SIZE
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#define CPM_DATAONLY_SIZE ((uint)(8 * 1024) - CPM_DATAONLY_BASE)
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void
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m8260_cpm_reset(void)
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{
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@ -124,13 +124,13 @@ static int check_CPU (long clock, uint pvr, uint immr)
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printf ("unknown M%s (0x%08x)", id_str, k);
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#if defined(CFG_866_CPUCLK_MIN) && defined(CFG_866_CPUCLK_MAX)
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#if defined(CFG_8xx_CPUCLK_MIN) && defined(CFG_8xx_CPUCLK_MAX)
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printf (" at %s MHz [%d.%d...%d.%d MHz]\n ",
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strmhz (buf, clock),
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CFG_866_CPUCLK_MIN / 1000000,
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((CFG_866_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CFG_866_CPUCLK_MAX / 1000000,
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((CFG_866_CPUCLK_MAX % 1000000) + 50000) / 100000
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CFG_8xx_CPUCLK_MIN / 1000000,
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((CFG_8xx_CPUCLK_MIN % 1000000) + 50000) / 100000,
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CFG_8xx_CPUCLK_MAX / 1000000,
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((CFG_8xx_CPUCLK_MAX % 1000000) + 50000) / 100000
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);
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#else
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printf (" at %s MHz: ", strmhz (buf, clock));
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@ -140,7 +140,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
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checkdcache () >> 10
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);
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/* do we have a FEC (860T/P or 852/859/866)? */
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/* do we have a FEC (860T/P or 852/859/866/885)? */
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immap->im_cpm.cp_fec.fec_addr_low = 0x12345678;
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if (immap->im_cpm.cp_fec.fec_addr_low == 0x12345678) {
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@ -25,7 +25,7 @@
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#include <mpc8xx.h>
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#include <asm/processor.h>
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#if !defined(CONFIG_TQM866M) || defined(CFG_MEASURE_CPUCLK)
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#if !defined(CONFIG_8xx_CPUCLK_DEFAULT) || defined(CFG_MEASURE_CPUCLK)
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#define PITC_SHIFT 16
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#define PITR_SHIFT 16
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@ -172,7 +172,7 @@ unsigned long measure_gclk(void)
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#endif
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#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
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#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
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/*
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* get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
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@ -226,15 +226,15 @@ int get_clocks (void)
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return (0);
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}
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#else /* CONFIG_MPC866_FAMILY */
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#else /* CONFIG_8xx_CPUCLK_DEFAULT defined, use dynamic clock setting */
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static long init_pll_866 (long clk);
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/* This function sets up PLL (init_pll_866() is called) and
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* fills gd->cpu_clk and gd->bus_clk according to the environment
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* variable 'cpuclk' or to CFG_866_CPUCLK_DEFAULT (if 'cpuclk'
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* variable 'cpuclk' or to CONFIG_8xx_CPUCLK_DEFAULT (if 'cpuclk'
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* contains invalid value).
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* This functions requires an MPC866 series CPU.
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* This functions requires an MPC866 or newer series CPU.
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*/
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int get_clocks_866 (void)
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{
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@ -248,8 +248,8 @@ int get_clocks_866 (void)
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if (getenv_r ("cpuclk", tmp, sizeof (tmp)) > 0)
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cpuclk = simple_strtoul (tmp, NULL, 10) * 1000000;
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if ((CFG_866_CPUCLK_MIN > cpuclk) || (CFG_866_CPUCLK_MAX < cpuclk))
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cpuclk = CFG_866_CPUCLK_DEFAULT;
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if ((CFG_8xx_CPUCLK_MIN > cpuclk) || (CFG_8xx_CPUCLK_MAX < cpuclk))
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cpuclk = CONFIG_8xx_CPUCLK_DEFAULT;
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gd->cpu_clk = init_pll_866 (cpuclk);
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#if defined(CFG_MEASURE_CPUCLK)
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@ -284,13 +284,13 @@ int sdram_adjust_866 (void)
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mamr = immr->im_memctl.memc_mamr;
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mamr &= ~MAMR_PTA_MSK;
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mamr |= ((gd->cpu_clk / CFG_866_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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mamr |= ((gd->cpu_clk / CFG_PTA_PER_CLK) << MAMR_PTA_SHIFT);
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immr->im_memctl.memc_mamr = mamr;
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return (0);
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}
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/* Configure PLL for MPC866/859 CPU series
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/* Configure PLL for MPC866/859/885 CPU series
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* PLL multiplication factor is set to the value nearest to the desired clk,
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* assuming a oscclk of 10 MHz.
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*/
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@ -312,19 +312,19 @@ static long init_pll_866 (long clk)
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if (clk < 40000000) {
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s = 2;
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step_mfi = CFG_866_OSCCLK / 4;
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step_mfi = CONFIG_8xx_OSCLK / 4;
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mfd = 7;
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step_mfn = CFG_866_OSCCLK / 30;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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} else if (clk < 80000000) {
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s = 1;
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step_mfi = CFG_866_OSCCLK / 2;
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step_mfi = CONFIG_8xx_OSCLK / 2;
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mfd = 14;
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step_mfn = CFG_866_OSCCLK / 30;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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} else {
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s = 0;
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step_mfi = CFG_866_OSCCLK;
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step_mfi = CONFIG_8xx_OSCLK;
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mfd = 29;
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step_mfn = CFG_866_OSCCLK / 30;
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step_mfn = CONFIG_8xx_OSCLK / 30;
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}
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/* Calculate integer part of multiplication factor
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@ -362,7 +362,7 @@ static long init_pll_866 (long clk)
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return (n);
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}
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#endif /* CONFIG_MPC866_FAMILY */
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#endif /* CONFIG_8xx_CPUCLK_DEFAULT */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
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/*
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@ -1,12 +1,12 @@
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The current implementation allows the user to specify the desired CPU
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clock value, in MHz, via an environment variable "cpuclk".
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Three compile-time constants are used:
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Four compile-time constants are used:
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CFG_866_OSCCLK - input quartz clock
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CFG_866_CPUCLK_MIN - minimum allowed CPU clock
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CFG_866_CPUCLK_MAX - maximum allowed CPU clock
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CFG_866_CPUCLK_DEFAULT - default CPU clock value
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CONFIG_8xx_OSCLK - input quartz clock
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CFG_8xx_CPUCLK_MIN - minimum allowed CPU clock
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CFG_8xx_CPUCLK_MAX - maximum allowed CPU clock
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CONFIG_8xx_CPUCLK_DEFAULT - default CPU clock value
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If the "cpuclk" environment variable value is within the CPUCLK_MIN /
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CPUCLK_MAX limits, the specified value is used. Otherwise, the
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@ -16,8 +16,9 @@ Please make sure you understand what you are doing, and understand
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the restrictions of your hardware (board, processor). For example,
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ethernet will stop working for CPU clock frequencies below 25 MHz.
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Please note that for now the new clock-handling code has been enabled
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for the TQM866M board only, even though it should be pretty much
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common for other MPC859 / MPC866 based boards also. Our intention
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here was to move in small steps and not to break the existing code
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for other boards.
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Please note that the new clock-handling code is enabled if
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CONFIG_8xx_CPUCLK_DEFAULT is defined. Since this mechanism supports
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only MPC866 and newer CPUs, this constant MUST NOT be defined for
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MPC823/850/860/862 series. The clock generation algorithm for older
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chips is different and has not been implemented yet. If you need it,
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your patch is welcome.
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#define FEC_ENET
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#endif /* CONFIG_FEC_ENET */
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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#define CFG_8xx_CPUCLK_MIN 40000000
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#ifdef CONFIG_MPC852T
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#define CFG_8xx_CPUCLK_MAX 50000000
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#else
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#define CFG_8xx_CPUCLK_MAX 120000000
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#endif /* CONFIG_MPC852T */
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#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
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| CFG_CMD_DHCP \
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@ -89,6 +96,15 @@
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#define CFG_MAMR 0x00802114
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/*
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* 2048 SDRAM rows
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* 1000 factor s -> ms
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* 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_PTA_PER_CLK ((2048 * 64 * 1000) / (4 * 64))
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#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
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#define CFG_MEMTEST_END 0x00700000 /* 1 ... 7 MB in SDRAM */
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/*
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* 10 MHz - PLL input clock
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*/
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#define CFG_866_OSCCLK 10000000
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#define CFG_8xx_OSCCLK 10000000
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/*
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* 50 MHz - default CPU clock
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*/
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#define CFG_866_CPUCLK_DEFAULT 50000000
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
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/*
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* 15 MHz - CPU minimum clock
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*/
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#define CFG_866_CPUCLK_MIN 15000000
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#define CFG_8xx_CPUCLK_MIN 15000000
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/*
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* 133 MHz - CPU maximum clock
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*/
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#define CFG_866_CPUCLK_MAX 133000000
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#define CFG_8xx_CPUCLK_MAX 133000000
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#define CFG_MEASURE_CPUCLK
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#define CFG_8XX_XIN CFG_866_OSCCLK
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#define CFG_8XX_XIN CFG_8xx_OSCCLK
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#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
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@ -307,7 +307,7 @@
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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/*
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* Memory Periodic Timer Prescaler
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@ -1,5 +1,5 @@
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/*
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* (C) Copyright 2000-2003
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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@ -36,10 +36,10 @@
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#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
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#define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */
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#define CFG_866_OSCCLK 10000000 /* 10 MHz - PLL input clock */
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#define CFG_866_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
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#define CFG_866_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
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#define CFG_866_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
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#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */
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#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */
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#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */
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#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 /* 50 MHz - CPU default clock */
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/* (it will be used if there is no */
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/* 'cpuclk' variable with valid value) */
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@ -404,12 +404,12 @@
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* 4 Number of refresh cycles per period
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* 64 Refresh cycle in ms per number of rows
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*/
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#define CFG_866_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
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/*
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* Memory Periodic Timer Prescaler
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* Periodic timer for refresh, start with refresh rate for 40 MHz clock
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* (CFG_866_CPUCLK_MIN / CFG_866_PTA_PER_CLK)
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* (CFG_8xx_CPUCLK_MIN / CFG_PTA_PER_CLK)
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*/
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#define CFG_MAMR_PTA 39
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board_early_init_f,
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#endif
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#if !defined(CONFIG_TQM866M) && !defined(CONFIG_NC650)
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#if !defined(CONFIG_8xx_CPUCLK_DEFAULT)
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get_clocks, /* get CPU and bus clocks (etc.) */
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#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M)
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adjust_sdram_tbs_8xx,
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@ -280,7 +280,7 @@ init_fnc_t *init_sequence[] = {
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board_postclk_init,
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#endif
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env_init,
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#if defined(CONFIG_TQM866M) || defined(CONFIG_NC650)
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#if defined(CONFIG_8xx_CPUCLK_DEFAULT)
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get_clocks_866, /* get CPU and bus clocks according to the environment variable */
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sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */
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init_timebase,
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Block a user