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- Replace STM32MP1_TRUSTED by TFABOOT flag

Browse Source 
- Enable bootd, iminfo, imxtract on ST defconfig
 - Rename LEDs to match silkscreen on AV96
 - Add KS8851-16MLL ethernet on FMC2
 - Define FMC2 base address
 - net: dwc_eth_qos: implement reset-gpios for stm32
 - net: dwc_eth_qos: implement phy reg and max-speed for stm32
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Merge tag 'u-boot-stm32-20200415' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm

- Replace STM32MP1_TRUSTED by TFABOOT flag
- Enable bootd, iminfo, imxtract on ST defconfig
- Rename LEDs to match silkscreen on AV96
- Add KS8851-16MLL ethernet on FMC2
- Define FMC2 base address
- net: dwc_eth_qos: implement reset-gpios for stm32
- net: dwc_eth_qos: implement phy reg and max-speed for stm32
This commit is contained in:
Tom Rini 2020-04-15 12:10:51 -04:00
commit 66b8669d77
17 changed files with 228 additions and 48 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Kconfig
View File

@ -1586,6 +1586,7 @@ config ARCH_STI
config ARCH_STM32MP
bool "Support STMicroelectronics STM32MP Socs with cortex A"
select ARCH_MISC_INIT
select ARCH_SUPPORT_TFABOOT
select BOARD_LATE_INIT
select CLK
select DM

6
arch/arm/dts/stm32mp157a-avenger96.dts
View File

@ -38,21 +38,21 @@
led {
compatible = "gpio-leds";
led1 {
label = "green:user1";
label = "green:user0";
gpios = <&gpioz 7 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
default-state = "off";
};
led2 {
label = "green:user2";
label = "green:user1";
gpios = <&gpiof 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc0";
default-state = "off";
};
led3 {
label = "green:user3";
label = "green:user2";
gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "mmc1";
default-state = "off";

68
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi
View File

@ -37,6 +37,12 @@
default-state = "on";
};
};
/* This is actually on FMC2, but we do not have bus driver for that */
ksz8851: ks8851mll@64000000 {
compatible = "micrel,ks8851-mll";
reg = <0x64000000 0x20000>;
};
};
&i2c4 {
@ -50,6 +56,68 @@
};
};
&pinctrl {
/* These should bound to FMC2 bus driver, but we do not have one */
pinctrl-0 = <&fmc_pins_b>;
pinctrl-1 = <&fmc_sleep_pins_b>;
pinctrl-names = "default", "sleep";
fmc_pins_b: fmc-0 {
pins1 {
pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */
<STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */
bias-disable;
drive-push-pull;
slew-rate = <3>;
};
};
fmc_sleep_pins_b: fmc-sleep-0 {
pins {
pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */
<STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */
<STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */
<STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */
<STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */
<STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */
<STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */
<STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */
<STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */
<STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */
<STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */
<STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */
<STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */
<STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */
<STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */
<STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */
<STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */
<STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */
<STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */
<STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */
<STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */
};
};
};
&pmic {
u-boot,dm-pre-reloc;
};

21
arch/arm/mach-stm32mp/Kconfig
View File

@ -35,9 +35,10 @@ config ENV_SIZE
config STM32MP15x
bool "Support STMicroelectronics STM32MP15x Soc"
select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
select ARCH_SUPPORT_PSCI if !TFABOOT
select ARM_SMCCC if TFABOOT
select CPU_V7A
select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
select CPU_V7_HAS_NONSEC if !TFABOOT
select CPU_V7_HAS_VIRT
select OF_BOARD_SETUP
select PINCTRL_STM32
@ -45,8 +46,8 @@ config STM32MP15x
select STM32_RESET
select STM32_SERIAL
select SYS_ARCH_TIMER
imply SYSRESET_PSCI if STM32MP1_TRUSTED
imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
imply SYSRESET_PSCI if TFABOOT
imply SYSRESET_SYSCON if !TFABOOT
help
support of STMicroelectronics SOC STM32MP15x family
STM32MP157, STM32MP153 or STM32MP151
@ -83,19 +84,9 @@ config TARGET_DH_STM32MP1_PDK2
endchoice
config STM32MP1_TRUSTED
bool "Support trusted boot with TF-A"
default y if !SPL
select ARM_SMCCC
help
Say Y here to enable boot with TF-A
Trusted boot chain is :
BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
TF-A monitor provides proprietary SMC to manage secure devices
config STM32MP1_OPTEE
bool "Support trusted boot with TF-A and OP-TEE"
depends on STM32MP1_TRUSTED
depends on TFABOOT
default n
help
Say Y here to enable boot with TF-A and OP-TEE

18
arch/arm/mach-stm32mp/bsec.c
View File

@ -68,7 +68,7 @@ static bool bsec_read_lock(u32 address, u32 otp)
return !!(readl(address + bank) & bit);
}
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
/**
* bsec_check_error() - Check status of one otp
* @base: base address of bsec IP
@ -273,7 +273,7 @@ static int bsec_program_otp(long base, u32 val, u32 otp)
return ret;
}
#endif /* CONFIG_STM32MP1_TRUSTED */
#endif /* CONFIG_TFABOOT */
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_platdata {
@ -282,7 +282,7 @@ struct stm32mp_bsec_platdata {
static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
#ifdef CONFIG_STM32MP1_TRUSTED
#ifdef CONFIG_TFABOOT
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_OTP,
otp, 0, val);
@ -313,7 +313,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
#ifdef CONFIG_STM32MP1_TRUSTED
#ifdef CONFIG_TFABOOT
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
@ -336,7 +336,7 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
#ifdef CONFIG_STM32MP1_TRUSTED
#ifdef CONFIG_TFABOOT
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
@ -349,7 +349,7 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
#ifdef CONFIG_STM32MP1_TRUSTED
#ifdef CONFIG_TFABOOT
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
@ -362,7 +362,7 @@ static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
static int stm32mp_bsec_write_lock(struct udevice *dev, u32 val, u32 otp)
{
#ifdef CONFIG_STM32MP1_TRUSTED
#ifdef CONFIG_TFABOOT
if (val == 1)
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRLOCK_OTP,
@ -473,7 +473,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
return 0;
}
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
static int stm32mp_bsec_probe(struct udevice *dev)
{
int otp;
@ -500,7 +500,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
.ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
.ops = &stm32mp_bsec_ops,
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
.probe = stm32mp_bsec_probe,
#endif
};

10
arch/arm/mach-stm32mp/cpu.c
View File

@ -76,7 +76,7 @@
#define PKG_MASK GENMASK(2, 0)
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
static void security_init(void)
{
/* Disable the backup domain write protection */
@ -136,7 +136,7 @@ static void security_init(void)
writel(BIT(0), RCC_MP_AHB5ENSETR);
writel(0x0, GPIOZ_SECCFGR);
}
#endif /* CONFIG_STM32MP1_TRUSTED */
#endif /* CONFIG_TFABOOT */
/*
* Debug init
@ -150,7 +150,7 @@ static void dbgmcu_init(void)
}
#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
#if !defined(CONFIG_STM32MP1_TRUSTED) && \
#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
/* get bootmode from ROM code boot context: saved in TAMP register */
static void update_bootmode(void)
@ -198,7 +198,7 @@ int arch_cpu_init(void)
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
dbgmcu_init();
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
security_init();
update_bootmode();
#endif
@ -214,7 +214,7 @@ int arch_cpu_init(void)
if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#if defined(CONFIG_DEBUG_UART) && \
!defined(CONFIG_STM32MP1_TRUSTED) && \
!defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
else
debug_uart_init();

1
arch/arm/mach-stm32mp/include/mach/stm32.h
View File

@ -13,6 +13,7 @@
#define STM32_RCC_BASE 0x50000000
#define STM32_PWR_BASE 0x50001000
#define STM32_DBGMCU_BASE 0x50081000
#define STM32_FMC2_BASE 0x58002000
#define STM32_TZC_BASE 0x5C006000
#define STM32_ETZPC_BASE 0x5C007000
#define STM32_STGEN_BASE 0x5C008000

58
board/dhelectronics/dh_stm32mp1/board.c
View File

@ -118,7 +118,7 @@ int checkboard(void)
if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
mode = "trusted with OP-TEE";
else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
else if (IS_ENABLED(CONFIG_TFABOOT))
mode = "trusted";
else
mode = "basic";
@ -283,7 +283,7 @@ static void __maybe_unused led_error_blink(u32 nb_blink)
static void sysconf_init(void)
{
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
u8 *syscfg;
#ifdef CONFIG_DM_REGULATOR
struct udevice *pwr_dev;
@ -375,6 +375,56 @@ static void sysconf_init(void)
#endif
}
static void board_init_fmc2(void)
{
#define STM32_FMC2_BCR1 0x0
#define STM32_FMC2_BTR1 0x4
#define STM32_FMC2_BWTR1 0x104
#define STM32_FMC2_BCR(x) ((x) * 0x8 + STM32_FMC2_BCR1)
#define STM32_FMC2_BCRx_FMCEN BIT(31)
#define STM32_FMC2_BCRx_WREN BIT(12)
#define STM32_FMC2_BCRx_RSVD BIT(7)
#define STM32_FMC2_BCRx_FACCEN BIT(6)
#define STM32_FMC2_BCRx_MWID(n) ((n) << 4)
#define STM32_FMC2_BCRx_MTYP(n) ((n) << 2)
#define STM32_FMC2_BCRx_MUXEN BIT(1)
#define STM32_FMC2_BCRx_MBKEN BIT(0)
#define STM32_FMC2_BTR(x) ((x) * 0x8 + STM32_FMC2_BTR1)
#define STM32_FMC2_BTRx_DATAHLD(n) ((n) << 30)
#define STM32_FMC2_BTRx_BUSTURN(n) ((n) << 16)
#define STM32_FMC2_BTRx_DATAST(n) ((n) << 8)
#define STM32_FMC2_BTRx_ADDHLD(n) ((n) << 4)
#define STM32_FMC2_BTRx_ADDSET(n) ((n) << 0)
#define RCC_MP_AHB6RSTCLRR 0x218
#define RCC_MP_AHB6RSTCLRR_FMCRST BIT(12)
#define RCC_MP_AHB6ENSETR 0x19c
#define RCC_MP_AHB6ENSETR_FMCEN BIT(12)
const u32 bcr = STM32_FMC2_BCRx_WREN |STM32_FMC2_BCRx_RSVD |
STM32_FMC2_BCRx_FACCEN | STM32_FMC2_BCRx_MWID(1) |
STM32_FMC2_BCRx_MTYP(2) | STM32_FMC2_BCRx_MUXEN |
STM32_FMC2_BCRx_MBKEN;
const u32 btr = STM32_FMC2_BTRx_DATAHLD(3) |
STM32_FMC2_BTRx_BUSTURN(2) |
STM32_FMC2_BTRx_DATAST(0x22) |
STM32_FMC2_BTRx_ADDHLD(2) |
STM32_FMC2_BTRx_ADDSET(2);
/* Set up FMC2 bus for KS8851-16MLL and X11 SRAM */
writel(RCC_MP_AHB6RSTCLRR_FMCRST, STM32_RCC_BASE + RCC_MP_AHB6RSTCLRR);
writel(RCC_MP_AHB6ENSETR_FMCEN, STM32_RCC_BASE + RCC_MP_AHB6ENSETR);
/* KS8851-16MLL -- Muxed mode */
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(1));
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(1));
/* AS7C34098 SRAM on X11 -- Muxed mode */
writel(bcr, STM32_FMC2_BASE + STM32_FMC2_BCR(3));
writel(btr, STM32_FMC2_BASE + STM32_FMC2_BTR(3));
setbits_le32(STM32_FMC2_BASE + STM32_FMC2_BCR1, STM32_FMC2_BCRx_FMCEN);
}
/* board dependent setup after realloc */
int board_init(void)
{
@ -398,7 +448,9 @@ int board_init(void)
sysconf_init();
if (CONFIG_IS_ENABLED(CONFIG_LED))
board_init_fmc2();
if (CONFIG_IS_ENABLED(LED))
led_default_state();
return 0;

6
board/st/stm32mp1/stm32mp1.c
View File

@ -92,7 +92,7 @@ int checkboard(void)
if (IS_ENABLED(CONFIG_STM32MP1_OPTEE))
mode = "trusted with OP-TEE";
else if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
else if (IS_ENABLED(TFABOOT))
mode = "trusted";
else
mode = "basic";
@ -462,7 +462,7 @@ static int board_check_usb_power(void)
static void sysconf_init(void)
{
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
u8 *syscfg;
#ifdef CONFIG_DM_REGULATOR
struct udevice *pwr_dev;
@ -647,7 +647,7 @@ int board_init(void)
sysconf_init();
if (CONFIG_IS_ENABLED(CONFIG_LED))
if (CONFIG_IS_ENABLED(LED))
led_default_state();
return 0;

3
configs/stm32mp15_basic_defconfig
View File

@ -21,10 +21,7 @@ CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_POWER_SUPPORT=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMINFO=y

1
configs/stm32mp15_dhcom_basic_defconfig
View File

@ -93,6 +93,7 @@ CONFIG_SPI_FLASH_MTD=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_DM_ETH=y
CONFIG_DWC_ETH_QOS=y
CONFIG_KS8851_MLL=y
CONFIG_PHY=y
CONFIG_PHY_STM32_USBPHYC=y
CONFIG_PINCONF=y

1
configs/stm32mp15_optee_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_ENV_OFFSET=0x280000

4
configs/stm32mp15_trusted_defconfig
View File

@ -1,5 +1,6 @@
CONFIG_ARM=y
CONFIG_ARCH_STM32MP=y
CONFIG_TFABOOT=y
CONFIG_SYS_MALLOC_F_LEN=0x3000
CONFIG_ENV_SECT_SIZE=0x40000
CONFIG_ENV_OFFSET=0x280000
@ -9,10 +10,7 @@ CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_BOOTCOMMAND="run bootcmd_stm32mp"
CONFIG_SYS_PROMPT="STM32MP> "
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_ELF is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EXPORTENV is not set
# CONFIG_CMD_IMPORTENV is not set
CONFIG_CMD_MEMINFO=y

2
drivers/clk/clk_stm32mp1.c
View File

@ -19,7 +19,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
/* activate clock tree initialization in the driver */
#define STM32MP1_CLOCK_TREE_INIT

72
drivers/net/dwc_eth_qos.c
View File

@ -306,6 +306,8 @@ struct eqos_priv {
struct clk clk_slave_bus;
struct mii_dev *mii;
struct phy_device *phy;
int phyaddr;
u32 max_speed;
void *descs;
struct eqos_desc *tx_descs;
struct eqos_desc *rx_descs;
@ -694,6 +696,29 @@ static int eqos_start_resets_tegra186(struct udevice *dev)
static int eqos_start_resets_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
debug("%s(dev=%p):\n", __func__, dev);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
ret);
return ret;
}
udelay(2);
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 0);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, deassert) failed: %d",
ret);
return ret;
}
}
debug("%s: OK\n", __func__);
return 0;
}
@ -709,6 +734,18 @@ static int eqos_stop_resets_tegra186(struct udevice *dev)
static int eqos_stop_resets_stm32(struct udevice *dev)
{
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
ret = dm_gpio_set_value(&eqos->phy_reset_gpio, 1);
if (ret < 0) {
pr_err("dm_gpio_set_value(phy_reset, assert) failed: %d",
ret);
return ret;
}
}
return 0;
}
@ -1046,12 +1083,21 @@ static int eqos_start(struct udevice *dev)
* don't need to reconnect/reconfigure again
*/
if (!eqos->phy) {
eqos->phy = phy_connect(eqos->mii, -1, dev,
eqos->phy = phy_connect(eqos->mii, eqos->phyaddr, dev,
eqos->config->interface(dev));
if (!eqos->phy) {
pr_err("phy_connect() failed");
goto err_stop_resets;
}
if (eqos->max_speed) {
ret = phy_set_supported(eqos->phy, eqos->max_speed);
if (ret) {
pr_err("phy_set_supported() failed: %d", ret);
goto err_shutdown_phy;
}
}
ret = phy_config(eqos->phy);
if (ret < 0) {
pr_err("phy_config() failed: %d", ret);
@ -1604,6 +1650,7 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
struct eqos_priv *eqos = dev_get_priv(dev);
int ret;
phy_interface_t interface;
struct ofnode_phandle_args phandle_args;
debug("%s(dev=%p):\n", __func__, dev);
@ -1618,6 +1665,8 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
if (ret)
return -EINVAL;
eqos->max_speed = dev_read_u32_default(dev, "max-speed", 0);
ret = clk_get_by_name(dev, "stmmaceth", &eqos->clk_master_bus);
if (ret) {
pr_err("clk_get_by_name(master_bus) failed: %d", ret);
@ -1641,6 +1690,24 @@ static int eqos_probe_resources_stm32(struct udevice *dev)
if (ret)
pr_warn("No phy clock provided %d", ret);
eqos->phyaddr = -1;
ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args);
if (!ret) {
/* search "reset-gpios" in phy node */
ret = gpio_request_by_name_nodev(phandle_args.node,
"reset-gpios", 0,
&eqos->phy_reset_gpio,
GPIOD_IS_OUT |
GPIOD_IS_OUT_ACTIVE);
if (ret)
pr_warn("gpio_request_by_name(phy reset) not provided %d",
ret);
eqos->phyaddr = ofnode_read_u32_default(phandle_args.node,
"reg", -1);
}
debug("%s: OK\n", __func__);
return 0;
@ -1704,6 +1771,9 @@ static int eqos_remove_resources_stm32(struct udevice *dev)
if (clk_valid(&eqos->clk_ck))
clk_free(&eqos->clk_ck);
if (dm_gpio_is_valid(&eqos->phy_reset_gpio))
dm_gpio_free(dev, &eqos->phy_reset_gpio);
debug("%s: OK\n", __func__);
return 0;
}

2
drivers/ram/stm32mp1/stm32mp1_ram.c
View File

@ -177,7 +177,7 @@ static int stm32mp1_ddr_probe(struct udevice *dev)
priv->info.base = STM32_DDR_BASE;
#if !defined(CONFIG_STM32MP1_TRUSTED) && \
#if !defined(CONFIG_TFABOOT) && \
(!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
priv->info.size = 0;
return stm32mp1_ddr_setup(dev);

2
include/configs/stm32mp1.h
View File

@ -10,7 +10,7 @@
#include <linux/sizes.h>
#include <asm/arch/stm32.h>
#ifndef CONFIG_STM32MP1_TRUSTED
#ifndef CONFIG_TFABOOT
/* PSCI support */
#define CONFIG_ARMV7_PSCI_1_0
#define CONFIG_ARMV7_SECURE_BASE STM32_SYSRAM_BASE