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ppc/8xxx: Misc DDR related fixes

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* Fix setting of ESDMODE (MR1) register - the bit shifting was wrong
* Fix the format string to match size in a debug print

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
2009-09-10 14:54:55 -05:00
committed by Tom Rix
parent f761439418
commit 6690dcc173
2 changed files with 7 additions and 7 deletions
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4
cpu/mpc8xxx/ddr/ddr3_dimm_params.c
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@@ -1,5 +1,5 @@
/*
* Copyright (C) 2008 Freescale Semiconductor, Inc.
* Copyright 2008-2009 Freescale Semiconductor, Inc.
* Dave Liu <daveliu@freescale.com>
*
* calculate the organization and timing parameter
@@ -71,7 +71,7 @@ compute_ranksize(const ddr3_spd_eeprom_t *spd)
bsize = 1ULL << (nbit_sdram_cap_bsize - 3
+ nbit_primary_bus_width - nbit_sdram_width);
debug("DDR: DDR III rank density = 0x%08x\n", bsize);
debug("DDR: DDR III rank density = 0x%16lx\n", bsize);
return bsize;
}